Datasheet TLC5628IN, TLC5628IDWR, TLC5628CN, TLC5628CDWR, TLC5628CDW Datasheet (Texas Instruments)

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Page 1

TLC5628C, TLC5628I

OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Eight 8-Bit Voltage Output DACs

5-V Single-Supply Operation

Serial Interface

High-Impedance Reference Inputs

Programmable 1 or 2 Times Output Range

Simultaneous Update Facility

Internal Power-On Reset

Low-Power Consumption

Half-Buffered Output

applications

Programmable V oltage Sources

Digitally Controlled Amplifiers/Attenuators

Mobile Communications

Automatic Test Equipment

Process Monitoring and Control

Signal Synthesis

description

The TLC5628C and TLC5628I are octal 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two times the reference voltages and GND and are monotonic. The device is simple to use, running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up conditions.

Digital control of the TLC5628C and TLC5628I are over a simple three-wire serial bus that is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 12-bit command word comprises eight bits of data, three DAC select bits, and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital inputs feature Schmitt triggers for high-noise immunity.

The 16-terminal small-outline (D) package allows digital control of analog functions in space-critical applications. The TLC5628C is characterized for operation from 0°C to 70°C. The TLC5628I is characterized for operation from –40°C to 85°C. The TLC5628C and TLC5628I do not require external trimming.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(DW)

PLASTIC DIP

(N)

0°C to 70°C TLC5628CDW TLC5628CN

–40°C to 85°C TLC5628IDW TLC5628IN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

DACB DACA

GND

DATA

CLK V

DACE DACF

DACC DACD REF1 LDAC LOAD REF2 DACH DACG

N OR DW PACKAGE

(TOP VIEW)

Page 2

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Serial

Interface

× 2

DAC

× 2

DAC

× 2

LDAC

REF1

+ –

REF2

CLK

DATA

LOAD

DACA

DACD

DACE

DACH

LatchLatch

Latch Latch

LatchLatch

Latch Latch

Power-On

Reset

5 4 12

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

CLK 5 I Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock

applied to the CLK terminal. DACA 2 O DAC A analog output DACB 1 O DAC B analog output DACC 16 O DAC C analog output DACD 15 O DAC D analog output DACE 7 O DAC E analog output DACF 8 O DAC F analog output DACG 9 O DAC G analog output DACH 10 O DAC H analog output DATA 4 I Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially.

Each data bit is clocked into the register on the falling edge of the clock signal. GND 3 I Ground return and reference terminal LDAC 13 I Load DAC. When LDAC is high, no DAC output updates occur when the input digital data is read into the serial

interface. The DAC outputs are only updated when LDAC is taken from high to low. LOAD 12 I Serial interface load control. When LDAC is low, the falling edge of the LOAD signal latches the digital data into

the output latch and immediately produces the analog voltage at the DAC output terminal. REF1 14 I Reference voltage input to DAC ABCD. This voltage defines the analog output range. REF2 11 I Reference voltage input to DAC EFGH. This voltage defines the analog output range. V

6 I Positive supply voltage

Page 3

TLC5628C, TLC5628I

OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

The TLC5628 is implemented using eight resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in T able 1. One end of each resistor string is connected to GND and the other end is fed from the output of the reference input buffer . Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance load to the reference sources. There are two input reference terminals; REF1 is used for DACA through DACD and REF2 is used by DACE through DACH.

Each DAC output is buffered by a configurable-gain output amplifier , that can be programmed to times 1 or times 2 gain.

On power up, the DACs are reset to CODE 0. Each output voltage is given by:

VO(DACA|B|C|D|E|F|G|H)+REF

CODE

256

(1)

RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal Output Transfer

D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE

0 0 0 0 0 0 0 0 GND 0 0000001 (1/256) × REF (1+RNG)

• ••••••• •

0 1111111 (127/256) × REF (1+RNG) 1 0000000 (128/256) × REF (1+RNG)

• ••••••• •

• ••••••• • 1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG)

data interface

With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low . When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit (MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4.

A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0

DAC Update

CLK

DATA

LOAD

su(DATA-CLK)

v(DATA-CLK)

su(CLK-LOAD)

w(LOAD)

su(LOAD-CLK)

Figure 1. LOAD-Controlled Update (LDAC = Low)

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TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

data interface (continued)

CLK

DATA

LOAD

LDAC

DAC Update

A2 A1 A0 RNG D7 D6 D5 D4 D2 D1 D0

su(DATA-CLK)

v(DATA-CLK)

w(LDAC)

su(LOAD–LDAC)

Figure 2. LDAC-Controlled Update

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

CLK

DATA

LOAD

LDAC

CLK Low

Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low)

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

CLK

DATA

LOAD

LDAC

CLK Low

Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word

T able 2 lists the A2, A1, and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG = low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode

A2 A1 A0 DAC UPDATED

0 0 0 DACA 0 0 1 DACB 0 1 0 DACC 0 1 1 DACD 1 0 0 DACE 1 0 1 DACF 1 1 0 DACG 1 1 1 DACH

Page 5

TLC5628C, TLC5628I

OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

linearity, offset, and gain error using single-end supplies

When an amplifier is operated from a single supply , the voltage offset can still be either positive or negative. With a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground.

The output voltage remains at 0 V until the input code value produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in the transfer function shown in Figure 5.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 5. Effect of Negative Offset (Single Supply)

This offset error , not the linearity error, produces the breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below ground.

For a DAC, linearity is measured between the zero-input code (all inputs are 0) and the full-scale code (all inputs are 1) after offset and full scale are adjusted out or accounted for in some way . However, single-supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity in the unipolar mode is measured between full-scale code and the lowest code that produces a positive output voltage.

The code is calculated from the maximum specification for the negative offset voltage.

Page 6

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent of inputs and outputs

GND

ref

Input

To DAC Resistor String

_ +

DAC Voltage Output

SINK

60 µA Typical

84 kΩ

× 1

× 2

Output

Range Select

Input from

Decoded DAC

INPUT CIRCUIT OUTPUT CIRCUIT

GND

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD – GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range, VID GND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range GND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLC5628C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC5628I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–50°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.75 5.25 V

High-level voltage, V

0.8 V

Low-level voltage, V

0.8 V

Reference voltage, V

ref

[A|B|C|D|E|F|G|H] VDD–1.5 V Analog full-scale output voltage, RL = 10 kΩ 3.5 V Load resistance, R

10 kΩ

Setup time, data input, t

su(DATA-CLK)

(see Figures 1 and 2) 50 ns

Valid time, data input valid after CLK↓, t

v(DATA-CLK)

(see Figures 1 and 2) 50 ns

Setup time, CLK eleventh falling edge to LOAD, t

su(CLK-LOAD)

(see Figure 1) 50 ns

Setup time, LOAD↑ to CLK↓, t

su(LOAD-CLK)

(see Figure 1) 50 ns

Pulse duration, LOAD, t

w(LOAD)

(see Figure 1) 250 ns

Pulse duration, LDAC, t

w(LDAC)

(see Figure 2) 250 ns

Setup time, LOAD↑ to LDAC↓, t

su(LOAD-LDAC)

(see Figure 2) 0 ns

CLK frequency 1 MHz

TLC5628C 0 70 °C

Operating free-air temperature, T

TLC5628I –40 85 °C

Page 7

TLC5628C, TLC5628I

OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, V

ref

= 2 V, × 1 gain output range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input current VI = V

±10 µA

Low-level input current VI = 0 V ±10 µA

O(sink)

Output sink current

20 µA

O(source)

Output source current

Each DAC output

2 mA

Input capacitance 15

Reference input capacitance 15

Supply current VDD = 5 V 4 mA

ref

Reference input current VDD = 5 V, V

ref

= 2 V ±10 µA

Linearity error (end point corrected) V

ref

= 2 V, × 2 gain (see Note 1) ±1 LSB

Differential-linearity error V

ref

= 2 V, × 2 gain (see Note 2) ±0.9 LSB

Zero-scale error V

ref

= 2 V, × 2 gain (see Note 3) 0 30 mV

Zero-scale-error temperature coefficient V

ref

= 2 V, × 2 gain (see Note 4) 10 µV/°C

Full-scale error V

ref

= 2 V, × 2 gain (see Note 5) ±60 mV

Full-scale-error temperature coefficient V

ref

= 2 V, × 2 gain (see Note 6) ±25 µV/°C

PSRR Power supply rejection ratio See Notes 7 and 8 0.5 mV/V

NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects

of zero code and full-scale errors).

2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

4. Zero-scale-error temperature coefficient is given by: ZSETC = [ZSE(T

max

) – ZSE(T

min

)]/V

ref

× 106/(T

max

– T

min

5. Full-scale error is the deviation from the ideal full-scale output (V

ref

– 1 LSB) with an output load of 10 kΩ.

6. Full-scale error temperature coefficient is given by: FSETC = [FSE(T

max

) – FSE (T

min

)]/V

ref

× 106/(T

max

– T

min

7. Zero-scale-error rejection ratio (ZSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage.

8. Full-scale-error rejection ratio (FSE RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage.

operating characteristics over recommended operating free-air temperature range, VDD = 5 V ± 5%, V

ref

= 2 V, × 1 gain output range (unless otherwise noted)

TEST CONDITIONS MIN TYP MAX UNIT

Output slew rate CL = 100 pF, RL = 10 kΩ 1 V/µs Output settling time To ±0.5 LSB, CL = 100 pF, RL = 10 kΩ, See Note 9 10 µs Large signal bandwidth Measured at –3 dB point 100 kHz Digital crosstalk CLK = 1-MHz square wave measured at DACA-DACD –50 dB Reference feedthrough See Note 10 –60 dB Channel-to-channel isolation See Note 11 –60 dB Reference input bandwidth See Note 12 100 kHz

NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within ±0.5 LSB starting from

an initial output voltage equal to zero.

10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V

ref

input = 1 V dc + 1 Vpp at 10 kHz.

11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with V

ref

input = 1 V dc + 1 Vpp at 10 kHz.

12. Reference bandwidth is the –3 dB bandwidth with an input at V

ref

= 1.25 V dc + 2 Vpp and with a full-scale digital input code.

Page 8

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

10 kΩ

CL = 100 pF

TLC5628

DACA DACB

•

DACH

Figure 6. Slew, Settling Time, and Linearity Measurements

TYPICAL CHARACTERISTICS

Figure 7

024681012141618

t – Time – µs

VDD = 5 V TA = 25°C Code 00 to FF Hex Range = ×2 V

ref

= 2 V

LDAC

– Output Voltage – VV

POSITIVE RISE AND SETTLING TIME

Figure 8

024681012141618

t – Time – µs

LDAC

VDD = 5 V TA = 25°C Code FF to 00 Hex Range = ×2 V

ref

= 2 V

– Output Voltage – V V

NEGATIVE FALL AND SETTLING TIME

Page 9

TLC5628C, TLC5628I

OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 9

3.8

3.4

3.2 3

4.8

3.6

0 102030405060

– DAC Output Voltage – V

4.4

4.2

4.6

DAC OUTPUT VOLTAGE

OUTPUT LOAD

70 80 90 100

RL – Output Load – kΩ

VDD = 5 V, V

ref

= 2.5 V,

Range = 2x

Figure 10

1.5

0.5

0102030405060

2.5

3.5

70 80 90 100

DAC OUTPUT VOLTAGE

OUTPUT LOAD

VDD = 5 V, V

ref

= 3.5 V,

Range = 1x

– DAC Output Voltage – V

RL – Output Load – kΩ

Figure 11

0123

– Output Source Current – mA

OUTPUT SOURCE CURRENT

OUTPUT VOLTAGE

VDD = 5 V TA = 25°C V

ref

= 2 V

Range = ×2 Input Code = 255

O(source)

VO – Output Voltage – V

Figure 12

0.9

0.85

0.8

– Supply Current – mA

1.1

1.15

SUPPLY CURRENT

TEMPERATURE

1.2

1.05

0.95

–50 0 50 100

VDD = 5 V V

ref

= 2V

Range = ×2 Input Code = 255

t – Temperature – °C

Page 10

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 13

1 10 100

G – Relative Gain – dB

f – Frequency – kHz

RELATIVE GAIN

FREQUENCY

1000

–2 –4

–6

–8

–10

–12

–14

–16

–18 –20

VDD = 5 V TA = 25°C V

ref

= 1.25 Vdc + 2 V

Input Code = 255

Figure 14

1 10 100 1000

G – Relative Gain – dB

f – Frequency – kHz

RELATIVE GAIN

FREQUENCY

10000

–10

–20

–30

–40

–50

–60

VDD = 5 V TA = 25°C V

ref

= 2 Vdc + 0.5 V

Input Code = 255

APPLICATION INFORMATION

NOTE A: Resistor R w 10 kΩ

TLC5628

DACA DACB

•

DACH

Figure 15. Output Buffering Scheme

Page 11

TLC5628C, TLC5628I

OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PIN SHOWN

4040000/B 03/95

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.293 (7,45)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

(17,78)

0.700

(18,03)

0.710

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

Page 12

TLC5628C, TLC5628I OCTAL 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS089E – NOVEMBER 1994 – REVISED APRIL 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

0.975

(24,77)

0.940

(23,88)

0.920

0.850

0.775

0.745

(19,69)

(18,92)

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

0.310 (7,87)

0.290 (7,37)

(23.37)

(21.59)

Seating Plane

0.010 (0,25) NOM

14/18 PIN ONL Y

4040049/C 08/95

0.070 (1,78) MAX

0.035 (0,89) MAX

0.020 (0,51) MIN

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

0.010 (0,25)

0.100 (2,54)

0°–15°

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001)

Page 13

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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