Datasheet TLC5510, TLC5510A Datasheet (TEXAS INSTRUMENTS)

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Page 1

MAXIMUM FULL-SCALE

20°C to 75°C

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

features

Analog Input Range – TLC5510...2 V Full Scale – TLC5510A...4 V Full Scale

8-Bit Resolution

Integral Linearity Error

±0.75 LSB Max (25°C) ±1 LSB Max (–20°C to 75°C)

Differential Linearity Error

±0.5 LSB Max (25°C) ±0.75 LSB Max (–20°C to 75°C)

Maximum Conversion Rate

20 Mega-Samples per Second (MSPS) Max

description

The TLC5510 and TLC5510A are CMOS, 8-bit, 20 MSPS analog-to-digital converters (ADCs) that utilize a semiflash architecture. The TLC5510 and TLC5510A operate with a single 5-V supply and typically consume only 130 mW of power. Included is an internal sample-and-hold circuit, parallel outputs with high-impedance mode, and internal reference resistors.

The semiflash architecture reduces power consumption and die size compared to flash converters. By implementing the conversion in a 2-step process, the number of comparators is significantly reduced. The latency of the data output valid is 2.5 clocks.

The TLC5510 uses the three internal reference resistors to create a standard, 2-V, full-scale conversion range using V need for external reference resistors. The TLC5510A uses only the center internal resistor section with an externally applied 4-V reference such that a 4-V input signal can be used. Differential linearity is 0.5 LSB at 25°C and a maximum of 0.75 LSB over the full operating temperature range. Typical dynamic specifications include a differential gain of 1% and differential phase of 0.7 degrees.

. Only external jumpers are required to implement this option and eliminates the

DDA

5-V Single-Supply Operation

Low Power Consumption TLC5510 . . . 127.5 mW Typ TLC5510A . . . 150 mW Typ

(includes reference resistor dissipation)

TLC5510 is Interchangeable With Sony CXD1175

applications

Digital TV

Medical Imaging

Video Conferencing

High-Speed Data Conversion

QAM Demodulators

PW OR NS PACKAGE

(TOP VIEW)

DGND

D1(LSB)

D8(MSB)

†

Available in tape and reel only and ordered as the shown in the Available Options table below.

D2 D3 D4 D5 D6 D7

DDD

CLK

2 3 4 5 6 7 8 9 10 11 12

DGND

REFB

REFBS

AGND

ANALOG IN

REFT

REFTS

†

DDA

DDA DDA DDD

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

The TLC5510 and TLC5510A are characterized for operation from –20°C to 75°C.

AVAILABLE OPTIONS

PACKAGE

–

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TSSOP (PW)

TLC5510IPW TLC5510INSLE 2 V

– TLC5510AINSLE 4 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SOP (NS)

(TAPE AND REEL ONLY)

INPUT VOLTAGE

Page 2

TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

functional block diagram

Resistor

Reference

Divider

REFB

270 Ω NOM

REFT

REFBS

AGND AGND

DDA

REFTS

ANALOG IN

CLK

80 Ω NOM

320 Ω NOM

Clock

Generator

Lower Sampling

Comparators

(4-Bit)

Lower Sampling

Comparators

(4-Bit)

Upper Sampling

Comparators

(4-Bit)

Lower Encoder

(4-Bit)

Lower Encoder

(4-Bit)

Upper Encoder

(4-Bit)

Lower Data

Latch

Upper Data

Latch

D1(LSB) D2 D3 D4

D5 D6 D7 D8(MSB)

schematics of inputs and outputs

EQUIVALENT OF ANALOG INPUT

DDA

ANALOG IN

AGND

EQUIVALENT OF EACH DIGITAL INPUT

OE, CLK

DDD

DGND

EQUIVALENT OF EACH DIGITAL OUTPUT

DDD

D1–D8

DGND

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Page 3

I/O

DESCRIPTION

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

Terminal Functions

TERMINAL

NAME NO.

AGND 20, 21 Analog ground ANALOG IN 19 I Analog input CLK 12 I Clock input DGND 2, 24 Digital ground D1–D8 3–10 O Digital data out. D1 = LSB, D8 = MSB OE 1 I Output enable. When OE = low, data is enabled. When OE = high, D1–D8 is in high-impedance state. V

DDA

DDD

REFB 23 I Reference voltage in bottom REFBS 22 Reference voltage in bottom. When using the TLC5510 internal voltage divider to generate a nominal 2-V

REFT 17 I Reference voltage in top REFTS 16 Reference voltage in top. When using the TLC5510 internal voltage divider to generate a nominal 2-V

14, 15, 18 Analog supply voltage

11, 13 Digital supply voltage

reference, REFBS is shorted to REFB (see Figure 3). When using the TLC5510A, REFBS is connected to ground.

reference, REFTS is shorted to REFT (see Figure 3). When using the TLC5510A, REFTS is connected to V

DDA

, V

†

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDD

I(ANLG)

I(DGTL)

O(DGTL)

stg

, V

REFT

AGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGND to V

AGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REFB

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings

Supply voltage, V Reference voltage input range, V Analog input voltage range, V Digital input voltage range, V Digital output voltage range, V Operating free-air temperature range, T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DDA

recommended operating conditions

MIN NOM MAX UNIT

–AGND 4.75 5 5.25

DDA

Supply voltage

Reference input voltage (top), V Reference input voltage (bottom), V Analog input voltage range, V High-level input voltage, V Low-level input voltage, V Pulse duration, clock high, t Pulse duration, clock low, t

‡

The reference voltage levels for the TLC5510 are derived through an internal resistor divider between V derived from a separate external voltage source (see the electrical characteristics and text). For the 4 V input range of the TLC5510A, the reference voltage is externally applied across the center divider resistor.

w(H)

w(L)

‡

ref(T)

I(ANLG)

(see Figure 1) 25 ns

ref(B)

‡

–AGND 4.75 5 5.25

DDD

AGND–DGND –100 0 100 mV TLC5510A V TLC5510A 0 V

+2 4 V

REFB

REFT

REFB

4 V

and ground and therefore are not

DDA

REFT

–4 V

1 V

DDA DDA DDD DDD

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Page 4

TLC5510, TLC5510A

Reference voltage current

Short REFB to REFBS

Short REFT to REFTS

TLC5510

(CLK)

Integral nonlinearity (INL)

TLC5510A

(CLK)

LSB

TLC5510

(CLK)

Differential nonlinearity (DNL)

TLC5510A

(CLK)

EZSZero-scale error

EFSFull-scale error

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

electrical characteristics at VDD = 5 V , V

REFT

= 2.5 V , V

REFB

otherwise noted)

digital I/O

PARAMETER TEST CONDITIONS

OZH

OZL

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

power

ref

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

static performance

ref

†

Conditions marked MIN or MAX are as stated in recommended operating conditions.

High-level input current VDD = MAX, VIH = V Low-level input current VDD = MAX, VIL = 0 5 High-level output current OE = GND, VDD = MIN, VOH = VDD–0.5 V –1.5 Low-level output current OE = GND, VDD = MIN, VOL = 0.4 V 2.5 High-level high-impedance-state

output leakage current Low-level high-impedance-state

output leakage current

PARAMETER TEST CONDITIONS

Supply current

PARAMETER TEST CONDITIONS

Self-bias (1), at REFB Self-bias (2), REFT – REFB Self-bias (3), at REFT Short REFB to AGND, Short REFT to REFTS 2.18 2.29 2.4 Reference voltage resistor Between REFT and REFB 190 270 350 Ω Analog input capacitance V

OE = VDD, VDD = MAX VOH = V

OE = VDD, VDD = MIN VOL = 0 16

= 20 MHz, National Television System Committee (NTSC)

(CLK)

ramp wave input, reference resistor dissipation is separate TLC5510 V

TLC5510A V

= 1.5 V + 0.07 V

I(ANLG)

= 20 MHz,

VI = 0.5 V to 2.5 V f

= 20 MHz,

VI = 0 to 4 V f

= 20 MHz,

VI = 0.5 V to 2.5 V f

= 20 MHz,

VI = 0 to 4 V

TLC5510 V TLC5510A V TLC5510 V

TLC5510A V

= REFT – REFB = 2 V –18 –43 –68 mV

ref

= REFT – REFB = 4 V –36 –86 –136 mV

ref

= REFT – REFB = 2 V –20 0 20 mV

ref

= REFT – REFB = 4 V –40 0 40 mV

ref

= REFT – REFB = 2 V 5.2 7.5 10.5 mA

ref

= REFT – REFB = 4 V 10.4 15 21 mA

ref

= 0.5 V , f

†

rms

TA = 25°C ±0.4 ±0.75 TA = –20°C to 75°C ±1 TA = 25°C ±0.4 ±0.75 TA = –20°C to 75°C ±1 TA = 25°C ±0.3 ±0.5 TA = –20°C to 75°C ±0.75 TA = 25°C ±0.3 ±0.5 TA = –20°C to 75°C ±0.75

= 20 MHz, TA = 25°C (unless

(CLK)

MIN TYP MAX UNIT

18 27 mA

MIN TYP MAX UNIT

0.57 0.61 0.65

1.9 2.02 2.15

16 pF

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Page 5

Maximum conversion rate

1-kHz ramp

g()

Input tone

Spurious free dynamic range (SFDR)

Input tone

SNR

Signal-to-noise ratio

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

operating characteristics at VDD = 5 V , V

REFT

= 2.5 V , V

REFB

= 0.5 V , f

= 20 MHz, TA = 25°C (unless

(CLK)

otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

conv

BW Analog input bandwidth At – 1 dB 14 MHz t

Digital output delay time CL ≤ 10 pF (see Note 1 and Figure 1) 18 30 ns

d(D)

Differential gain Differential phase

Aperture jitter time 30 ps

Sampling delay time 4 ns

d(s)

Enable time, OE↓ to valid data CL = 10 pF 5 ns

Disable time, OE↑ to high impedance CL = 10 pF 7 ns

dis

NOTE 1: CL includes probe and jig capacitance.

TLC5510 TLC5510A

NTSC 40 Institute of Radio Engineers (IRE) modulation wave, f

TA = 25°C 46 Full range 44

= 1 MHz

= 3 MHz

= 6 MHz

= 10 MHz

V V

conv

TA = 25°C 45 Full range 43 TA = 25°C 45 Full range 46 TA = 25°C 43 Full range 42 TA = 25°C 39 Full range 39

= 0.5 V – 2.5 V 20 MSPS

I(ANLG)

= 0 V – 4 V 20 MSPS

I(ANLG)

= 14.3 MSPS

0.7 degrees

CLK (clock)

ANALOG IN

(input signal)

D1–D8

(output data)

w(H)

d(s)

w(L)

N–3 N–2 N–1 N N+1

d(D)

N+1

N+2

N+3

N+4

Figure 1. I/O Timing Diagram

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Page 6

TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

PRINCIPLES OF OPERATION

functional description

The TLC5510 and TLC5510A are semiflash ADCs featuring two lower comparator blocks of four bits each. As shown in Figure 2, input voltage V

(1) is sampled with the falling edge of CLK1 to the upper comparators block

and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1) with the rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1) corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shown in Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point.

Input voltage V

(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and

LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) data appears with the rising edge of CLK5.

VI(1) VI(2) VI(3) VI(4)

ANALOG IN

(sampling points)

CLK5

CLK (clock)

Upper Comparators Block

Upper Data

CLK1 CLK2 CLK3 CLK4

S(1) C(1) S(2) C(2) S(3) C(3) S(4) C(4)

UD(0)

UD(1)

UD(2)

UD(3)

Lower Reference Voltage

Lower Comparators Block (A)

Lower Data (A)

Lower Comparators Block (B)

Lower Data (B)

D1–D8 (data output)

RV(0)

S(1) H(1) C(1) S(3) H(3) C(3)

LD(–1)

H(0) C(0) S(2) H(2) C(2) S(4) H(4)

LD(–2)

OUT(–2) OUT(–1) OUT(0) OUT(1)

RV(1)

RV(2)

LD(1)

LD(0)

Figure 2. Internal Functional Timing Diagram

RV(3)

LD(2)

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Page 7

internal referencing

TLC5510

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

PRINCIPLES OF OPERATION

The three internal resistors shown with V out on V

, REFTS, REFT, REFB, REFBS, and AGND.

DDA

can generate a 2-V reference voltage. These resistors are brought

DDA

T o use the internally generated reference voltage, terminal connections should be made as shown in Figure 3. This connection provides the standard video 2-V reference for the nominal digital output.

TLC5510

REFT

16 17

R1 320 Ω NOM

ref

270 Ω NOM

R2 80 Ω NOM

(analog supply)

DDA

REFTS

REFBS

REFB

AGND

Figure 3. External Connections for a 2-V Analog Input Span Using the Internal-Reference Resistor Divider

TLC5510A

For an analog input span of 4 V , 4 V is supplied to REFT , and REFB is grounded and terminal connections should be made as shown in Figure 4. This connection provides the 4-V reference for the nominal zero to full-scale digital output with a 4 V

(analog supply)

analog input at ANALOG IN.

DDA

AGND

REFTS

4 V

REFB

REFBS

16 17

REFT

TLC5510A

R1 320 Ω NOM

ref

270 Ω NOM

R2 80 Ω NOM

Figure 4. External Connections for 4-V Analog Input Span

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Page 8

TLC5510, TLC5510A

INPUT SIGNAL

STEP

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

PRINCIPLES OF OPERATION

functional operation

The output code change with input voltage is shown in Table 1.

Table 1. Functional Operation

INPUT SIGNAL

VOLTAGE

ref(B)

•

• • ••••••••

• 128 0 1111111

• 127 1 0000000

• • • •••••••

• • ••••••••

ref(T)

255 0 0 0 0 0 0 0 0

MSB LSB

• • •••••••

0 1 1 1 1 1 1 1 1

DIGITAL OUTPUT CODE

APPLICATION INFORMATION

The following notes are design recommendations that should be used with the device.

External analog and digital circuitry should be physically separated and shielded as much as possible to reduce system noise.

RF breadboarding or printed-circuit-board (PCB) techniques should be used throughout the evaluation and production process. Breadboards should be copper clad for bench evaluation.

Since AGND and DGND are connected internally , the ground lead in must be kept as noise free as possible. A good method to use is twisted-pair cables for the supply lines to minimize noise pickup. An analog and digital ground plane should be used on PCB layouts when additional logic devices are used. The AGND and DGND terminals of the device should be tied to the analog ground plane.

to AGND and V

DDA

to DGND should be decoupled with 1-µF and 0.01-µF capacitors, respectively ,

DDD

and placed as close as possible to the affected device terminals. A ceramic-chip capacitor is recommended for the 0.01-µF capacitor. Care should be exercised to ensure a solid noise-free ground connection for the analog and digital ground terminals.

, AGND, and ANALOG IN should be shielded from the higher frequency terminals, CLK and D0–D7.

DDA

When possible, AGND traces should be placed on both sides of the ANALOG IN traces on the PCB for shielding.

In testing or application of the device, the resistance of the driving source connected to the analog input should be 10 Ω or less within the analog frequency range of interest.

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Page 9

Video

Input

5 V

R4 R2

TP1

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

APPLICATION INFORMATION

REF

ADJ

C11

FB3

FB2

FB7

FB1

JP2JP1

C12

TLC5510, TLC5510A

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

DV 5 V

TLC5510

CLK

DDD

C11

REFTS

REFT

ANALOG IN

AGND

DDD

DDA

D8 (MSB)

Clock

– 5 V

NOTE A: Shorting JP1 and JP3 allows adjustment of the reference voltage by R5 using temperature-compensating diodes D2 and D3

which compensate for D1 and Q1 variations. By shorting JP2 and JP4, the internal divider generates a nominal 2-V reference.

C1, C3–C4, C6–C12 0.1-µF capacitor

FB1, FB2, FB3, FB7 Ferrite bead

TP3

LOCATION DESCRIPTION

C2 10-pF capacitor C5 47-µF capacitor

Q1 2N3414 or equivalent

R1, R3 75-Ω resistor

R2 500-Ω resistor R4 10-kΩ resistor, clamp voltage adjust R5 300-Ω resistor, reference-voltage fine adjust

JP4JP3

C10

AGND

REFBS

REFB

DGND

D1 (LSB)

DGND

Output Enable

Figure 5. TLC5510 Evaluation and Test Schematic

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Page 10

TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

APPLICATION INFORMATION

5 V

REF

Video

Input

R4 R2

ADJ

TP1

C11

FB3

FB2

FB7

FB1

REFTS

REFT

ANALOG IN

AGND

TLC5510A

DDD

DDA

CLK

DDD

D8 (MSB)

C11

DV 5 V

Clock

AGND

REFBS

REFB

DGND

D1 (LSB)

– 5 V

NOTE A: R5 allows adjustment of the reference voltage to 4 V. R4 adjusts for the desired Q1 quiescent operating point.

LOCATION

C1, C3–C4, C6–C1 1 0.1-µF capacitor

C2 10-pF capacitor C5 47-µF capacitor

FB1, FB2, FB3, FB7 Ferrite bead

Q1 2N3414 or equivalent

R1, R3 75-Ω resistor

R2 500-Ω resistor R4 10-kΩ resistor, clamp voltage adjust R5 300-Ω resistor, reference-voltage fine adjust

DESCRIPTION

DGND

Output Enable

Figure 6. TLC5510A Evaluation and Test Schematic

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Page 11

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

APPLICATION INFORMATION

5 V

0.1 µF4.7 µF

1 kΩ

THS3001

681 Ω

FB3

FB1

CLOCK

TLC5510

CLOCK

ANALOG IN

DDA

REFTS REFT

REFBS REFB

4.7 µF

0.1 µF

4.7 µF

49.9 Ω

0.1 µF

4.7 µF

0.1 µF

100 pF

0.1 µF

+ _

681 Ω

†

0.1 µF

4.7 µF

D1 D2 D3 D4 D5 D6 D7 D8

DDD

DGND DGND

0.1 µF

To Processor

0.1 µF

5 V

4.7 µF

49.9 Ω

– 5V

1 kΩ

4.7 µF

10 kΩ POT

4.7 µF

0.1 µF

4.7 µF

†

FB – Ferrite Bead

AGND AGND

Figure 7. TLC5510 Application Schematic

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Page 12

TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

APPLICATION INFORMATION

5 V

0.1 µF4.7 µF

FB1

FB3

1 kΩ

681 Ω

†

AD8001

4.7 µF

+ _

0.1 µF

681 Ω

4.7 µF

ref

4 V

4.7 µF

0.1 µF

49.9 Ω

4.7 µF

CLOCK

100 pF

0.1 µF

49.9 Ω

– 5 V

1 kΩ

4.7 µF

10 kΩ POT

4.7 µF

0.1 µF

TLC5510A

CLOCK

ANALOG IN

DDA

REFTS REFT

REFBS REFB

D1 D2 D3 D4 D5 D6 D7 D8

DDD

DGND DGND

0.1 µF

To Processor

0.1 µF

5 V

4.7 µF

†

FB – Ferrite Bead

AGND AGND

Figure 8. TLC5510A Application Schematic

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Page 13

TLC5510, TLC5510A

8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

0,30

0,19

4,50 4,30

PINS **

Seating Plane

0,15

0,05

DIM

6,60 6,20

0,10

0,15 NOM

2016

0°–8°

Gage Plane

0,25

0,75 0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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Page 14

TLC5510, TLC5510A 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

SLAS095K – SEPTEMBER 1994 – REVISED MA Y 1999

MECHANICAL DATA

NS (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

1,27

PINS **

DIM

0,51 0,35

5,60 5,00

0,25

8,20 7,40

A MAX

A MIN

10,501410,50

9,90 9,90

0,15 NOM

Gage Plane

0°–10°

20 24

15,3012,90

12,30 14,70

0,25

1,05 0,55

2,00 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

0,05 MIN

Seating Plane

0,10

4040062/B 2/95

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IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

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