Datasheet TLC549IP, TLC549IDR, TLC549ID, TLC549CP, TLC549CDR Datasheet (Texas Instruments)

TLC548C, TLC548I, TLC549C, TLC549I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

D

Microprocessor Peripheral or Standalone
Operation

D

8-Bit Resolution A/D Converter

D

Differential Reference Input Voltages

D

Conversion Time ...17 µs Max

D

Total Access and Conversion Cycles Per
Second

– TLC548...up to 45500
– TLC549...up to 40000

D

On-Chip Software-Controllable
Sample-and-Hold Function

D

Total Unadjusted Error...±0.5 LSB Max

D

4-MHz Typical Internal System Clock

D

Wide Supply Range...3 V to 6 V

D

Low Power Consumption...15 mW Max

D

Ideal for Cost-Effective, High-Performance
Applications including Battery-Operated
Portable Instrumentation

D

Pinout and Control Signals Compatible
With the TLC540 and TLC545 8-Bit A/D
Converters and with the TLC1540 10-Bit
A/D Converter

D

CMOS Technology

description

REF+

ANALOG IN

REF–

GND

D OR P PACKAGE

(TOP VIEW)

1
2
3
4

V

8

I/O CLOCK

7

DATA OUT

6

CS

5

CC

The TLC548 and TLC549 are CMOS analog-to-digital converter (ADC) integrated circuits built around an 8-bit
switched-capacitor successive-approximation ADC. These devices are designed for serial interface with a
microprocessor or peripheral through a 3-state data output and an analog input. The TLC548 and TLC549 use
only the input/output clock (I/O CLOCK) input along with the chip select (CS

) input for data control. The
maximum I/O CLOCK input frequency of the TLC548 is 2.048 MHz, and the I/O CLOCK input frequency of the
TLC549 is specified up to 1.1 MHz.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SMALL OUTLINE

(D)

TLC548CD
TLC549CD

TLC548ID
TLC549ID

PLASTIC DIP

(P)

TLC548CP
TLC549CP

TLC548IP
TLC549IP

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

description (continued)

Operation of the TLC548 and the TLC549 is very similar to that of the more complex TLC540 and TLC541
devices; however, the TLC548 and TLC549 provide an on-chip system clock that operates typically at 4 MHz
and requires no external components. The on-chip system clock allows internal device operation to proceed
independently of serial input/output data timing and permits manipulation of the TLC548 and TLC549 as desired
for a wide range of software and hardware requirements. The I/O CLOCK together with the internal system clock
allow high-speed data transfer and conversion rates of 45 500 conversions per second for the TLC548, and
40 000 conversions per second for the TLC549.

Additional TLC548 and TLC549 features include versatile control logic, an on-chip sample-and-hold circuit that
can operate automatically or under microprocessor control, and a high-speed converter with differential
high-impedance reference voltage inputs that ease ratiometric conversion, scaling, and circuit isolation from
logic and supply noises. Design of the totally switched-capacitor successive-approximation converter circuit
allows conversion with a maximum total error of ±0.5 least significant bit (LSB) in less than 17 µs.

The TLC548C and TLC549C are characterized for operation from 0°C to 70°C. The TLC548I and TLC549I are
characterized for operation from –40°C to 85°C.

functional block diagram

CS

1
3

2

5
7

Sample

and

Hold

REF+

REF–

ANALOG IN

I/O CLOCK

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

ANALOG IN

Internal
System

Clock

Ci = 60 pF TYP
(equivalent input
capacitance)

8-Bit

Analog-to

Digital

Converter

(Switched-

Capacitors)

Control

Logic and

Output Counter

8

Output

Data

Regiser

ANALOG IN

8

4

8-to-1 Data

Selector

and

Driver

5 MΩ TYP

6

DATA
OUT

2

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operating sequence

TLC548C, TLC548I, TLC549C, TLC549I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

88765432765432

A7

MSBLSB

Don’t

t

conv

(see Note A)

Hi-Z State

I/O

CLOCK

t

su(CS)

CS

DATA

OUT

t

en

NOTES: A. The conversion cycle, which requires 36 internal system clock periods (17 µs maximum), is initiated with the eighth I/O clock pulse

trailing edge after CS

B. The most significant bit (A7) is automatically placed on the DAT A OUT bus after CS

are clocked out on the first seven I/O clock falling edges. B7–B0 follows in the same manner.

Access
Cycle B

A7 A6 A5 A4 A3 A2 A1 A0

MSB
(see Note B)

Previous Conversion Data A

goes low for the channel whose address exists in memory at the time.

Sample
Cycle B

t

wH(CS)

Care

t

en

11

Access

Cycle C

t

su(CS)

Conversion Data B

is brought low. The remaining seven bits (A6–A0)

Sample
Cycle C

Hi-Z State

B0B1B2B3B4B5B6B7

B7

MSBMSB LSB

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input –0.3 V to V
Output voltage range –0.3 V to V

Peak input current range (any input) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current range (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

(see Note 2): TLC548C, TLC549C 0°C to 70°C. . . . . . . . . . . . .

A

TLC548I, TLC549I –40°C to 85°C. . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTES: 1. All voltage values are with respect to the network ground terminal with the REF– and GND terminals connected together, unless

otherwise noted.

2. The D package is not recommended below –40°C.

CC
CC

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3

TLC548C, TLC548I, TLC549C, TLC549I

UNIT

°C

8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

recommended operating conditions

TLC548 TLC549

MIN NOM MAX MIN NOM MAX

Supply voltage, V
Positive reference voltage, V
Negative reference voltage, V
Differential reference voltage, V
Analog input voltage (see Note 3) 0 V
High-level control input voltage, VIH (for VCC = 4.75 V to 5.5 V) 2 2 V
Low-level control input voltage, VIL (for VCC = 4.75 V to 5.5 V) 0.8 0.8 V
Input/output clock frequency, f
Input/output clock high, t
Input/output clock low, t
Input/output clock transition time, t

(for VCC = 4.75 V to 5.5 V) (see Note 4 and Operating Sequence)
Duration of CS input high state during conversion, t

(for VCC = 4.75 V to 5.5 V) (see Operating Sequence)
Setup time, CS low before first I/O CLOCK, t

(for VCC = 4.75 V to 5.5 V) (see Note 5)
TLC548C, TLC549C 0 70 0 70
TLC548I, TLC549I –40 85 –40 85

NOTES: 3. Analog input voltages greater than that applied to REF+ convert to all ones (11111111), while input voltages less than that applied

CC

(see Note 3) 2.5 VCCVCC+0.1 2.5 VCCVCC+0.1 V

ref+

(see Note 3) –0.1 0 2.5 –0.1 0 2.5 V

ref–

, V

ref+

clock(I/O)

(for VCC = 4.75 V to 5.5 V) 200 404 ns

wH(I/O)

(for VCC = 4.75 V to 5.5 V) 200 404 ns

wL(I/O)

to REF– convert to all zeros (00000000). For proper operation, the positive reference voltage V
the negative reference voltage, V
falls below 4.75 V.

4. This is the time required for the I/O CLOCK input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications in which the sensor and the ADC are placed several feet away from the controlling microprocessor.

5. T o minimize errors caused by noise at the CS
system clock after CS

(see Note 3) 1 VCCVCC+0.2 1 VCCVCC+0.2 V

ref–

(for VCC = 4.75 V to 5.5 V) 0 2.048 0 1.1 MHz

t(I/O)

wH(CS)

su(CS)

. In addition, unadjusted errors may increase as the differential reference voltage, V

ref–

↓ before responding to control input signals. This CS setup time is given by the ten and t

input, the internal circuitry waits for two rising edges and one falling edge of internal

3 5 6 3 5 6 V

CC

100 100 ns

17 17 µs

1.4 1.4 µs

0 V

, must be at least 1 V greater than

ref+

CC

su(CS)

ref+

specifications.

°

– V

V

ref–

,

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IOZHigh-impedance off-state output current

A

I

gg

A

CiInput capacitance

pF

PARAMETER

TEST CONDITIONS

UNIT

TLC548C, TLC548I, TLC549C, TLC549I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

electrical characteristics over recommended operating free-air temperature range,
V

= V

CC

(unless otherwise noted)

V

OH

V

OL

I

IH

I

IL

I(on)

I

CC

ICC + I

ref

= 4.75 V to 5.5 V, f

ref+

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

High-level output voltage VCC = 4.75 V, IOH = –360 µA 2.4 V
Low-level output voltage VCC = 4.75 V, IOL = 3.2 mA 0.4 V

p

High-level input current, control inputs VI = V
Low-level input current, control inputs VI = 0 –0.005 –2.5 µA

Analog channel on-state input current during sample
cycle

Operating supply current CS at 0 V 1.8 2.5 mA
Supply and reference current V

p

p

clock(I/O)

p

= 2.048 MHz for TLC548 or 1.1 MHz for TLC549

VO = VCC, CS at V
VO = 0, CS at V

CC

Analog input at V
Analog input at 0 V

= V

ref+

CC

Analog inputs 7 55
Control inputs 5 15

CC

CC
CC

0.005 2.5 µA

0.4 1

–0.4 –1

1.9 3 mA

10

–10

µ

µ

p

operating characteristics over recommended operating free-air temperature range,
V

CC

= V

= 4.75 V to 5.5 V, f

ref+

clock(I/O)

= 2.048 MHz for TLC548 or 1.1 MHz for TLC549

(unless otherwise noted)

TLC548 TLC549

TYP

†

MAX MIN TYP†MAX

300 300 ns

MIN

E

L

E

ZS

E

FS

t

conv

t

a

t

v

t

d

t

en

t

dis

t

r(bus)

t

f(bus)

†

All typicals are at VCC = 5 V, TA = 25°C.

NOTES: 6. Linearity error is the deviation from the best straight line through the A/D transfer characteristics.

Linearity error See Note 6 ±0.5 ±0.5 LSB
Zero-scale error See Note 7 ±0.5 ±0.5 LSB
Full-scale error See Note 7 ±0.5 ±0.5 LSB
Total unadjusted error See Note 8 ±0.5 ±0.5 LSB
Conversion time See Operating Sequence 8 17 12 17 µs
Total access and conversion time See Operating Sequence 12 22 19 25 µs

Channel acquisition time (sample cycle) See Operating Sequence 4 4

Time output data remains
valid after I/O CLOCK↓

Delay time to data output valid I/O CLOCK↓ 200 400 ns
Output enable time 1.4 1.4 µs
Output disable time 150 150 ns
Data bus rise time
Data bus fall time 300 300 ns

7. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference
between 11111111 and the converted output for full-scale input voltage.

8. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.

See Figure 1

10 10 ns

I/O

clock

cycles

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5

TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

PARAMETER MEASUREMENT INFORMATION

1.4 V

V

CC

Output

Under Test

C

(see Note A)

Output Waveform 1

Output Waveform 2

L

LOAD CIRCUIT FOR

td, tr, AND t

(see Note C)

(see Note C)

CS

3 kΩ

f

Test
Point

Under Test

50%

t

PZL

t

PZH

Output

C

(see Note A)

LOAD CIRCUIT FOR

50%

50%

L

See Note B

t

AND t

PZH

See Note B

PHZ

3 kΩ

Test
Point

50%

t

t

PHZ

PLZ

Output

Under Test

(see Note A)

LOAD CIRCUIT FOR

t

PZL

10%

90%

C

L

See Note B

AND t

PLZ

V

CC

0 V

V

CC

0 V

V

OH

0 V

3 kΩ

Test
Point

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

I/O CLOCK

t

d

DATA OUT

VOLTAGE WAVEFORMS FOR DELAY TIME

NOTES: A. CL = 50 pF for TLC548 and 100 pF for TLC549; CL includes jig capacitance.

B. ten = t
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

PZH

or t

PZL

, t

= t

dis

PHZ

or t

0.8 V

PLZ

Output

t

2.4 V

0.8 V

.

r(bus)

VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES

Figure 1. Load Circuits and Voltage Waveforms

t

f(bus)

2.4 V

0.4 V

6

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simplified analog input analysis

TLC548C, TLC548I, TLC549C, TLC549I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

APPLICATIONS INFORMATION

Using the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

–t

= VS 1–e

V

C

( )

c/RtCi

where

R

= Rs + r

t

i

The final voltage to 1/2 LSB is given by

(1/2 LSB) = VS – (VS/512)

C

Equating equation 1 to equation 2 and solving for time t

–t

–(VS/512) = VS 1–e (3)

V

S

( )

c/RtCi

gives

c

and

t

(1/2 LSB) = Rt × Ci × ln(512) (4)

c

Therefore, with the values given the time for the analog input signal to settle is

t

(1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(512) (5)

c

This time must be less than the converter sample time shown in the timing diagrams.

S

(1)

(2)V

Driving Source

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the

• Rs must be real at the input frequency.

†

R

s

V

S

VI= Input Voltage at ANALOG IN
VS= External Driving Source Voltage
Rs= Source Resistance
ri= Input Resistance
Ci= Input Capacitance

resolution of the converter.

V

I

r

i

1 kΩ MAX

TLC548/9

V

C

C

i

55 pF MAX

Figure 2. Equivalent Input Circuit Including the Driving Source

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7

TLC548C, TLC548I, TLC549C, TLC549I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

PRINCIPLES OF OPERATION

The TLC548 and TLC549 are each complete data acquisition systems on a single chip. Each contains an internal
system clock, sample-and-hold function, 8-bit A/D converter, data register, and control logic circuitry. For flexibility
and access speed, there are two control inputs: I/O CLOCK and chip select (CS
TTL-compatible 3-state output facilitate serial communications with a microprocessor or minicomputer. A conversion
can be completed in 17 µs or less, while complete input-conversion-output cycles can be repeated in 22 µs for the
TLC548 and in 25 µs for the TLC549.

The internal system clock and I/O CLOCK are used independently and do not require any special speed or phase
relationships between them. This independence simplifies the hardware and software control tasks for the device.
Due to this independence and the internal generation of the system clock, the control hardware and software need
only be concerned with reading the previous conversion result and starting the conversion by using the I/O clock. In
this manner, the internal system clock drives the “conversion crunching” circuitry so that the control hardware and
software need not be concerned with this task.

). These control inputs and a

When CS
allows I/O CLOCK to share the same control logic point with its counterpart terminal when additional TLC548 and
TLC549 devices are used. This also serves to minimize the required control logic terminals when using multiple
TLC548 and TLC549 devices.

The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain
the conversion result. A normal control sequence is:

is high, DA TA OUT is in a high-impedance condition and I/O CLOCK is disabled. This CS control function

1. CS

2. The falling edges of the first four I/O CLOCK cycles shift out the second, third, fourth, and fifth most significant

3. Three more I/O CLOCK cycles are then applied to the I/O CLOCK terminal and the sixth, seventh, and eighth

4. The final (the eighth) clock cycle is applied to I/O CLOCK. The on-chip sample-and-hold function begins the

is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges
and then a falling edge of the internal system clock after a CS
upon a CS
rest of the integrated circuitry does not recognize the transition until the specified t
technique protects the device against noise when used in a noisy environment. The most significant bit (MSB)
of the previous conversion result initially appears on DATA OUT when CS

bits of the previous conversion result. The on-chip sample-and-hold function begins sampling the analog
input after the fourth high-to-low transition of I/O CLOCK. The sampling operation basically involves the
charging of internal capacitors to the level of the analog input voltage.

conversion bits are shifted out on the falling edges of these clock cycles.

hold operation upon the high-to-low transition of this clock cycle. The hold function continues for the next four
internal system clock cycles, after which the holding function terminates and the conversion is performed
during the next 32 system clock cycles, giving a total of 36 cycles. After the eighth I/O CLOCK cycle, CS
go high or the I/O clock must remain low for at least 36 internal system clock cycles to allow for the completion
of the hold and conversion functions. CS
keeping CS
glitches on the I/O CLOCK line. If glitches occur on I/O CLOCK, the I/O sequence between the
microprocessor/controller and the device loses synchronization. When CS
until the end of conversion. Otherwise, a valid high-to-low transition of CS
aborts the conversion in progress.

rising edge, DA T A OUT goes to a high-impedance state within the specified t

can be kept low during periods of multiple conversion. When

low during periods of multiple conversion, special care must be exercised to prevent noise

↓ before the transition is recognized. However ,

even though the

dis

has elapsed. This

su(CS)

goes low.

must

is taken high, it must remain high

causes a reset condition, which

A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through
4 before the 36 internal system clock cycles occur. Such action yields the conversion result of the previous conversion
and not the ongoing conversion.

8

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TLC548C, TLC548I, TLC549C, TLC549I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS067C – NOVEMBER 1983 – REVISED SEPTEMBER 1996

PRINCIPLES OF OPERATION

For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time.
This device accommodates these applications. Although the on-chip sample-and-hold function begins sampling
upon the high-to-low transition of the fourth I/O CLOCK cycle, the hold function does not begin until the high-to-low
transition of the eighth I/O CLOCK cycle, which should occur at the moment when the analog signal must be
converted. The TLC548 and TLC549 continue sampling the analog input until the high-to-low transition of the eighth
I/O CLOCK pulse. The control circuitry or software then immediately lowers I/O CLOCK and starts the holding function
to hold the analog signal at the desired point in time and starts the conversion.

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9

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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Copyright  1998, Texas Instruments Incorporated