Datasheet TLC2942IDBR, TLC2942IDBLE Datasheet (Texas Instruments)

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Dual TLC2932 by Multichip Module (MCM)
Technology

D

Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One

External Bias Resistor (R

BIAS

)

– Recommended Lock Frequency Range:

22 MHz to 50 MHz (V

DD

= 5 V ±5%,

T

A

= –20°C to 75°C, ×1 Output)

11 MHz to 25 MHz (V

DD

= 5 V ±5%,

T

A

= –20°C to 75°C, ×1/2 Output)

– Output Frequency...×1 and ×1/2

Selectable

D

Includes a High-Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump

D

Independent VCO, PFD Power-Down Mode

description

The TLC2942 is a multichip module product that
uses two TLC2932 chips. The TLC2932 chip is
composed of a voltage-controlled oscillator and
an edge-triggered phase frequency detector. The
oscillation frequency range of each VCO is set by
an external bias resistor (R

BIAS

) and each VCO output can be a ×1 or ×1/2 output frequency . Each high speed
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. The VCO and the PFD have inhibit functions that can be used as a
power-down mode. The high-speed and stable oscillation capability of the TLC2932 makes the TLC2942
suitable for use in dual high-performance phase-locked loop (PLL) systems.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(DB)

–20°C to 75°C TLC2942IDB

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

LOGIC V

DD1

SELECT1

VCO OUT1

F

IN

–A1

F

IN

–B1

PFD OUT1

LOGIC GND1

GND

NC
NC
NC

GND

LOGIC V

DD2

SELECT2

VCO OUT2

F

IN

–A2

F

IN

–B2

PFD OUT2

LOGIC GND2

VCO V

DD1

BIAS1
VCOIN1
VCO GND1
VCOINHIBIT1
PFD INHIBIT1
NC
GND
NC
NC
NC
GND
VCO V

DD2

BIAS2
VCOIN2
VCO GND2
VCOINHIBIT2
PFD INHIBIT2
NC

DB PACKAGE

(TOP VIEW)

NC – No internal connection

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

SELECT1

SELECT2

VCO_1 VCO_2

PFD_1 PFD_2

VCO

INHIBIT1

VCO

INHIBIT2

VCO OUT1 VCO OUT2

PFD OUT1 PFD OUT2

PFD INHIBIT1 PFD INHIBIT2

VCOIN1

FIN–A1

FIN–B1

VCOIN2

FIN–A2

FIN–B2

34 1523 2214

24

16

17

1833 6 21

36

4

5

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

I/

NAME NO.

O

DESCRIPTION

BIAS1 37 I VCO1 bias supply. An external resistor (R

BIAS

1) between VCO V

DD1

and BIAS1 supplies bias for adjusting

the oscillation frequency range.

BIAS2 25 I VCO2 bias supply. An external resistor (R

BIAS2

) between VCO V

DD2

and BIAS2 supplies bias for adjusting

the oscillation frequency range.
FIN–A1 4 I Input reference frequency 1. The frequency f(REF IN)1 is applied to FIN-A1.
FIN–A2 16 I Input reference frequency 2. The frequency f(REF IN)2 is applied to FIN-A2.
FIN–B1 5 I Input for VCO1 external counter output frequency f(FIN-B)1. FIN-B1 is nominally provided from the external

counter (see Figure 28).
FIN–B2 17 I Input for VCO2 external counter output frequency f(FIN-B)2. FIN-B2 is nominally provided from the external

counter (see Figure 28).
GND 8, 12,

27,31

Ground

LOGIC V

DD1

1 Logic1 supply voltage. LOGIC V

DD1

supplies voltage to internal logic 1. LOGIC V

DD1

should be separate

from the other supply lines to reduce cross-coupling between power supplies.
LOGIC V

DD2

13 Logic2 supply voltage. LOGIC V

DD2

supplies voltage to internal logic 2. LOGIC V

DD2

should be separate

from the other supply lines to reduce cross-coupling between power supplies.
LOGIC GND1 7 Ground for the internal logic 1
LOGIC GND2 19 Ground for the internal logic 2
NC 9, 10, 11,

20, 28,
29, 30,

32

No internal connection

PFD INHIBIT1 33 I PFD inhibit 1 control. When PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state (see

Table 4).
PFD INHIBIT2 21 I PFD inhibit 2 control. When PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state (see

Table 5).
PFD OUT1 6 O PFD1 output. When the PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state.
PFD OUT2 18 O PFD2 output. When the PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state.
SELECT1 2 I VCO1 output frequency select. When SELECT1 is high, the VCO1 output frequency is 1/2 and when

SELECT1 is low, the output frequency is 1 (see Table 1).
SELECT2 14 I VCO2 output frequency select. When SELECT2 is high, the VCO2 output frequency is 1/2 and when

SELECT2 is low, the output frequency is 1 (see Table 1).
VCO GND1 35 Ground for VCO1
VCO GND2 23 Ground for VCO2
VCOINHIBIT1 34 I VCO1 inhibit control. When VCOINHIBIT1 is high, VCO OUT1 is low (see Table 2).
VCOINHIBIT2 22 O VCO2 inhibit control. When VCOINHIBIT2 is high, VCO OUT2 is low (see Table 3).
VCO OUT1 3 O VCO1 output. When VCOINHIBIT1 is high, VCO OUT1 is low.
VCO OUT2 15 VCO2 output. When VCOINHIBIT2 is high, VCO OUT2 is low.
VCO V

DD1

38 VCO1 supply voltage. VCO V

DD1

supplies voltage for VCO1. VCO V

DD1

should be separated from LOGIC

V

DD1

and LOGIC V

DD2

and VCO VDD2 to reduce cross-coupling between power supplies.

VCO V

DD2

26 VCO2 supply voltage. VCO V

DD2

supplies voltage for VCO2. VCO V

DD2

should be separated from LOGIC

V

DD1

and LOGIC V

DD2

and VCO VDD1 to reduce cross-coupling between power supplies.

VCOIN1 36 I VCO1 control voltage input. Nominally the external loop filter output1 connects to VCOIN1 to control VCO1

oscillation frequency .
VCOIN2 24 I VCO2 control voltage input. Nominally the external loop filter output2 connects to VCOIN2 to control VCO2

oscillation frequency .

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

multichip module

The TLC2942 is a multichip module (MCM) product that uses two TLC2932 chips. A newly developed lead frame
for TLC2942IBD is specially shaped and cut in the package to electrically isolate one chip from another. The
two chips are completely independent from each other to perform the best stable oscillation and locking. If
asynchronous locking operation is required for these two PLL blocks, each TLC2942 VCO and PFD can achieve
the same stability as the single chip TLC2932IPW.

Three NC terminals are on both sides of the package between chip1 and chip2 due to the lead frame shape.
To avoid performance degradation, special attention is needed for each PLL block PCB layout especially for
supply voltage lines and GND patterns.

voltage-controlled oscillator (VCO)

VCO1 and VCO2 have the same typical characteristics. Each VCO oscillation frequency is determined by an
external resistor (R

BIAS

) connected between each VCO VDD and BIAS terminals. The oscillation frequency and
range depends on this register value. The bias resistor value for the minimum temperature coefficient is
nominally 3.3 kΩ with V

DD

= 3 V and nominally 2.2 kΩ with VDD = 5 V. For the lock frequency range refer to
the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control
voltage.

VCO Oscillation Frequency Range

Bias Resistor (R

BIAS

)

1/2 V

DD

VCO Control Voltage (VCOIN)

VCO Oscillation Frequency

(f )

osc

Figure 1. VCO1 and VCO2 Oscillation Frequency

VCO output frequency 1/2 divider

SELECT1 and SELECT2 select between f

osc

and 1/2 f

osc

for the VCO output frequencies as shown in T able 1.

Table 1. SELECT1 and SELECT2 Function Table

SELECT1

VCO1 OUTPUT

FREQUENCY

SELECT2

VCO2 OUTPUT

FREQUENCY

Low

f

osc1

Low f

osc2

High

1/2 f

osc1

High 1/2 f

osc2

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

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VCO inhibit function

Each VCO has an externally controlled inhibit function that inhibits the VCO output. The VCO oscillation is
stopped during a high level on VCOINHIBIT , so the high level can also be used as the power-down mode. The
VCO output maintains a low level during the power-down mode (see Table 2 and Table 3).

Table 2. VCO1 Inhibit Function

VCOINHIBIT1 VCO1 OSCILLAT OR VCO OUT1 VCO1 I

DD

Low Active Active Normal
High Stop Low Power Down

Table 3. VCO2 Inhibit Function

VCOINHIBIT2 VCO2 OSCILLAT OR VCO OUT2 VCO2 I

DD

Low Active Active Normal
High Stop Low Power Down

PFD operation

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to F

IN

–A and FIN–B as shown in Figure 2. Nominally the

reference is supplied to F

IN

–A, and the frequency from the external counter output is fed to FIN–B.

FIN–A1,

FIN–A2

FIN–B1,

FIN–B2

PFD OUT1,

PFD OUT2

V

OH

Hi-Z

V

OL

Figure 2. PFD Function Timing Chart

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

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PFD output control

A high level on PFD INHIBIT places the PFD OUT in the high-impedance state and the PFD stops phase
detection as shown in Table 4 and Table 5. A high level on PFD INHIBIT also can be used as the power-down
mode for the PFD.

Table 4. PFD1 Inhibit Function

PFD INHIBIT1 DETECTION PFD OUT1 PFD1 I

DD

Low Active Active Normal

High Stop Hi-Z Power Down

Table 5. PFD2 Inhibit Function Table

PFD INHIBIT2 DETECTION PFD OUT2 PFD2 I

DD

Low Active Active Normal

High Stop Hi-Z Power Down

schematics

VCO block schematic (VCO1, VCO2)

Bias

Circuit

VCO

Output

1/2

R

BIAS

VCOIN1,

VCOIN2

(VCO control)

VCOINHIBIT

VCO OUT1,

VCO OUT2

SELECT1,2

M
U
X

Ring Oscillator

PFD block schematic (PFD1, PFD2)

Detector

Charge Pump

PFD OUT

FIN–A

FIN–B

PFD INHIBIT

V

DD

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (each supply), V

DD

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range (each input), V

I

(see Note 1) –0.5 V to V

DD

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current (each input), I

I

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (each output), I

O

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation, at (or below) T

A

= 25°C (see Note 2) 1160 mW. . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to network GND.

2. For operation above 25°C free-air temperature, derate linearly at the rate of 9.3 mW/°C.

recommended operating conditions

MIN NOM MAX UNIT

pp

pp

VDD = 3 V 2.85 3 3.15

Suppl

y v

oltage, V

DD

(each suppl

y,

see Note 3)

VDD = 5 V 4.75 5 5.25

V

Input voltage, VI, (all inputs except VCOIN1, VCOIN2) 0 V

DD

V
Output current, IO (each output) 0 ±2 mA
VCO control voltage at each VCOIN1, VCOIN2 0.9 V

DD

V

p

VDD = 3 V 14 21

Lock frequenc

y,

(each VCO) (×1 output)

VDD = 5 V 22 50

MH

z

p

VDD = 3 V 7 10.5

Lock frequenc

y,

(each VCO) (×1/2 output)

VDD = 5 V 11 25

MH

z

VDD = 3 V 2.2 3.3 4.3

Bias resistor, (each BIAS), R

BIAS1,

R

BIAS2

VDD = 5 V 1.5 2.2 3.3

kΩ

Operating temperature, T

A

–20 75 °C

NOTE 3: It is recommended that LOGIC V

DD1

and VCO V

DD1

or LOGIC V

DD2

and VCO V

DD2

should be at the same voltage and separated from

each other.

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VCO1, VCO2 electrical characteristics, V

DD

= 3 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage IOH = –2 mA 2.4 V

V

OL

Low-level output voltage IOL = 2 mA 0.3 V

V

IT

Input threshold voltage

SELECT1, SELECT2,
VCOINHIBIT2, VCOINHIBIT1

0.9 1.5 2.1 V

I

I

Input current

SELECT1, SELECT2,
VCOINHIBIT2, VCOINHIBIT1

VI = VDD or GND ±1 µA

Z

i(VCOIN)

Input impedance VCOIN2, VCOIN1 VCOIN = 1/2 V

DD

10 MΩ

I

DD(INH)

VCO supply current (inhibit) (each chip) See Note 4 0.01 1 µA

I

DD(VCO)

VCO supply current (each chip) See Note 5 5 15 mA

NOTES: 4. The current into VCO VDD and LOGIC VDD when VCOINHIBIT = VDD, and the PFD is inhibited.

5. The current into VCO VDD and LOGIC VDD when VCOIN = 1/2 VDD, R

BIAS

= 3.3 kΩ, VCOINHIBIT = GND, and the PFD is inhibited.

PFD1, PFD2 electrical characteristic, V

DD

= 3 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage IOH = –2 mA 2.7 V

V

OL

Low-level output voltage IOL = 2 mA 0.2 V

I

OZ

High-impedance output current

PFD INHIBIT = high,
VO = VDD or GND

±1 µA

V

IH

High-level input voltage

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

2.7 V

V

IL

Low-level input voltage

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

0.5 V

V

IT

Input threshold voltage PFD INHIBIT2, PFD INHIBIT1 0.9 1.5 2.1 V

C

i

Input capacitance

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

5 pF

Z

i

Input impedance

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

10 MΩ

I

DD(Z)

High-impedance state PFD supply current See Note 6 0.1 1 µA

I

DD(PFD)

PFD supply current See Note 7 0.1 1.5 mA

NOTES: 6. The current into LOGIC VDD, when FIN–A and FIN–B = GND, PFD INHIBIT= VDD, no load, and VCO OUT is inhibited.

7. The current into LOGIC VDD when FIN–A and FIN–B = 1 MHz with V

I(PP)

= 3 V rectangular wave, PFD INHIBIT = GND, no load,

and VCO OUT is inhibited.

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VCO1, VCO2 operating characteristics, V

DD

= 3 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

osc

Operating oscillation frequency

R

BIAS1, RBIAS2

= 3.3 kΩ,

VCOIN1, VCOIN2 = 1/2 V

DD

15 19 23 MHz

t

s(fosc)

Time to stable oscillation See Note 8 10 µs

CL = 15 pF, See Figure 3 7 14

trRise time

CL = 50 pF, See Figure 3 14

ns

CL = 15 pF, See Figure 3 6 12

tfFall time

CL = 50 pF, See Figure 3 10

ns

Duty cycle at VCO OUT

R

BIAS1

, R

BIAS2

= 3.3 kΩ,

VCOIN1, VCOIN2 = 1/2 V

DD

45% 50% 55%

α

(fosc)

Temperature coefficient of oscillation frequency

R

BIAS1, RBIAS2

= 3.3 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD,
TA = –20°C to 75°C

0.04 %/°C

k

SVS(fosc)

Supply voltage coefficient of oscillation frequency

R

BIAS1,

R

BIAS2

= 3.3 kΩ,
VCOIN1, VCOIN2 = 1.5 V,
VDD = 2.85 V to 3.15 V

0.02 %/mV

Jitter absolute (see Note 9) R

BIAS1

= 3.3 kΩ 100 ps

NOTES: 8. The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.

9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.

PFD1, PFD2 operating characteristics, V

DD

= 3 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

max

Maximum operating frequency 20 MHz

t

PLZ

PFD output disable time from low level 21 50

t

PHZ

PFD output disable time from high level

23 50

ns

t

PZL

PFD output enable time to low level

See Figures 4 and 5 and Table 4

11 30

t

PZH

PFD output enable time to high level 10 30

ns

t

r

Rise time

p

2.3 10 ns

t

f

Fall time

C

L

= 15 pF,

See Figure 4

2.1 10 ns

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VCO1, VCO2 electrical characteristics, V

DD

= 5 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage IOH = –2 mA 4 V

V

OL

Low-level output voltage IOL = 2 mA 0.5 V

V

IT

Input threshold voltage SELECT1, SELECT2,

VCOINHIBIT1, VCOINHIBIT2

1.5 2.5 3.5 V

I

I

Input current SELECT1, SELECT2,

VCOINHIBIT1, VCOINHIBIT2

VI = VDD or GND ±1 µA

Z

i(VCOIN)

Input impedance VCOIN1, VCOIN2 VCOIN = 1/2 V

DD

10 MΩ

I

DD(INH)

VCO supply current (inhibit) (each chip) See Note 4 0.01 1 µA

I

DD(VCO)

VCO supply current (each chip) See Note 10 15 35 mA

NOTES: 4. The current into VCO VDD and LOGIC VDD when VCOINHIBIT = VDD, and the PFD is inhibited.

10. The current into VCO VDD and LOGIC VDD when VCOIN = 1/2 VDD, R

BIAS

= 2.2 kΩ, VCOINHIBIT = GND, and the PFD is inhibited.

PFD1, PFD2 electrical characteristics, V

DD

= 5 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage IOH = 2 mA 4.5 V

V

OL

Low-level output voltage IOL = 2 mA 0.2 V

I

OZ

High-impedance output current

PFD INHIBIT1, PFD INHIBIT2 = high,
VO = VDD or GND

±1 µA

V

IH

High-level input voltage

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

4.5 V

V

IL

Low-level input voltage

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

1 V

V

IT

Input threshold voltage

PFD INHIBIT2,
PFD INHIBIT1

1.5 2.5 3.5 V

C

i

Input capacitance

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

5 pF

Z

i

Input impedance

FIN–A1, FIN–B1,
FIN–A2, FIN–B2

10 MΩ

I

DD(Z)

High-impedance state PFD supply current See Note 6 0.1 1 µA

I

DD(PFD)

PFD supply current (each chip) See Note 11 0.15 3 mA

NOTES: 6. The current into LOGIC VDD, when FIN–A and FIN–B = GND, PFD INHIBIT= VDD, no load, and VCO OUT is inhibited.

11. The current into LOGIC VDD when FIN–A and FIN–B = 1 MHz with V

I(PP)

= 5-V rectangular wave, PFD INHIBIT = GND, no load,
and
VCO OUT is inhibited.

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VCO1, VCO2 operating characteristics, V

DD

= 5 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

osc

Operating oscillation frequency

R

BIAS1, RBIAS2

= 2.2 kΩ,

VCOIN1, VCOIN2 = 1/2 V

DD

32 41 50 MHz

t

s(fosc)

Time to stable oscillation See Note 8 10 µs

CL = 15 pF, See Figure 3 5.5 10

trRise time

CL = 50 pF, See Figure 3 8

ns

CL = 15 pF, See Figure 3 5 10

tfFall time

CL = 50 pF, See Figure 3 6

ns

Duty cycle at VCO OUT

R

BIAS1, RBIAS2

= 2.2 kΩ,

VCOIN1, VCOIN2 = 1/2 V

DD

45% 50% 55%

α

(fosc)

Temperature coefficient of oscillation frequency

R

BIAS1, RBIAS2

= 2.2 kΩ,
VCOIN1, VCOIN2 = 1/2 VDD,
T

ope

= –20°C to 75°C

0.06 %/°C

k

SVS(fosc)

Supply voltage coefficient of oscillation fre­quency

R

BIAS1, RBIAS2

= 2.2 kΩ,
VCOIN1, VCOIN2 = 2.5 V,
VDD = 4.75 V to 5.25 V

0.006 %/mV

Jitter absolute (see Note 9) R

BIAS1

= 3.3 kΩ 100 ps

NOTES: 8. The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.

9. The LPF circuit is shown in Figure 28 with calculated values listed in T able 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.

PFD1, PFD2 operating characteristics, V

DD

= 5 V, T

A

= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

max

Maximum operating frequency 40 MHz

t

PLZ

PFD output disable time from low level 21 40

t

PHZ

PFD output disable time from high level

20 40

ns

t

PZL

PFD output enable time to low level

See Figures 4 and 5 and Table 4

7.3 20

t

PZH

PFD output enable time to high level 6.5 20

ns

t

r

Rise time

p

2.3 10 ns

t

f

Fall time

C

L

= 15 pF,

See Figure 4

1.7 10 ns

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

r

t

f

90%

10%

90%

10%

VCO OUT1,
VCO OUT2

Figure 3. VCO Output Voltage Waveform

50%

90%

10%

10%

50%

50%

t

PHZ

t

r

t

f

t

PLZ

V

DD

GND
V

DD

GND

V

DD

GND

V

DD

GND
V

DD

GND

V

DD

GND

FIN–A1,

FIN–A2

FIN–B1,

FIN–B2

PFD INHIBIT1,

PFD INHIBIT2

PFD OUT1,

PFD OUT2

(a) OUTPUT PULLDOWN

(see Figure 5 and Table 6)

(b) OUTPUT PULLUP

(see Figure 5 and Table 6)

†

FIN–A and FIN–B are for reference phase only, not for timing.

90%

t

PZL

t

PZH

GND

V

OH

50%

50%

50%

V

DD

V

OL

Figure 4. PFD Output Voltage Waveform

Table 6. PFD1 and PDF2 Output Test Conditions

PARAMETER R

L

C

L

S

1

S

2

t

PZH

t

PHZ

Open Close

t

r

p

t

PZL

1 kΩ

15 pF

t

PLZ

Close Open

t

f

S1

S2

R

L

C

L

Test Point

PFD OUT

DUT

V

DD

Figure 5. PFD1 and PFD2 Output Test Conditions

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

10

0

40

20

01 2 3

30

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

VI

(VCOIN)

– VCO Control Voltage – V

VDD = 3 V
R

BIAS

= 2.2 kΩ

–20°C

25°C

75°C

– VCO Oscillation Frequency – MHz

f

osc

Figure 7

60

40

0123

80

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

100

45

20

VI

(VCOIN)

– VCO Control Voltage – V

–20°C

25°C

75°C

VDD = 5 V
R

BIAS

= 1.5 kΩ

– VCO Oscillation Frequency – MHz

f

osc

Figure 8

10

0

40

20

0123

30

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

VI

(VCOIN)

– VCO Control Voltage – V

VDD = 3 V
R

BIAS

= 3.3 kΩ

25°C

75°C

–20°C

– VCO Oscillation Frequency – MHz

f

osc

Figure 9

40

0

01238045

20

60

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

VDD = 5 V
R

BIAS

= 2.2 kΩ

25°C

75°C

VI

(VCOIN)

– VCO Control Voltage – V

–20°C

– VCO Oscillation Frequency – MHz

f

osc

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

10

0

40

20

0123

30

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

VI

(VCOIN)

– VCO Control Voltage – V

–20°C

25°C

75°C

VDD = 3 V
R

BIAS

= 4.3 kΩ

– VCO Oscillation Frequency – MHz

f

osc

Figure 11

40

0

01238045

20

60

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

VI

(VCOIN)

– VCO Control Voltage – V

–20°C

25°C

75°C

VDD = 5 V
R

BIAS

= 3.3 kΩ

– VCO Oscillation Frequency – MHz

f

osc

Figure 12

20

15

10

30

25

2 2.5 3.5 4 4.5

– VCO Oscillation Frequency – MHz

VCO OSCILLATION FREQUENCY

vs

BIAS RESISTOR

VDD = 3 V
VCOIN = 1/2 V

DD

TA = 25°C

f

osc

R

BIAS

– Bias Resistor – kΩ

3

Figure 13

40

30

20

60

50

1.5 2 2.5 3.5

– VCO Oscillation Frequency – MHz

VCO OSCILLATION FREQUENCY

vs

BIAS RESISTOR

VDD = 5 V
VCOIN = 1/2 V

DD

TA = 25°C

f

osc

R

BIAS

– Bias Resistor – kΩ

3

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 14

0.2

0.1

2 2.5

3.3

0.3

TEMPERATURE COEFFICIENT OF

OSCILLATION FREQUENCY

vs

BIAS RESISTOR

0.4

4 4.5

C

°

– Temperature Coefficient of Oscillation

R

BIAS

– Bias Resistor – kΩ

Frequency – % /

VDD = 3 V
VCOIN = 1/2 V

DD

TA = –20°C to 75°C

3 3.5

(f

osc)

α

0

Figure 15

0.2

0.1

1.5

2.2

0.3

TEMPERATURE COEFFICIENT OF

OSCILLATION FREQUENCY

vs

BIAS RESISTOR

0.4

3.5

R

BIAS

– Bias Resistor – kΩ

VDD = 5 V
VCOIN = 1/2 V

DD

TA = –20°C to 75°C

2 2.5 3

C

°

– Temperature Coefficient of Oscillation

Frequency – % /

(f

osc)

α

0

Figure 16

20

18

16

2.85 3

22

VCO OSCILLATION FREQUENCY

vs

VCO SUPPLY VOLTAGE

24

3.15

VDD – VCO Supply Voltage – V

R

BIAS

= 3.3 kΩ

VCOIN = 1.5 V
TA = 25°C

– VCO Oscillation Frequency – MHz

f

osc

Figure 17

40

36

32

4.75 5

44

VCO OSCILLATION FREQUENCY

vs

VCO SUPPLY VOLTAGE

48

5.25

VDD – VCO Supply Voltage – V

R

BIAS

= 2.2 kΩ

VCOIN = 1/2 V

DD

TA = 25°C

– VCO Oscillation Frequency – MHz
f

osc

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 18

0.03

0.02

0.01

2 2.5 3.5 4

0.04

SUPPLY VOLTAGE COEFFICIENT OF VCO

OSCILLATION FREQUENCY

vs

BIAS RESISTOR

0.05

4.5

R

BIAS

– Bias Resistor – kΩ

VDD = 2.85 V to 3.15 V
VCOIN = 1/2 V

DD

TA = 25°C

3

– Supply Voltage Coefficient of

Oscillation Frequency – %/V

k

SVS(fosc)

0

Figure 19

0.005

1.5 2.5 3

0.01

3.5

R

BIAS

– Bias Resistor – kΩ

SUPPLY VOLTAGE COEFFICIENT OF VCO

OSCILLATION FREQUENCY

vs

BIAS RESISTOR

VDD = 4.75 V to 5.25 V
VCOIN = 1/2 V

DD

TA = 25°C

2

0

– Supply Voltage Coefficient of

Oscillation Frequency – %/V

k

SVS(fosc)

Figure 20

20

15

10

30

25

2 2.5 3.5 4 4.5

Recommended Lock Frequency – MHz

RECOMMENDED LOCK FREQUENCY

(×1 OUTPUT)

vs

BIAS RESISTOR

R

BIAS

– Bias Resistor – kΩ

VDD = 2.85 V to 3.15 V
TA = –20°C to 75°C

3

Figure 21

40

30

20

10

1.5 2 2.5

50

60

3.5

R

BIAS

– Bias Resistor – kΩ

Recommended Lock Frequency – MHz

RECOMMENDED LOCK FREQUENCY

(×1 OUTPUT)

vs

BIAS RESISTOR

VDD = 4.75 V to 5.25 V
TA = –20°C to 75°C

3

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 22

Recommended Lock Frequency – MHz

RECOMMENDED LOCK FREQUENCY

(×1/2 OUTPUT)

vs

BIAS RESISTOR

R

BIAS

– Bias Resistor – kΩ

10

7.5

5

15

12.5

2 2.5 3.5 4 4.5

3

VDD = 2.85 V to 3.15 V
TA = –20°C to 75°C
SELECT = V

DD

Figure 23

R

BIAS

– Bias Resistor – kΩ

Recommended Lock Frequency – MHz

RECOMMENDED LOCK FREQUENCY

(×1/2 OUTPUT)

vs

BIAS RESISTOR

20

15

10

5

1.5 2 2.5

25

30

3.5

3

VDD = 4.75 V to 5.25 V
TA = –20°C to 75°C
SELECT = V

DD

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

gain of VCO and PFD

Figure 24 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The K

p

and KV values are obtained from the operating
characteristics of the device as shown in Figure

24. K

p

is defined from the phase detector VOL and

V

OH

specifications and the equation shown in

Figure 24(b). K

V

is defined from Figures 8, 9, 10,

and 11 as shown in Figure 24(c).
The parameters for the block diagram with the

units are as follows:

K

V

: VCO gain (rad/s/V)

K

p

: PFD gain (V/rad)

K

f

: LPF gain (V/V)

K

N

: countdown divider gain (1/N)

external counter

When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.

R

BIAS

The external bias resistor sets the VCO center frequency with 1/2 V

DD

applied to the VCOIN terminal. However,

for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply, or a resistor value of

2.5 kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice,
but a carbon-compositiion resistor can be used with excellent results also. A 0.22-µF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.

hold-in range

From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:

DwH]

0.8

ǒ

K

p

Ǔǒ

K

V

Ǔǒ

Kf(R)

Ǔ

Where

K

f

(∞) = the filter transfer function value at ω = ∞

(1)

Divider

(KN = 1/N)

PFD
(Kp)

VCO
(KV)

LPF
(Kf)

TLC2942

f

REF

V

OH

f

MAX

f

MIN

VIN

MIN

VIN

MAX

–2π 2π–π 0 π

Range of

Comparison

V

OH

V

OL

Kp =

VOH – V

OL

4π

KV =

2π(f

MAX

– f

MIN

)

VIN

MAX

– VIN

MIN

Figure 24. Example of a PLL Block Diagram

(a)

(c)(b)

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

low-pass-filter (LPF) configurations

Many excellent references are available that include detailed design information about LPFs and they should
be consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are
shown in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to F

IN

-B
because of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at
the VCO input. The value of C2 should be equal to or less than one-tenth the value of C1.

R1

C1

T1 = C1R1

(a) LAG FILTER

R1

C1

T1 = C1R1
T2 = C1R2

R2

(b) LAG-LEAD FILTER

R2

C1

R1

T1 = C1R1
T2 = C1R2

(c) ACTIVE FILTER

A

–

V

I

V

O

V

I

V

O

V

I

C2

V

O

C2

Figure 25. LPF Examples for PLL

the passive filter

The transfer function for the low-pass filter shown in Figure 25(b) is:

V

O

V

IN

+

1)s

@

T2

1)s

@

(

T1)T2

)

Where

T1+R1

@

C1 and T2+R2@C1

(2)

Using this filter makes the closed loop PLL system a type 1 second-order system. The response curves of this
system to a unit step are shown in Figure 26.

the active filter

When using the active filter shown in Figure 25(c), the phase detector inputs must be reversed since the filter
adds an additional inversion. Therefore, the input reference frequency should be applied to the F

IN

-B terminal

and the output of the VCO divider should be applied to the input reference terminal, F

IN

-A.

The transfer function for the active filter shown in Figure 25(c) is:

F(s)

+

1)s

@R2@

C1

s

@R1@

C1

(3)

Using this filter makes the closed loop PLL system a type 2 second-order system. The response curves of this
system to a unit step are shown in Figure 27.

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

012345678910111213

ω

nt

(t), Normalized Responseφ

2

= 0.1

z

= 0.2

z

= 0.3

z

= 0.4

z

= 0.5

z

= 0.6

z

= 0.7

z

= 0.8

z

= 1.0

z

= 1.5

z

= 2.0

z

ωnts = 4.5

Figure 26. Type 1 Second-Order Step Response

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

012345678910111213

ω

nt

(t), Normalized Output Frequencyφ

0

ζ = 0.8

ζ = 0.1

ζ = 0.2

ζ = 0.3

ζ = 0.4

ζ = 0.5
ζ = 0.6

ζ = 0.7

ζ = 1.0

ζ = 2.0

Figure 27. Type 2 Second-Order Step Response

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

basic design example

The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.

Assume the loop has to have a 100-µs settling time (t

s

) with a countdown divider N value = 8. Using the Type

1, second-order response curves of Figure 26, a value of 4.5 radians is selected for ω

nts

with a damping factor
of 0.7. This selection gives a good combination for settling time, accuracy, and loop gain margin. The initial
parameters are summarized in Table 7. The loop constants, K

V

and Kp, are calculated from the data sheet

specifications and Table 8 shows these values.
The natural loop frequency is calculated as follows:

wnts+

4.5

Then

wn+

4.5

100ms

+

45 k-radiansńsec

Since

(4)

T able 7. Design Parameters

PARAMETER SYMBOL VALUE UNITS

Divider value N 8
Lockup time t 100 µs
Radian value to selected lockup time ωnt 4.5 rad
Damping factor ζ 0.7

Table 8. Device Specifications

PARAMETER SYMBOL VALUE UNITS

VCO gain 76.6 Mrad/V/s

f

MAX

70 MHz

f

MIN

K

V

20 MHz

VIN

MAX

5 V

VIN

MIN

0.9 V

PFD gain K

p

0.342357 V/rad

Using the low-pass filter in Figure 25(b) and divider N value, the transfer function for phase and frequency are
shown in equations 5 and 6. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.

Hence, transfer function of Figure 24 (a) for phase is:

F

2(s)

F

1(s)

+

K

p

@

K

V

N

@

(

T1)T2

)

ȧ

ȧ
ȧ
ȧ

ȱ

Ȳ

1)s@T2

s2)

s

ƪ

1

)

K

p

@

K

V

@

T2

N@(T1)T2)

ƫ

)

K

p

@

K

V

N@(T1)T2)

ȧ

ȧ
ȧ
ȧ

ȳ

ȴ

(5)

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

23

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

and the transfer function for frequency is:

F

OUT(s)

F

REF(s)

+

K

p

@

K

V

(

T1)T2

)

ȧ

ȧ
ȧ
ȧ

ȱ

Ȳ

1)s@T2

s2)

s

@

ƪ

1

)

K

p

@

K

V

@

T2

N

@

(T1)T2)

ƫ

)

K

p

@

K

V

N

@

(T1)T2)

ȧ

ȧ
ȧ
ȧ

ȳ

ȴ

(6)

The standard two-pole denominator is D = s

2

+ 2 ζ ωn s + ω

n

2

and comparing the coefficients of the denominator

of equation 5 and 6 with the standard two-pole denominator gives the following results:

wn+

K

p

@

K

V

N

@

(T1)T2)

Ǹ

Solving for T1 + T2

T1)T2

+

K

p

@

K

V

N

@

w

2

n

(7)

and by using this value for T1 + T2 in equation 7 the damping factor is:

z

+

w

n

2

@

ǒ

T2

)

N

K

p

@

K

V

Ǔ

solving for T2:

T2

+

2

z

w

–

N

K

p

@

K

V

then by substituting for T2 in equation 7 and solving for T1 as given in equation 10:

T1

+

K

V

@

K

p

N

@

w

2

n

–

2

z

w

n

)

N

K

p

@

K

V

(8)

(9)

(10)

From the circuit constants and the initial design parameters then:

R2

+

ƪ

2

z

w

n

*

N

K

p

@

K

V

ƫ

1

C1

R1

+

ȧ

ȱ
Ȳ

K

p

@

K

v

w

2

n

@

N

*

2

z

w

n

)

N

K

p

@

K

V

ȧ

ȳ
ȴ

1

C1

(11)

(12)

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculated
values are listed in Table 9.

Table 9. Calculated Values

PARAMETER SYMBOL VALUE UNITS

Natural angular frequency ω

n

45000 rad/sec

K = (KV • Kp)/N 3.277 Mrad/sec
Lag-lead filter

Calculated value
Nearest standard value

R1

15870
16000

Ω

Calculated value
Nearest standard value

R2

308
300

Ω

Selected value C1 0.1 µF

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The evaluation and operation schematic for the TLC2942I is shown in Figure 28.

1/2 f

osc

Phase

Comparator

AGND

DGND

DGND

DGND

REF IN

DV

DD

AV

DD

V

DD

LOGIC VDD (digital)

LOGIC GND (Digital)

SELECT

FIN–A

VCOINHIBIT

PFD INHIBIT

GND

VCO GND

VCOIN

BIAS

VCO V

DD

VCO

R1

†

R3

C1

R2C2

R4 R5 R6

S1
S2
S3

Divide

By

N

0.22 µF

1

2

3

4

5

6

7

38

37

36

35

34

33

8

FIN–B

†

R

BIAS

resistor

VCO OUT

PFD OUT

PLL2

PLL1

Figure 28. Evaluation and Operation Schematic

TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

PCB layout considerations

The TLC2942I contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.

The following design recommendations benefit the TLC2942I user:

D

External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.

D

RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.

D

Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.

D

LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.

D

VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.

D

The no-connection (NC) terminal on the package should be connected to GND.

TLC2942

HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK

SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040065 /C 10/95

28 PIN SHOWN

Gage Plane

8,20
7,40

0,15 NOM

0,63

1,03

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,60
5,00

15

0,22

14

A

28

1

2016

6,50

6,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65

M

0,15

0°–8°

0,10

3,30

8

2,70

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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