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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Voltage-Controlled Oscillator (VCO)
Section:
– Ring Oscillator Using Only One
External Bias Resistor (R
BIAS
)
– Lock Frequency:
43 MHz to 100 MHz (V
DD
= 5 V ±5%,
T
A
= –20°C to 75°C, ×1 Output)
37 MHz to 55 MHz (V
DD
= 3 V ±5%,
T
A
= –20°C to 75°C)
D
Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump
D
Independent VCO, PFD Power-Down Mode
D
Thin Small-Outline Package (14 terminal)
D
CMOS Technology
D
Typical Applications:
– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division
D
CMOS Input Logic Level
description
The TLC2933 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (R
BIAS
). The high-speed PFD with internal charge pump detects
the phase difference between the reference frequency input and signal frequency input from the external
counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. With the
high-speed and stable VCO characteristics, the TLC2933 is well suited for use in high-performance PLL
systems.
functional block diagram
Phase
Frequency
Detector
4
5
9
6
FIN–A
FIN–B
PFD INHIBIT
PFD OUT
Voltage-
Controlled
Oscillator
12
13
10
3
VCO IN
BIAS
VCO INHIBIT
VCO OUT
2
TEST
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(PW)
–20°C to 75°C TLC2933PWLE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
LOGIC V
DD
TEST
VCO OUT
FIN–A
FIN–B
PFD OUT
LOGIC GND
VCO V
DD
BIAS
VCO
IN
VCO GND
VCO INHIBIT
PFD INHIBIT
NC
PW PACKAGE
†
(TOP VIEW)
NC – No internal connection
†
Available in tape and reel only and ordered as the
TLC2933PWLE.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
BIAS 13 I Bias supply. An external resistor (R
BIAS
) between VCO VDD and BIAS supplies bias for adjusting the
oscillation frequency range.
FIN–A 4 I Input reference frequency f
(REF IN)
is applied to FIN–A.
FIN–B 5 I Input for VCO external counter output frequency f
(FIN–B)
. FIN–B is nominally provided from the external
counter.
LOGIC GND 7 Ground for the internal logic.
LOGIC V
DD
1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce
cross-coupling between supplies.
NC 8 No internal connection.
PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD OUT is in the high-impedance state, see Table 2.
PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD OUT is in the high-impedance state.
TEST 2 I Test terminal. TEST connects to ground for normal operation.
VCO GND 11 Ground for VCO.
VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency .
VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 1).
VCO OUT 3 O VCO output. When VCO INHIBIT is high, VCO OUT is low.
VCO V
DD
14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling
between supplies.
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external resistor (R
BIAS
) connected between the VCO V
DD
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. While all resistor
values within the specified range result in excellent low temperature coefficients, the bias resistor value for the
minimum temperature coefficient is nominally 2.2 kΩ with 3-V V
DD
and nominally 2.4 kΩ with 5-V VDD. For the
lock frequency range refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and VCO control voltage.
VCO Oscillation Frequency Range
Bias Resistor (R
BIAS
)
1/2 V
DD
VCO Control Voltage (VCO IN)
VCO Oscillation Frequency
(f )
osc
Figure 1. VCO Oscillation Frequency
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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode as shown in Table 1.
Table 1. VCO Inhibit Function
VCO INHIBIT VCO OSCILLATOR VCO OUT I
DD(VCO)
Low Active Active Normal
High Stopped Low level Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B. For clock
recovery PLL systems, other types of phase detectors should be used.
FIN–A
FIN–B
PFD OUT
V
OH
Hi-Z
V
OL
Figure 2. PFD Function Timing Chart
PFD inhibit control
A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops
phase detection as shown in Table 2. A high level on the PFD INHIBIT terminal can also be used as the
power-down mode for the PFD.
Table 2. VCO Output Control Function
PFD INHIBIT DETECTION PFD OUT I
DD(PFD)
Low Active Active Normal
High Stopped Hi-Z Power Down
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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics
VCO block schematic
Bias
Control
VCO
Output
Buffer
R
BIAS
VCO IN
VCO INHIBIT
VCO OUT
BIAS
PFD block schematic
Detector
Charge Pump
PFD OUT
FIN–A
FIN–B
PFD INHIBIT
V
DD
absolute maximum ratings
†
Supply voltage (each supply), V
DD
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (each input), V
I
(see Note 1) –0.3 V to V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (each input), I
I
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current (each output), I
O
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation at (or below) T
A
= 25°C (see Note 2) 700 mW. . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
pp
pp
VDD = 3 V 2.85 3 3.15
Suppl
y v
oltage, V
DD
(each suppl
y,
see Note 3)
VDD = 5 V 4.75 5 5.25
V
Input voltage, VI (inputs except VCO IN) 0 V
DD
V
Output current, IO (each output) 0 ±2 mA
VCO control voltage at VCO IN 1 V
DD
V
VDD = 3 V 37 55
Lock frequenc
y
VDD = 5 V 43 100
MH
z
VDD = 3 V 1.8 2.7
Bias resistor, R
BIAS
VDD = 5 V 2.2 3
kΩ
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and
separated from each other.
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage IOH = –2 mA 2.4 V
V
OL
Low-level output voltage IOL = 2 mA 0.3 V
V
IT+
Positive input threshold voltage at TEST, VCO INHIBIT 0.9 1.5 2.1 V
I
I
Input current at TEST, VCO INHIBIT VI = VDD or ground ±1 µA
Z
i(VCO IN)
Input impedance at VCO IN VCO IN = 1/2 V
DD
10 MΩ
I
DD(INH)
VCO supply current (inhibit) See Note 4 0.01 1 µA
I
DD(VCO)
VCO supply current See Note 5 5.1 15 mA
NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, R
BIAS
= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage IOH = –2 mA 2.7 V
V
OL
Low-level output voltage IOL = 2 mA 0.2 V
I
OZ
High-impedance-state output current
PFD INHIBIT = high,
VI = VDD or ground
±1 µA
V
IH
High-level input voltage at FIN–A, FIN–B 2.1 V
V
IL
Low-level input voltage at FIN–A, FIN–B 0.9 V
V
IT+
Positive input threshold voltage at PFD INHIBIT 0.9 1.5 2.1 V
C
i
Input capacitance at FIN–A, FIN–B 5 pF
Z
i
Input impedance at FIN–A, FIN–B 10 MΩ
I
DD(Z)
High-impedance-state PFD supply current See Note 6 0.01 1 µA
I
DD(PFD)
PFD supply current See Note 7 0.7 4 mA
NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V
I(PP)
= 3 V , rectangular wave), PFD INHIBIT = GND, PFD OUT
open, and VCO OUT is inhibited.
Page 6
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
osc
Operating oscillation frequency R
BIAS
= 2.4 kΩ, VCO IN = 1/2 V
DD
38 48 55 MHz
t
s(fosc)
Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs
t
r
Rise time, VCO OUT↑ CL = 15 pF, See Figure 3 3.3 10 ns
t
f
Fall time, VCO OUT↓ CL = 15 pF, See Figure 3 2 8 ns
Duty cycle at VCO OUT R
BIAS
= 2.4 kΩ, VCO IN = 1/2 V
DD
45% 50% 55%
α
(fosc)
Temperature coefficient of oscillation frequency
R
BIAS
= 2.4 kΩ, VCO IN = 1/2 VDD,
TA = –20°C to 75°C
0.03 %/°C
k
SVS(fosc)
Supply voltage coefficient of oscillation frequency
R
BIAS
= 2.4 kΩ, VCO IN = 1.5 V,
VDD = 2.85 V to 3.15 V
0.04 %/mV
Jitter absolute (see Note 9) R
BIAS
= 2.4 kΩ 100 ps
NOTES: 8. The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully designed printed circuit board (PCB) with no device socket.
PFD section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
max
Maximum operating frequency 30 MHz
t
PLZ
Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z 20 40
t
PHZ
Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z
18 40
ns
t
PZL
Enable time, PFD INHIBIT↓ to PFD OUT low
See Figures 4 and 5 and Table 3
4.1 18
t
PZH
Enable time, PFD INHIBIT↓ to PFD OUT high 4.8 18
ns
t
r
Rise time, PFD OUT↑
p
3.1 9 ns
t
f
Fall time, PFD OUT↓
C
L
=
15 pF
,
See Figure 4
1.5 9 ns
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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage IOH = –2 mA 4.5 V
V
OL
Low-level output voltage IOL = 2 mA 0.5 V
V
IT+
Positive input threshold voltage at TEST, VCO INHIBIT 1.5 2.5 3.5 V
I
I
Input current at TEST, VCO INHIBIT VI = VDD or ground ±1 µA
Z
i(VCO IN)
Input impedance at VCO IN VCO IN = 1/2 V
DD
10 MΩ
I
DD(INH)
VCO supply current (inhibit) See Note 4 0.01 1 µA
I
DD(VCO)
VCO supply current See Note 5 14 35 mA
NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD, and PFD INHIBIT high.
5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, R
BIAS
= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
high.
PFD section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
High-level output voltage IOH = 2 mA 4.5 V
V
OL
Low-level output voltage IOL = 2 mA 0.2 V
I
OZ
High-impedance-state output current
PFD INHIBIT = high,
VI = VDD or ground
±1 µA
V
IH
High-level input voltage at FIN–A, FIN–B 3.5 V
V
IL
Low-level input voltage at FIN–A, FIN–B 1.5 V
V
IT+
Positive input threshold voltage at PFD INHIBIT 1.5 2.5 3.5 V
C
i
Input capacitance at FIN–A, FIN–B 7 pF
Z
i
Input impedance at FIN–A, FIN–B 10 MΩ
I
DD(Z)
High-impedance-state PFD supply current See Note 6 0.01 1 µA
I
DD(PFD)
PFD supply current See Note 10 2.6 8 mA
NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
10. The current into LOGIC VDD when FIN–A and FIN–B = 50 MHz (V
I(PP)
= 3 V , rectangular wave), PFD INHIBIT = ground, PFD OUT
open, and VCO OUT is inhibited.
Page 8
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
osc
Operating oscillation frequency R
BIAS
= 2.4 kΩ,, VCO IN = 1/2 V
DD
64 80 96 MHz
t
s(fosc)
Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs
t
r
Rise time, VCO OUT↑ CL = 15 pF, See Figure 3 2.1 5 ns
t
f
Fall time, VCO OUT↓ CL = 15 pF, See Figure 3 1.5 4 ns
Duty cycle at VCO OUT R
BIAS
= 2.4 kΩ, VCO IN = 1/2 V
DD
45% 50% 55%
α
(fosc)
Temperature coefficient of oscillation frequency
R
BIAS
= 2.4 kΩ, VCO IN = 1/2 VDD,
TA = –20°C to 75°C
0.03 %/°C
k
SVS(fosc)
Supply voltage coefficient of oscillation frequency
R
BIAS
= 2.4 kΩ, VCO IN = 2.5 V,
VDD = 4.75 V to 5.25 V
0.02 %/mV
Jitter absolute (see Note 9) R
BIAS
= 2.4 kΩ 100 ps
NOTES: 8: The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully designed printed circuit board (PCB) with no device socket.
PFD section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
max
Maximum operating frequency 50 MHz
t
PLZ
Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z 20 40
t
PHZ
Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z
17 40
ns
t
PZL
Enable time, PFD INHIBIT↓ to PFD OUT low
See Figures 4 and 5 and Table 3
3.7 10
t
PZH
Enable time, PFD INHIBIT↓ to PFD OUT high 3.4 10
ns
t
r
Rise time, PFD OUT↑
p
1.7 5 ns
t
f
Fall time, PFD OUT↓
C
L
=
15 pF, See Figure 4
1.3 5 ns
Page 9
TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS136A – APRIL 1996 – REVISED JUNE 1997
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
r
t
f
90%
10%
90%
10%
VCO OUT
Figure 3. VCO Output Voltage Waveform
50%
90%
10%
10%
50%
50%
t
PHZ
t
r
t
f
t
PLZ
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
GND
FIN–A
†
FIN–B
†
PFD INHIBIT
PFD OUT
(a) PFD OUT Hi-Z Timing To and From a High Level
(see Figure 5 and Table 3)
(b) PFD OUT Hi-Z Timing To and From a Low Level
(see Figure 5 and Table 3)
†
FIN–A and FIN–B are for reference phase only, not for timing.
90%
t
PZL
t
PZH
Hi-Z
V
OH
50%
50%
50%
V
OL
50% 50%
Hi-Z
Figure 4. PFD Output Voltage Waveform
Table 3. PFD Output Test Conditions
PARAMETER R
L
C
L
S
1
S
2
t
PZH
t
PHZ
Open Closed
t
r
p
t
PZL
1 kΩ
15 pF
t
PLZ
Closed Open
t
f
S1
S2
R
L
C
L
Test Point
PFD OUT
DUT
V
DD
Figure 5. PFD Output Test Conditions
Page 10
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
40
30
10
0
0 0.3 0.6 0.9 1.2 1.5 1.8
60
70
90
2.1 2.4 2.7 3
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
80
50
20
VDD = 3 V
R
BIAS
= 1.8 kΩ
–20°C
25°C
75°C
Figure 7
40
30
10
0
0 0.3 0.6 0.9 1.2 1.5 1.8
60
70
90
2.1 2.4 2.7 3
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
80
50
20
VDD = 3 V
R
BIAS
= 2.2 kΩ
–20°C
25°C
75°C
–20°C
Figure 8
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
40
30
10
0
0 0.8 0.6 0.9 1.2 1.5
50
70
80
1.8 2.1 2.4 2.7
20
60
VDD = 3 V
R
BIAS
= 2.4 kΩ
–20°C
25°C
3
–20°C
75°C
Figure 9
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
40
30
10
0
0 0.3 0.6 0.9 1.2 1.5
50
70
80
1.8 2.1 2.4 2.7
20
60
VDD = 3 V
R
BIAS
= 2.7 kΩ
–20°C
25°C
75°C
3
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 10
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
80
60
20
0
0 0.5 1 1.5 2 2.5 3
100
140
160
3.5 4 4.5 5
40
120
VDD = 5 V
R
BIAS
= 2.2 kΩ
75°C
25°C
–20°C
75°C
–20°C
Figure 11
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
80
60
20
0
0 0.5 1 1.5 2 2.5
100
140
160
3 3.5 4 4.5
40
120
VDD = 5 V
R
BIAS
= 2.4 kΩ
75°C
–20°C
25°C
5
75°C
–20°C
Figure 12
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
40
20
120
0
0 0.5 1 1.5 2 2.5 3
80
60
100
140
3.5 4 4.5
75°C
–20°C
25°C
VDD = 5 V
R
BIAS
= 2.7 kΩ
–20°C
75°C
5
Figure 13
– VCO Oscillation Frequency – MHz
f
osc
VCO IN – VCO Control Voltage – V
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
40
20
120
0
0 0.5 1 1.5 2 2.5 3
80
60
100
140
3.5 4 4.5
75°C
–20°C
25°C
VDD = 5 V
R
BIAS
= 3 kΩ
5
–20°C
75°C
Page 12
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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TYPICAL CHARACTERISTICS
Figure 14
45
40
35
30
1.8 2.2
Recommended Lock Frequency – MHz
50
55
RECOMMENDED LOCK FREQUENCY
vs
BIAS RESISTOR
60
2.4 2.7
VDD = 3 V ± 5%
TA = –20°C to 75°C
R
BIAS
– Bias Resistor – kΩ
MAX
MIN
Figure 15
70
50
40
30
2.2 2.4
Recommended Lock Frequency – MHz
80
100
RECOMMENDED LOCK FREQUENCY
vs
BIAS RESISTOR
110
2.7 3
VDD = 5 V ± 5%
TA = –20°C to 75°C
R
BIAS
– Bias Resistor – kΩ
MAX
MIN
90
60
Page 13
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
gain of VCO and PFD
Figure 16 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The K
p
and KV values are obtained from the operating
characteristics of the device as shown in
Figure 16. K
p
is defined from the phase detector
V
OL
and VOH specifications and the equation
shown in Figure 16(b). K
V
is defined from
Figures 8, 9, 10, and 1 1 as shown in Figure 16(c).
The parameters for the block diagram with the
units are as follows:
K
V
: VCO gain (rad/s/V)
K
p
: PFD gain (V/rad)
K
f
: LPF gain (V/V)
K
N
: countdown divider gain (1/N)
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V
DD
applied to the VCO IN terminal. For the
most accurate results, a metal-film resistor is the better choice but a carbon-composition resistor can also be
used with excellent results. A 0.22 µF capacitor should be connected from the BIAS terminal to ground as close
to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 17 is as follows:
DwH]
0.8
ǒ
K
p
Ǔǒ
K
V
Ǔǒ
Kf(R)
Ǔ
Where
K
f
(∞) = the filter transfer function value at ω = ∞
(1)
Divider
(KN = 1/N)
PFD
(Kp)
VCO
(KV)
LPF
(Kf)
TLC2933
f REF
V
OH
f
MAX
f
MIN
VIN
MIN
VIN
MAX
–2π 2π–π 0 π
Range of
Comparison
V
OH
V
OL
Kp =
VOH – V
OL
4π
KV =
2π(f
MAX
– f
MIN
)
VIN
MAX
– VIN
MIN
Figure 16. Example of a PLL Block Diagram
(a)
(c)(b)
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown
in Figure 17. When the active filter of Figure 17(c) is used, the reference should be applied to FIN-B because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. The value of C2 should be equal to or less than one tenth the value of C1.
R1
C1
T1 = C1R1
(a) LAG FILTER
R1
C1
T1 = C1R1
T2 = C1R2
R2
(b) LAG-LEAD FILTER
R2
C1
R1
T1 = C1R1
T2 = C1R2
(c) ACTIVE FILTER
A
–
V
I
V
O
V
I
V
O
V
I
C2
V
O
C2
Figure 17. LPF Examples for PLL
the passive filter
The transfer function for the low-pass filter shown in Figure 17(b) is;
V
O
V
IN
+
1)s
@
T2
1)s
@
(
T1)T2
)
where
T1+R1
@
C1 and T2+R2@C1
(2)
Using this filter makes the closed-loop PLL system a type 1 second-order system. The response curves of this
system to a unit step are shown in Figure 18.
the active filter
When using the active filter shown in Figure 17(c), the phase detector inputs must be reversed since the filter
adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B terminal
and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 17(c) is:
F(s)
+
1)s
@
R2@C1
s
@R1@
C1
(3)
Using this filter makes the closed-loop PLL system a type 2 second-order system. The response curves of this
system to a unit step are shown in Figure 19.
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
Using the lag-lead filter in Figure 17(b) and divider N value, the transfer function for phase and frequency are
shown in equations 4 and 5. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, the transfer function of Figure 17(a) for phase is
F
2(s)
F
1(s)
+
K
p
@
K
V
N
@
(
T1)T2
)
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1)s@T2
s2)
s
ƪ
1
)
K
p
@
K
V
@
T2
N
@
(T1)T2)
ƫ
)
K
p
@
K
V
N
@
(T1)T2)
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
(4)
and the transfer function for frequency is
F
OUT(s)
F
REF(s)
+
K
p
@
K
V
(
T1)T2
)
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1)s@T2
s2)
s
@
ƪ
1
)
K
p
@
K
V
@
T2
N@(T1)T2)
ƫ
)
K
p
@
K
V
N@(T1)T2)
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
(5)
The standard 2-pole denominator is D = s
2
+ 2 ζ ωn s + ω
n
2
and comparing the coefficients of the denominator
of equation (4) and (5) with the standard 2-pole denominator gives the following results.
wn+
K
p
@
K
V
N
@
(T1)T2)
Ǹ
Solving for T1 + T2
T1)T2
+
K
p
@
K
V
N
@
w
2
n
(6)
and by using this value for T1 + T2 in equation (6) the damping factor is
z
+
w
n
2
@
ǒ
T2
)
N
K
p
@
K
V
Ǔ
solving for T2
T2
+
2
z
w
–
N
K
p
@
K
V
then by substituting for T2 in equation (6)
T1
+
K
V
@
K
p
N
@
w
2
n
–
2
z
w
n
)
N
K
p
@
K
V
(7)
(8)
(9)
Page 16
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
R2
+
ƪ
2
z
w
n
*
N
K
p
@
K
V
ƫ
1
C1
R1
+
ȧ
ȱ
Ȳ
K
p
@
K
v
w
2
n
@
N
*
2
z
w
n
)
N
K
p
@
K
V
ȧ
ȳ
ȴ
1
C1
(10)
(11)
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size.
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
012345678910111213
ω
nt
Normalized Gain Response
= 0.1
z
= 0.2
z
= 0.3
z
= 0.4
z
= 0.5
z
= 0.6
z
= 0.7
z
= 0.8
z
= 1.0
z
= 1.5
z
= 2.0
z
ωnts = 4.5
Figure 18. Type 1 Second-Order Step Response
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TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
012345678910111213
ω
nt
Normalized Gain Response
ζ = 0.8
ζ = 0.1
ζ = 0.2
ζ = 0.3
ζ = 0.4
ζ = 0.5
ζ = 0.6
ζ = 0.7
ζ = 1.0
ζ = 2.0
Figure 19. Type 2 Second-Order Step Response
Page 19
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Phase
Comparator
AGND
DGND
DGND
DGND
REF IN
DV
DD
AV
DD
V
DD
LOGIC VDD (Digital)
LOGIC GND (Digital)
TEST
FIN–A
VCO INHIBIT
PFD INHIBIT
NC
VCO GND
VCO IN
BIAS
VCO V
DD
VCO
R1
†
R3
C1
R2C2
R5 R6
S1
S2
Divide
By
N
0.22 µF
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FIN–B
†
R
BIAS
resistor
VCO OUT
PFD OUT
Figure 20. Evaluation and Operation Schematic
PCB layout considerations
The TLC2933 contains a high frequency oscillator; therefore, very careful breadboarding and PCB layout is
required for evaluation.
The following design recommendations benefit the TLC2933 user:
D
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
D
Radio frequency (RF) breadboarding or RF PCB techniques should be used throughout the evaluation and
production process.
D
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
D
LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
D
VCO VDD to ground and LOGIC VDD to ground should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
D
The no-connection (NC) terminal on the package should be connected to ground to prevent stray pickup.
Page 20
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HIGH-PERFORMANCE PHASE-LOCKED LOOP
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Page 21
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