Datasheet TLC2933 Datasheet (TEXAS INSTRUMENTS)

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TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

D

Voltage-Controlled Oscillator (VCO) Section:

PW PACKAGE

(TOP VIEW)

†

– Ring Oscillator Using Only One

External Bias Resistor (R

BIAS

)

– Lock Frequency:

43 MHz to 100 MHz (V T

= –20°C to 75°C, ×1 Output)

A

37 MHz to 55 MHz (V T

= –20°C to 75°C)

A

D

Phase-Frequency Detector (PFD) Section

= 5 V ±5%,

DD

= 3 V ±5%,

DD

Includes a High-Speed Edge-Triggered Detector With Internal Charge Pump

D

Independent VCO, PFD Power-Down Mode

D

Thin Small-Outline Package (14 terminal)

D

CMOS Technology

D

Typical Applications:

LOGIC V

LOGIC GND

†

Available in tape and reel only and ordered as the TLC2933PWLE.

NC – No internal connection

DD

TEST

VCO OUT

FIN–A FIN–B

PFD OUT

1 2 3 4 5 6 7

14 13 12 11 10

9 8

– Frequency Synthesis – Modulation/Demodulation – Fractional Frequency Division

D

CMOS Input Logic Level

description

The TLC2933 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range of the VCO is set by an external bias resistor (R the phase difference between the reference frequency input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. With the high-speed and stable VCO characteristics, the TLC2933 is well suited for use in high-performance PLL systems.

). The high-speed PFD with internal charge pump detects

BIAS

VCO V

DD

BIAS

IN

VCO VCO GND VCO INHIBIT PFD INHIBIT NC

functional block diagram

4

FIN–A FIN–B

PFD INHIBIT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

5

Frequency

Detector

9

Phase

VCO IN

6

PFD OUT

AVAILABLE OPTIONS

T

A

–20°C to 75°C TLC2933PWLE

SMALL OUTLINE

BIAS

VCO INHIBIT

TEST

PACKAGE

(PW)

12 13

Voltage-

Controlled

10

Oscillator

2

Copyright  1997, Texas Instruments Incorporated

3

VCO OUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TLC2933

I/O

DESCRIPTION

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

Terminal Functions

TERMINAL

NAME NO.

BIAS 13 I Bias supply. An external resistor (R

FIN–A 4 I Input reference frequency f FIN–B 5 I Input for VCO external counter output frequency f

LOGIC GND 7 Ground for the internal logic. LOGIC V

NC 8 No internal connection. PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD OUT is in the high-impedance state, see Table 2. PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD OUT is in the high-impedance state. TEST 2 I Test terminal. TEST connects to ground for normal operation. VCO GND 11 Ground for VCO. VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO

VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 1). VCO OUT 3 O VCO output. When VCO INHIBIT is high, VCO OUT is low. VCO V

DD

1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce

14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling

oscillation frequency range.

(REF IN)

counter.

cross-coupling between supplies.

oscillation frequency .

between supplies.

) between VCO VDD and BIAS supplies bias for adjusting the

BIAS

is applied to FIN–A.

(FIN–B)

. FIN–B is nominally provided from the external

detailed description

VCO oscillation frequency

The VCO oscillation frequency is determined by an external resistor (R and the BIAS terminals. The oscillation frequency and range depends on this resistor value. While all resistor values within the specified range result in excellent low temperature coefficients, the bias resistor value for the minimum temperature coefficient is nominally 2.2 kΩ with 3-V V

and nominally 2.4 kΩ with 5-V VDD. For the

DD

lock frequency range refer to the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.

VCO Oscillation Frequency Range

osc

(f )

VCO Oscillation Frequency

1/2 V

VCO Control Voltage (VCO IN)

Bias Resistor (R

DD

BIAS

)

) connected between the VCO V

BIAS

DD

Figure 1. VCO Oscillation Frequency

2

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HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

VCO inhibit function

The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during the power-down mode as shown in Table 1.

Table 1. VCO Inhibit Function

TLC2933

VCO INHIBIT VCO OSCILLATOR VCO OUT I

Low Active Active Normal

High Stopped Low level Power Down

DD(VCO)

PFD operation

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B. For clock recovery PLL systems, other types of phase detectors should be used.

FIN–A

FIN–B

V

OH

PFD OUT

Hi-Z

V

OL

Figure 2. PFD Function Timing Chart

PFD inhibit control

A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops phase detection as shown in Table 2. A high level on the PFD INHIBIT terminal can also be used as the power-down mode for the PFD.

Table 2. VCO Output Control Function

PFD INHIBIT DETECTION PFD OUT I

Low Active Active Normal

High Stopped Hi-Z Power Down

DD(PFD)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

schematics

VCO block schematic

R

BIAS

VCO

Output

Buffer

VCO OUT

VCO IN

VCO INHIBIT

Bias

Control

PFD block schematic

Charge Pump

V

DD

FIN–A

Detector

FIN–B

PFD INHIBIT

absolute maximum ratings

Supply voltage (each supply), V Input voltage range (each input), V Input current (each input), I Output current (each output), I

†

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

(see Note 1) –0.3 V to V

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Continuous total power dissipation at (or below) T Operating free-air temperature range, T Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

= 25°C (see Note 2) 700 mW. . . . . . . . . . . . . . . . . . . . . . .

–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

PFD OUT

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to network ground terminal.

2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage, V

(each suppl

see Note 3)

V

Lock frequenc

MH

Bias resistor, R

kΩ

TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

recommended operating conditions

MIN NOM MAX UNIT

pp

y v

Input voltage, VI (inputs except VCO IN) 0 V Output current, IO (each output) 0 ±2 mA VCO control voltage at VCO IN 1 V

NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and

separated from each other.

y

BIAS

DD

pp

y,

electrical characteristics over recommended operating free-air temperature range, VDD = 3 V (unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

V

IT+

I

Z

i(VCO IN)

I

DD(INH)

I

DD(VCO)

NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.

High-level output voltage IOH = –2 mA 2.4 V Low-level output voltage IOL = 2 mA 0.3 V Positive input threshold voltage at TEST, VCO INHIBIT 0.9 1.5 2.1 V Input current at TEST, VCO INHIBIT VI = VDD or ground ±1 µA Input impedance at VCO IN VCO IN = 1/2 V VCO supply current (inhibit) See Note 4 0.01 1 µA VCO supply current See Note 5 5.1 15 mA

5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, R is high.

VDD = 3 V 2.85 3 3.15 VDD = 5 V 4.75 5 5.25

DD

VDD = 3 V 37 55 VDD = 5 V 43 100 VDD = 3 V 1.8 2.7 VDD = 5 V 2.2 3

DD

= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT

BIAS

10 MΩ

V

z

PFD section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

I

OZ

V

IH

V

IL

V

IT+

C

i

Z

i

I

DD(Z)

I

DD(PFD)

NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.

High-level output voltage IOH = –2 mA 2.7 V Low-level output voltage IOL = 2 mA 0.2 V

High-impedance-state output current High-level input voltage at FIN–A, FIN–B 2.1 V

Low-level input voltage at FIN–A, FIN–B 0.9 V Positive input threshold voltage at PFD INHIBIT 0.9 1.5 2.1 V Input capacitance at FIN–A, FIN–B 5 pF Input impedance at FIN–A, FIN–B 10 MΩ High-impedance-state PFD supply current See Note 6 0.01 1 µA PFD supply current See Note 7 0.7 4 mA

7. The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V open, and VCO OUT is inhibited.

PFD INHIBIT = high, VI = VDD or ground

= 3 V , rectangular wave), PFD INHIBIT = GND, PFD OUT

I(PP)

±1 µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC2933

ns

See Figures 4 and 5 and Table 3

ns

C

15 pF

See Figure 4

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

operating characteristics over recommended operating free-air temperature range, VDD = 3 V (unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

osc

t

s(fosc)

t

r

t

f

α

(fosc)

k

SVS(fosc)

NOTES: 8. The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.

PFD section

f

max

t

PLZ

t

PHZ

t

PZL

t

PZH

t

r

t

f

Operating oscillation frequency R Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs Rise time, VCO OUT↑ CL = 15 pF, See Figure 3 3.3 10 ns Fall time, VCO OUT↓ CL = 15 pF, See Figure 3 2 8 ns Duty cycle at VCO OUT R

Temperature coefficient of oscillation frequency

Supply voltage coefficient of oscillation frequency

Jitter absolute (see Note 9) R

9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with a carefully designed printed circuit board (PCB) with no device socket.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Maximum operating frequency 30 MHz Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z 20 40 Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z Enable time, PFD INHIBIT↓ to PFD OUT low Enable time, PFD INHIBIT↓ to PFD OUT high 4.8 18 Rise time, PFD OUT↑ Fall time, PFD OUT↓

= 2.4 kΩ, VCO IN = 1/2 V

BIAS

= 2.4 kΩ, VCO IN = 1/2 V

BIAS

R

= 2.4 kΩ, VCO IN = 1/2 VDD,

BIAS

TA = –20°C to 75°C R

= 2.4 kΩ, VCO IN = 1.5 V,

BIAS

VDD = 2.85 V to 3.15 V

= 2.4 kΩ 100 ps

BIAS

p

,

=

L

DD

38 48 55 MHz

45% 50% 55%

0.03 %/°C

0.04 %/mV

18 40

4.1 18

3.1 9 ns

1.5 9 ns

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V (unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

V

IT+

I

Z

i(VCO IN)

I

DD(INH)

I

DD(VCO)

NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD, and PFD INHIBIT high.

PFD section

V

OH

V

OL

I

OZ

V

IH

V

IL

V

IT+

C

i

Z

i

I

DD(Z)

I

DD(PFD)

NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.

High-level output voltage IOH = –2 mA 4.5 V Low-level output voltage IOL = 2 mA 0.5 V Positive input threshold voltage at TEST, VCO INHIBIT 1.5 2.5 3.5 V Input current at TEST, VCO INHIBIT VI = VDD or ground ±1 µA Input impedance at VCO IN VCO IN = 1/2 V VCO supply current (inhibit) See Note 4 0.01 1 µA VCO supply current See Note 5 14 35 mA

5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, R high.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage IOH = 2 mA 4.5 V Low-level output voltage IOL = 2 mA 0.2 V

High-impedance-state output current High-level input voltage at FIN–A, FIN–B 3.5 V

Low-level input voltage at FIN–A, FIN–B 1.5 V Positive input threshold voltage at PFD INHIBIT 1.5 2.5 3.5 V Input capacitance at FIN–A, FIN–B 7 pF Input impedance at FIN–A, FIN–B 10 MΩ High-impedance-state PFD supply current See Note 6 0.01 1 µA PFD supply current See Note 10 2.6 8 mA

10. The current into LOGIC VDD when FIN–A and FIN–B = 50 MHz (V open, and VCO OUT is inhibited.

I(PP)

= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT

BIAS

PFD INHIBIT = high, VI = VDD or ground

= 3 V , rectangular wave), PFD INHIBIT = ground, PFD OUT

DD

10 MΩ

±1 µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TLC2933

ns

See Figures 4 and 5 and Table 3

ns

C

15 pF, See Figure 4

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

operating characteristics over recommended operating free-air temperature range, VDD = 5 V (unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

osc

t

s(fosc)

t

r

t

f

α

(fosc)

k

SVS(fosc)

NOTES: 8: The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.

PFD section

f

max

t

PLZ

t

PHZ

t

PZL

t

PZH

t

r

t

f

Operating oscillation frequency R Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs Rise time, VCO OUT↑ CL = 15 pF, See Figure 3 2.1 5 ns Fall time, VCO OUT↓ CL = 15 pF, See Figure 3 1.5 4 ns Duty cycle at VCO OUT R

Temperature coefficient of oscillation frequency

Supply voltage coefficient of oscillation frequency

Jitter absolute (see Note 9) R

9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with a carefully designed printed circuit board (PCB) with no device socket.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Maximum operating frequency 50 MHz Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z 20 40 Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z Enable time, PFD INHIBIT↓ to PFD OUT low Enable time, PFD INHIBIT↓ to PFD OUT high 3.4 10 Rise time, PFD OUT↑ Fall time, PFD OUT↓

= 2.4 kΩ,, VCO IN = 1/2 V

BIAS

= 2.4 kΩ, VCO IN = 1/2 V

BIAS

R

= 2.4 kΩ, VCO IN = 1/2 VDD,

BIAS

TA = –20°C to 75°C R

= 2.4 kΩ, VCO IN = 2.5 V,

BIAS

VDD = 4.75 V to 5.25 V

= 2.4 kΩ 100 ps

BIAS

p

=

L

DD

64 80 96 MHz

45% 50% 55%

0.03 %/°C

0.02 %/mV

17 40

3.7 10

1.7 5 ns

1.3 5 ns

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1 kΩ

15 pF

TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

PARAMETER MEASUREMENT INFORMATION

FIN–A

FIN–B

PFD INHIBIT

PFD OUT

VCO OUT

90%

10%

Figure 3. VCO Output Voltage Waveform

†

90%

50%

t

r

50%

PHZ

50% 50%

10%

t

PZH

(a) PFD OUT Hi-Z Timing To and From a High Level

(see Figure 5 and Table 3)

t

r

V

DD

GND V

DD

GND

V

DD

GND

V

OH

Hi-Z

90%

10%

t

f

50%

t

f

90%

t

PZL

(b) PFD OUT Hi-Z Timing To and From a Low Level

50%

10%

(see Figure 5 and Table 3)

50%

PLZ

V

DD

GND V

DD

GND

V

DD

GND

Hi-Z

V

OL

†

FIN–A and FIN–B are for reference phase only, not for timing.

Figure 4. PFD Output Voltage Waveform

Table 3. PFD Output Test Conditions

PARAMETER R

t

PZH

t

PHZ

t

r

t

PZL

t

PLZ

t

f

C

L

p

S

1

Open Closed

Closed Open

S

2

V

DD

S1

S2

DUT

PFD OUT

Test Point

R

L

C

L

Figure 5. PFD Output Test Conditions

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9

TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

TYPICAL CHARACTERISTICS

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

90

VDD = 3 V

80

R

= 1.8 kΩ

BIAS

70

60

50

40

30

20

– VCO Oscillation Frequency – MHz

osc

10

f

0

0 0.3 0.6 0.9 1.2 1.5 1.8

VCO IN – VCO Control Voltage – V

Figure 6

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

80

VDD = 3 V

70

R

= 2.4 kΩ

BIAS

60

–20°C

25°C

2.1 2.4 2.7 3

–20°C

75°C

25°C

75°C

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

90

VDD = 3 V

80

R

= 2.2 kΩ

BIAS

70

60

50

40

30

20

– VCO Oscillation Frequency – MHz

osc

10

f

0

0 0.3 0.6 0.9 1.2 1.5 1.8

–20°C

VCO IN – VCO Control Voltage – V

Figure 7

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

80

VDD = 3 V

70

R

= 2.7 kΩ

BIAS

60

–20°C

25°C

75°C

2.1 2.4 2.7 3

25°C

50

40

30

20

– VCO Oscillation Frequency – MHz

osc

10

f

0

0 0.8 0.6 0.9 1.2 1.5

–20°C

VCO IN – VCO Control Voltage – V

Figure 8

10

– VCO Oscillation Frequency – MHz

osc

f

1.8 2.1 2.4 2.7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

50

40

75°C

30

20

10

0

0 0.3 0.6 0.9 1.2 1.5

VCO IN – VCO Control Voltage – V

Figure 9

–20°C

1.8 2.1 2.4 2.7

3

TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

TYPICAL CHARACTERISTICS

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

160

VDD = 5 V

140

R

= 2.2 kΩ

BIAS

120

100

80

60

75°C

40

– VCO Oscillation Frequency – MHz

osc

f

–20°C

20

0

0 0.5 1 1.5 2 2.5 3

VCO IN – VCO Control Voltage – V

Figure 10

VCO OSCILLATION FREQUENCY

VCO CONTROL VOLTAGE

140

VDD = 5 V R

= 2.7 kΩ

120

100

BIAS

80

vs

–20°C

25°C

75°C

3.5 4 4.5 5

–20°C

25°C

75°C

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

160

VDD = 5 V R

140

120

100

80

60

75°C

40

– VCO Oscillation Frequency – MHz

osc

20

f

0

0 0.5 1 1.5 2 2.5

= 2.4 kΩ

BIAS

–20°C

VCO IN – VCO Control Voltage – V

Figure 11

VCO OSCILLATION FREQUENCY

vs

VCO CONTROL VOLTAGE

140

VDD = 5 V R

= 3 kΩ

120

100

BIAS

80

–20°C

25°C

75°C

3 3.5 4 4.5

–20°C

25°C

75°C

5

60

75°C

40

– VCO Oscillation Frequency – MHz

20

osc

f

–20°C

0

0 0.5 1 1.5 2 2.5 3

VCO IN – VCO Control Voltage – V

Figure 12

60

40

75°C

– VCO Oscillation Frequency – MHz

20

osc

f

3.5 4 4.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

–20°C

0

0 0.5 1 1.5 2 2.5 3

3.5 4 4.5

VCO IN – VCO Control Voltage – V

Figure 13

5

11

TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

TYPICAL CHARACTERISTICS

RECOMMENDED LOCK FREQUENCY

vs

BIAS RESISTOR

60

VDD = 3 V ± 5% TA = –20°C to 75°C

55

50

45

40

35

Recommended Lock Frequency – MHz

30

1.8 2.2 R

– Bias Resistor – kΩ

BIAS

Figure 14

MAX

MIN

2.4 2.7

RECOMMENDED LOCK FREQUENCY

vs

BIAS RESISTOR

110

100

90

80

70

60

50

Recommended Lock Frequency – MHz

40

30

2.2 2.4 R

– Bias Resistor – kΩ

BIAS

VDD = 5 V ± 5% TA = –20°C to 75°C

Figure 15

MAX

MIN

2.7 3

12

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TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

APPLICATION INFORMATION

gain of VCO and PFD

Figure 16 is a block diagram of the PLL. The divider N value depends on the input frequency and the desired VCO output frequency according to the system application requirements. The K and KV values are obtained from the operating characteristics of the device as shown in Figure 16. K V

and VOH specifications and the equation

OL

shown in Figure 16(b). K

is defined from the phase detector

p

is defined from

V

Figures 8, 9, 10, and 1 1 as shown in Figure 16(c). The parameters for the block diagram with the

units are as follows:

K

: VCO gain (rad/s/V)

V

K

: PFD gain (V/rad)

p

K

: LPF gain (V/V)

f

K

: countdown divider gain (1/N)

N

external counter

When a large N counter is required by the application, there is a possibility that the PLL response becomes slow due to the counter response delay time. In the case of a high frequency application, the counter delay time should be accounted for in the overall PLL design.

p

–2π 2π–π 0 π

Divider

(KN = 1/N)

f REF

Range of

Comparison

VOH – V

Kp =

4π

OL

PFD (Kp)

TLC2933

V

OH

V

OL

LPF (Kf)

(a)

f

MAX

f

MIN

KV =

VCO (KV)

V

OH

VIN

MIN

2π(f

MAX

(c)(b)

VIN

– f

– VIN

Figure 16. Example of a PLL Block Diagram

MIN

MAX )

MIN

R

BIAS

The external bias resistor sets the VCO center frequency with 1/2 V

applied to the VCO IN terminal. For the

DD

most accurate results, a metal-film resistor is the better choice but a carbon-composition resistor can also be used with excellent results. A 0.22 µF capacitor should be connected from the BIAS terminal to ground as close to the device terminals as possible.

hold-in range

From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter configurations shown in Figure 17 is as follows:

ǒ

Ǔǒ

Where

DwH]

K

0.8

K

p

(∞) = the filter transfer function value at ω = ∞

f

K

V

Ǔǒ

Kf(R)

Ǔ

(1)

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TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

APPLICATION INFORMATION

low-pass-filter (LPF) configurations

Many excellent references are available that include detailed design information about LPFs and should be consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown in Figure 17. When the active filter of Figure 17(c) is used, the reference should be applied to FIN-B because of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO input. The value of C2 should be equal to or less than one tenth the value of C1.

V

R1

I

T1 = C1R1

(a) LAG FILTER

C1

V

O

V

R1

I

T1 = C1R1 T2 = C1R2

(b) LAG-LEAD FILTER

R2

C1

C2

V

O

V

I

R1

(c) ACTIVE FILTER

R2

–

C2

A

C1

T1 = C1R1 T2 = C1R2

V

O

Figure 17. LPF Examples for PLL

the passive filter

The transfer function for the low-pass filter shown in Figure 17(b) is;

V

O

V

IN

+

1)s

@

T2

@

(

T1)T2

)

where

T1+R1

C1 and T2+R2@C1

@

Using this filter makes the closed-loop PLL system a type 1 second-order system. The response curves of this system to a unit step are shown in Figure 18.

the active filter

When using the active filter shown in Figure 17(c), the phase detector inputs must be reversed since the filter adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.

The transfer function for the active filter shown in Figure 17(c) is:

1)s

@

F(s)

+

Using this filter makes the closed-loop PLL system a type 2 second-order system. The response curves of this system to a unit step are shown in Figure 19.

s

@R1@

R2@C1

C1

(2)

(3)

14

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HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

APPLICATION INFORMATION

Using the lag-lead filter in Figure 17(b) and divider N value, the transfer function for phase and frequency are shown in equations 4 and 5. Note that the transfer function for phase differs from the transfer function for frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity while the feedback for frequency is 1/N.

Hence, the transfer function of Figure 17(a) for phase is

TLC2933

ȱ

K

@

N

@

p

(

T1)T2

F

2(s)

+

F

1(s)

and the transfer function for frequency is

ȧ

V

ȧ

)

ȧ

s2)

ƪ

1

s

Ȳ

)

K

p

N

@

1)s@T2 K

T2

@

V

(T1)T2)

K

@

)

p

N

(T1)T2)

@

ƫ

ȱ

F

OUT(s)

F

REF(s)

The standard 2-pole denominator is D = s of equation (4) and (5) with the standard 2-pole denominator gives the following results.

Solving for T1 + T2

+

wn+

T1)T2

K

@

p

(

T1)T2

K

Ǹ

N

@

K

+

K

ȧ

V

ȧ

)

ȧ

s2)

Ȳ

K

@

p (T1)T2)

K

@

p

V

w

N

@

n

1)s@T2

K

T2

@

p

ƪ

1

@

)

2

s

V

2

V

N@(T1)T2)

+ 2 ζ ωn s + ω

ƫ

K

@

p

)

N@(T1)T2)

2

and comparing the coefficients of the denominator

n

V

ȳ ȧ

ȧ ȧ

K

ȧ

V

ȴ

ȳ ȧ

ȧ ȧ ȧ

ȴ

(4)

(5)

(6)

and by using this value for T1 + T2 in equation (6) the damping factor is

w

n

z

+

solving for T2

T2

+

then by substituting for T2 in equation (6)

T1

+

ǒ

T2

@

2

z

N

–

w

K

@

p

K

@

p

V

N

@

–

2

w

n

)

N

K

p

K

V

2

z

w

n

Ǔ

K

@

V

N

)

K

@

p

V

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(7)

(8)

(9)

15

TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

APPLICATION INFORMATION

From the circuit constants and the initial design parameters then

2

ȱ ȧ

Ȳ

z

ƪ

w

n

K

@

p

2

w

n

R2

+

R1

+

The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and physical capacitor size.

*

N

K

@

p

K

v

2

*

w

N

@

1

ƫ

K

C1

V

z

)

K

n

p

ȳ

N

@

1

ȧ

K

C1

V

ȴ

(10)

(11)

16

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TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

APPLICATION INFORMATION

1.9

1.8 = 0.1

z

1.7

1.6

1.5

1.4

1.3

1.2

1.1

= 0.6

z

= 0.7

z

= 0.8

z

= 0.2

z

= 0.3

z

= 0.4

z

= 0.5

z

1

0.9

0.8

Normalized Gain Response

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

012345678910111213

= 1.0

z

= 1.5

z

= 2.0

z

ωnts = 4.5

ω

nt

Figure 18. Type 1 Second-Order Step Response

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TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

APPLICATION INFORMATION

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

0.9

0.8

Normalized Gain Response

0.7

ζ = 0.1

ζ = 0.2

ζ = 0.3

ζ = 0.4

ζ = 0.5 ζ = 0.6

ζ = 0.7

ζ = 0.8

ζ = 1.0

ζ = 2.0

0.6

0.5

0.4

0.3

0.2

0.1

0

012345678910111213

ω

nt

Figure 19. Type 2 Second-Order Step Response

18

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REF IN

TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

APPLICATION INFORMATION

AV

R1

DD

†

R3

R2C2

C1

V

DD

1

LOGIC VDD (Digital)

TEST

2

3

VCO OUT

FIN–A

4

VCO

VCO V

VCO IN

VCO GND

DD

BIAS

14

13

0.22 µF

12

11

NC

DV

10

9

8

DD

R5 R6

AGND

S1

S2

DGND

5

FIN–B

PFD OUT

6

7

LOGIC GND (Digital)

Divide

By

N

†

R

resistor

BIAS

DGND

Phase

Comparator

VCO INHIBIT

PFD INHIBIT

Figure 20. Evaluation and Operation Schematic

PCB layout considerations

The TLC2933 contains a high frequency oscillator; therefore, very careful breadboarding and PCB layout is required for evaluation.

The following design recommendations benefit the TLC2933 user:

D

External analog and digital circuitry should be physically separated and shielded as much as possible to reduce system noise.

D

Radio frequency (RF) breadboarding or RF PCB techniques should be used throughout the evaluation and production process.

D

Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance and resistance. The ground plane is the better choice for noise reduction.

D

LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point available in the system to minimize supply cross-coupling.

D

VCO VDD to ground and LOGIC VDD to ground should be decoupled with a 0.1-µF capacitor placed as close as possible to the appropriate device terminals.

D

The no-connection (NC) terminal on the package should be connected to ground to prevent stray pickup.

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19

TLC2933 HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

20

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IMPORTANT NOTICE

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