Page 1
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
D
Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One
External Bias Resistor (R
BIAS
– Lock Frequency:
22 MHz to 50 MHz (V
= 5 V ±5%,
DD
TA = –20°C to 75°C, ×1 Output)
11 MHz to 25 MHz (VDD = 5 V ±5%,
TA = –20°C to 75°C, ×1/2 Output)
– Output Frequency . . . ×1 and ×1/2
Selectable
D
Phase-Frequency Detector (PFD) Section
Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump
D
Independent VCO, PFD Power-Down Mode
D
Thin Small-Outline Package (14 terminal)
D
CMOS Technology
D
Typical Applications:
– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division
D
Application Report Available
D
CMOS Input Logic Level
†
description
PW PACKAGE
(TOP VIEW)
)
LOGIC V
LOGIC GND
†
Available in tape and reel only and ordered as the
TLC2932IPWLE.
NC – No internal connection
DD
SELECT
VCO OUT
FIN–A
FIN–B
PFD OUT
1
2
3
4
5
6
7
†
14
13
12
11
10
9
8
VCO V
DD
BIAS
VCO
IN
VCO GND
VCO INHIBIT
PFD INHIBIT
NC
The TLC2932 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (R
). The VCO has a 1/2 frequency divider at the output stage.
BIAS
The high-speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as a power-down mode. The TLC2932 is suitable for use as a high-performance PLL due
to the high speed and stable oscillation capability of the device.
functional block diagram
4
FIN–A
FIN–B
PFD INHIBIT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
TLC2932 Phase-Locked-Loop Building Block With Analog Voltage-Controlled Oscillator and Phase Frequency Detector (SLAA011).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
5
Frequency
9
Detector
Phase
6
PFD OUT
AVAILABLE OPTIONS
T
A
–20°C to 75°C TLC2932IPWLE
VCO IN
BIAS
VCO INHIBIT
SELECT
PACKAGE
SMALL OUTLINE
(PW)
12
13
Voltage-
Controlled
10
Oscillator
2
Copyright 1997, Texas Instruments Incorporated
3
VCO OUT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
Page 2
TLC2932
I/O
DESCRIPTION
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
Terminal Functions
TERMINAL
NAME NO.
FIN–A 4 I Input reference frequency f
FIN–B 5 I Input for VCO external counter output frequency f
LOGIC GND 7 GND for the internal logic.
LOGIC V
NC 8 No internal connection.
PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state, see Table 3.
PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
BIAS 13 I Bias supply. An external resistor (R
SELECT 2 I VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when low, the
VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 2).
VCO GND 11 GND for VCO.
VCO OUT 3 O VCO output. When the VCO INHIBIT is high, VCO output is low.
VCO V
DD
DD
1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce
14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling
counter.
cross-coupling between supplies.
oscillation frequency range.
output frequency is ×1, see Table 1.
oscillation frequency .
between supplies.
(REF IN)
is applied to FIN–A.
(FIN–B)
) between VCO VDD and BIAS supplies bias for adjusting the
BIAS
. FIN–B is nominally provided from the external
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external resistor (R
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. The bias resistor
value for the minimum temperature coefficient is nominally 3.3 kΩ with 3-V at the VCO V
nominally 2.2 kΩ with 5-V at the VCO V
terminal. For the lock frequency range refer to the recommended
DD
operating conditions. Figure 1 shows the typical frequency variation and VCO control voltage.
VCO Oscillation Frequency Range
osc
(f )
VCO Oscillation Frequency
1/2 V
VCO Control Voltage (VCO IN)
Bias Resistor (R
DD
BIAS
)
) connected between the VCO V
BIAS
DD
terminal and
DD
Figure 1. VCO Oscillation Frequency
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
VCO output frequency 1/2 divider
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
The TLC2932 SELECT terminal sets the f
f
output should be used for minimum VCO output jitter.
osc
osc
or 1/2 f
VCO output frequency as shown in Table 1. The 1/2
osc
Table 1. VCO Output 1/2 Divider Function
SELECT VCO OUTPUT
Low f
High 1/2 f
osc
osc
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode, refer to Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT VCO OSCILLATOR VCO OUTPUT I
Low Active Active Normal
High Stopped Low level Power Down
DD(VCO)
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B.
FIN–A
FIN–B
V
OH
PFD OUT
Hi-Z
V
OL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on the PFD INHIBIT terminal places the PFD output in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal also can be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT DETECTION PFD OUTPUT I
Low Active Active Normal
High Stopped Hi-Z Power Down
DD(PFD)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
schematics
VCO block schematic
R
BIAS
VCO IN
VCO INHIBIT
PFD block schematic
BIAS
Bias
Control
Charge Pump
V
DD
VCO
Output
1/2
M
U
X
SELECT
VCO OUT
FIN–A
PFD OUT
PFD INHIBIT
absolute maximum ratings
Detector
FIN–B
†
Supply voltage (each supply), VDD (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range (each input), VI (see Note 1) –0.5 V to V
DD
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (each input), II ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current (each output), I
±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous total power dissipation, at (or below) TA = 25°C (see Note 2) 700 mW. . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
Suppl
oltage, V
(each suppl
see Note 3)
V
Lock frequency (×1 output)
MH
Lock frequency (×1/2 output)
MH
Bias resistor, R
kΩ
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
recommended operating conditions
PARAMETER MIN NOM MAX UNIT
pp
y v
Input voltage, VI (inputs except VCO IN) 0 V
Output current, IO (each output) 0 ±2 mA
VCO control voltage at VCO IN 0.9 V
NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) should be at the same voltage
and separated from each other.
DD
BIAS
pp
y,
p
p
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VDD = 3 V 2.85 3 3.15
VDD = 5 V 4.75 5 5.25
DD
DD
VDD = 3 V 14 21
VDD = 5 V 22 50
VDD = 3 V 7 10.5
VDD = 5 V 11 25
VDD = 3 V 2.2 3.3 4.3
VDD = 5 V 1.5 2.2 3.3
V
V
z
z
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
V
OL
V
IT
I
I
Z
i(VCO IN)
I
DD(INH)
I
DD(VCO)
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, PFD is inhibited.
High-level output voltage IOH = –2 mA 2.4 V
Low-level output voltage IOL = 2 mA 0.3 V
Input threshold voltage at SELECT, VCO INHIBIT 0.9 1.5 2.1 V
Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA
Input impedance VCO IN = 1/2 V
VCO supply current (inhibit) See Note 4 0.01 1 µA
VCO supply current See Note 5 5 15 mA
5. Current into VCO VDD, when VCO IN = 1/2 VDD, R
= 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
BIAS
DD
10 MΩ
PFD section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
V
OL
I
OZ
V
IH
V
IL
V
IT
C
i
Z
i
I
DD(Z)
I
DD(PFD)
NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.
High-level output voltage IOH = –2 mA 2.7 V
Low-level output voltage IOL = 2 mA 0.2 V
High-impedance-state output current
High-level input voltage at FIN–A, FIN–B 2.7 V
Low-level input voltage at FIN–A, FIN–B 0.5 V
Input threshold voltage at PFD INHIBIT 0.9 1.5 2.1 V
Input capacitance at FIN–A, FIN–B 5 pF
Input impedance at FIN–A, FIN–B 10 MΩ
High-impedance-state PFD supply current See Note 6 0.01 1 µA
PFD supply current See Note 7 0.1 1.5 mA
7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (V
inhibited.
I(PP)
PFD INHIBIT = high,
VI = VDD or GND
= 3 V, rectangular wave), NC = GND, no load, and VCO OUT is
±1 µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
TLC2932
trRise time
ns
tfFall time
ns
ns
See Figures 4 and 5 and Table 4
ns
C
See Figure 4
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
operating characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
osc
t
s(fosc)
α
(fosc)
k
SVS(fosc)
NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
Operating oscillation frequency R
Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs
Duty cycle at VCO OUT R
Temperature coefficient of oscillation frequency
Supply voltage coefficient of oscillation frequency
Jitter absolute (see Note 9) R
9. The low-pass-filter (LPF) circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent
on circuit layout and external device characteristics. The jitter specification was made with a carefully designed PCB with no device
socket.
= 3.3 kΩ, VCO IN = 1/2 V
BIAS
CL = 15 pF, See Figure 3 7 14
CL = 50 pF, See Figure 3 14
CL = 15 pF, See Figure 3 6 12
CL = 50 pF, See Figure 3 10
= 3.3 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%
BIAS
R
= 3.3 kΩ, VCO IN = 1/2 VDD,
BIAS
TA = –20°C to 75°C
R
= 3.3 kΩ, VCO IN = 1.5 V,
BIAS
VDD = 2.85 V to 3.15 V
= 3.3 kΩ 100 ps
BIAS
DD
15 19 23 MHz
0.04 %/°C
0.02 %/mV
PFD section
f
max
t
PLZ
t
PHZ
t
PZL
t
PZH
t
r
t
f
Maximum operating frequency 20 MHz
PFD output disable time from low level 21 50
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level 10 30
Rise time
Fall time
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
23 50
11 30
p
= 15 pF,
L
2.3 10 ns
2.1 10 ns
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
V
OL
V
IT
I
I
Z
i(VCO IN)
I
DD(INH)
I
DD(VCO)
NOTES: 4. Current into VCO VDD, when VCO INHIBIT = VDD, and PFD is inhibited.
PFD section
V
OH
V
OL
I
OZ
V
IH
V
IL
V
IT
C
i
Z
i
I
DD(Z)
I
DD(PFD)
NOTES: 6. Current into LOGIC VDD, when FIN–A, FIN–B = GND, PFD INHIBIT = VDD, no load, and VCO OUT is inhibited.
High-level output voltage IOH = –2 mA 4 V
Low-level output voltage IOL = 2 mA 0.5 V
Input threshold voltage at SELECT, VCO INHIBIT 1.5 2.5 3.5 V
Input current at SELECT, VCO INHIBIT VI = VDD or GND ±1 µA
Input impedance VCO IN = 1/2 V
VCO supply current (inhibit) See Note 4 0.01 1 µA
VCO supply current See Note 5 15 35 mA
5. Current into VCO VDD, when VCO IN = 1/2 VDD, R
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level output voltage IOH = 2 mA 4.5 V
Low-level output voltage IOL = 2 mA 0.2 V
High-impedance-state output current
High-level input voltage at FIN–A, FIN–B 4.5 V
Low-level input voltage at FIN–A, FIN–B 1 V
Input threshold voltage at PFD INHIBIT 1.5 2.5 3.5 V
Input capacitance at FIN–A, FIN–B 5 pF
Input impedance at FIN–A, FIN–B 10 MΩ
High-impedance-state PFD supply current See Note 6 0.01 1 µA
PFD supply current See Note 7 0.15 3 mA
7. Current into LOGIC VDD, when FIN–A, FIN–B = 1 MHz (V
VCO OUT is inhibited.
= 3.3 kΩ, VCO INHIBIT = GND, and PFD is inhibited.
BIAS
PFD INHIBIT = high,
VI = VDD or GND
= 5 V, rectangular wave), PFD INHIBIT = GND, no load, and
I(PP)
DD
10 MΩ
±1 µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
TLC2932
trRise time
ns
tfFall time
ns
ns
See Figures 4 and 5 and Table 4
ns
C
See Figure 4
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
operating characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)
VCO section
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
osc
t
s(fosc)
α
(fosc)
k
SVS(fosc)
NOTES: 8: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
Operating oscillation frequency R
Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs
Duty cycle at VCO OUT R
Temperature coefficient of oscillation frequency
Supply voltage coefficient of oscillation frequency
Jitter absolute (see Note 9) R
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 7. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
= 2.2 kΩ, VCO IN = 1/2 V
BIAS
CL = 15 pF, See Figure 3 5.5 10
CL = 50 pF, See Figure 3 8
CL = 15 pF, See Figure 3 5 10
CL = 50 pF, See Figure 3 6
= 2.2 kΩ, VCO IN = 1/2 VDD, 45% 50% 55%
BIAS
R
= 2.2 kΩ, VCO IN = 1/2 VDD,
BIAS
TA = –20°C to 75°C
R
= 2.2 kΩ, VCO IN = 2.5 V,
BIAS
VDD = 4.75 V to 5.25 V
= 2.2 kΩ 100 ps
BIAS
DD
30 41 52 MHz
0.06 %/°C
0.006 %/mV
PFD section
f
max
t
PLZ
t
PHZ
t
PZL
t
PZH
t
r
t
f
Maximum operating frequency 40 MHz
PFD output disable time from low level 21 40
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level 6.5 20
Rise time
Fall time
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
20 40
7.3 20
p
= 15 pF,
L
2.3 10 ns
1.7 10 ns
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
1 kΩ
15 pF
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
FIN–A
FIN–B
PFD INHIBIT
PFD OUT
VCO OUT
10%
90%
t
r
90%
10%
t
f
Figure 3. VCO Output Voltage Waveform
V
†
†
50%
t
t
r
90%
10%
t
PZH
(a) OUTPUT PULLDOWN
(see Figure 5 and Table 4)
50%
50%
PHZ
DD
GND
V
DD
GND
V
DD
GND
V
OH
GND
t
PZL
90%
50%
t
t
f
50%
10%
(b) OUTPUT PULLUP
(see Figure 5 and Table 4)
50%
PLZ
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
V
OL
†
FIN–A and FIN–B are for reference phase only, not for timing.
Figure 4. PFD Output Voltage Waveform
Table 4. PFD Output Test Conditions
PARAMETER R
t
PZH
t
PHZ
t
r
t
PZL
t
PLZ
t
f
C
L
L
p
S
1
Open Close
Close Open
S
2
V
DD
S1
S2
DUT
PFD OUT
Test Point
C
R
L
L
Figure 5. PFD Output Test Conditions
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
Page 10
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
40
VDD = 3 V
R
= 2.2 kΩ
BIAS
30
20
10
– VCO Oscillation Frequency – MHz
osc
f
0
01 2 3
VCO IN – VCO Control Voltage – V
–20°C
25°C
75°C
Figure 6
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
40
VDD = 3 V
R
= 3.3 kΩ
BIAS
30
–20°C
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
100
VDD = 5 V
R
= 1.5 kΩ
BIAS
80
60
40
– VCO Oscillation Frequency – MHz
20
osc
f
0123
VCO IN – VCO Control Voltage – V
Figure 7
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VDD = 5 V
R
= 2.2 kΩ
BIAS
60
–20°C
25°C
75°C
45
–20°C
75°C
20
10
– VCO Oscillation Frequency – MHz
osc
f
0
0123
VCO IN – VCO Control Voltage – V
Figure 8
10
75°C
25°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
40
20
– VCO Oscillation Frequency – MHz
osc
f
0
01238045
25°C
VCO IN – VCO Control Voltage – V
Figure 9
Page 11
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
40
VDD = 3 V
R
= 4.3 kΩ
BIAS
30
75°C
20
10
– VCO Oscillation Frequency – MHz
osc
f
0
0123
VCO IN – VCO Control Voltage – V
25°C
–20°C
Figure 10
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
30
VDD = 3 V
VCO IN = 1/2 V
TA = 25°C
DD
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VDD = 5 V
R
= 3.3 kΩ
BIAS
60
40
20
– VCO Oscillation Frequency – MHz
osc
f
0
25°C
75°C
–20°C
01238045
VCO IN – VCO Control Voltage – V
Figure 11
VCO OSCILLATION FREQUENCY
vs
BIAS RESISTOR
60
VDD = 5 V
VCO IN = 1/2 V
TA = 25°C
DD
25
20
15
– VCO Oscillation Frequency – MHz
osc
f
10
2 2.5 3.5 4 4.5
3
R
– Bias Resistor – kΩ
BIAS
Figure 12
50
40
30
– VCO Oscillation Frequency – MHz
osc
f
20
1.5 2 2.5 3.5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
R
– Bias Resistor – kΩ
BIAS
Figure 13
3
11
Page 12
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
TYPICAL CHARACTERISTICS
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.4
VDD = 3 V
VCO IN = 1/2 V
TA = –20°C to 75°C
0.3
C
°
0.2
Frequency – % /
0.1
– Temperature Coefficient of Oscillation
osc)
(f
α
0
2 2.5
DD
3 3.5
R
– Bias Resistor – kΩ
BIAS
3.3
Figure 14
4 4.5
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.4
VDD = 5 V
VCO IN = 1/2 V
TA = –20°C to 75°C
0.3
C
°
0.2
Frequency – % /
0.1
– Temperature Coefficient of Oscillation
osc)
(f
α
0
1.5
DD
2 2.5 3
2.2
R
– Bias Resistor – kΩ
BIAS
Figure 15
3.5
VCO OSCILLATION FREQUENCY
vs
VCO SUPPLY VOLTAGE
24
R
= 3.3 kΩ
BIAS
VCO IN = 1.5 V
TA = 25°C
22
20
18
– VCO Oscillation Frequency – MHz
osc
f
16
3.05 3
VDD – VCO Supply Voltage – V
Figure 16
3.15
VCO OSCILLATION FREQUENCY
vs
VCO SUPPLY VOLTAGE
48
R
= 2.2 kΩ
BIAS
VCO IN = 1/2 V
TA = 25°C
44
40
36
– VCO Oscillation Frequency – MHz
osc
f
32
4.75 5
DD
VDD – VCO Supply Voltage – V
Figure 17
5.25
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 13
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
0.05
VDD = 2.85 V to 3.15 V
VCO IN = 1/2 V
TA = 25°C
0.04
V
0.03
0.02
Frequency – % /
0.01
– Supply Voltage Coefficient of VCO Oscillation
0
osc)
(f
α
2 2.5 3.5 4
DD
3
R
– Bias Resistor – kΩ
BIAS
Figure 18
4.5
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
BIAS RESISTOR
VDD = 4.75 V to 5.25 V
VCO IN = 1/2 V
TA = 25°C
0.01
V
0.005
Frequency – % /
– Supply Voltage Coefficient of VCO Oscillation
osc)
(f
α
0
1.5 2.5 3
DD
2
R
– Bias Resistor – kΩ
BIAS
Figure 19
vs
3.5
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
BIAS RESISTOR
30
VDD = 2.85 V to 3.15 V
TA = –20°C to 75°C
25
20
15
Recommended Lock Frequency – MHz
10
2 2.5 3.5 4 4.5
3
R
– Bias Resistor – kΩ
BIAS
Figure 20
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
BIAS RESISTOR
60
VDD = 4.75 V to 5.25 V
TA = –20°C to 75°C
50
40
30
20
Recommended Lock Frequency – MHz
10
1.5 2 2.5
R
– Bias Resistor – kΩ
BIAS
Figure 21
3
3.5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
Page 14
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
BIAS RESISTOR
15
VDD = 2.85 V to 3.15 V
TA = –20°C to 75°C
SELECT = V
12.5
10
7.5
Recommended Lock Frequency – MHz
5
2 2.5 3.5 4 4.5
DD
3
R
– Bias Resistor – kΩ
BIAS
Figure 22
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
BIAS RESISTOR
30
VDD = 4.75 V to 5.25 V
TA = –20°C to 75°C
SELECT = V
25
20
15
10
Recommended Lock Frequency – MHz
5
1.5 2 2.5
DD
R
– Bias Resistor – kΩ
BIAS
Figure 23
3
3.5
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 15
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
countdown N value depends on the input
frequency and the desired VCO output frequency
according to the system application requirements.
The K
and KV values are obtained from the
p
operating characteristics of the device as shown
in Figure 24. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 24(b). KV is defined from
Figures 8, 9, 10, and 1 1 as shown in Figure 24(c).
The parameters for the block diagram with the
units are as follows:
KV : VCO gain (rad/s/V)
Kp : PFD gain (V/rad)
Kf : LPF gain (V/V)
K
: count down divider gain (1/N)
N
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
Divider
(KN = 1/N)
f REF
–2π 2π–π 0 π
Range of
Comparison
VOH – V
Kp =
4π
OL
PFD
(Kp)
TLC2932
V
OH
V
OL
LPF
(Kf)
(a)
f
MAX
f
MIN
KV =
VCO
(KV)
V
OH
VIN
VIN
MIN
2π(f
MAX
MAX
– f
– VIN
(c)(b)
Figure 24. Example of a PLL Block Diagram
VIN
MIN
MAX
)
MIN
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V
applied to the VCO IN terminal. However,
DD
for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply and a resistor value of 2.5
kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice
but a carbon-compositiion resistor can be used with excellent results also. A 0.22 µF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
Ǔǒ
Where
DwH]
0.8ǒK
p
Ǔǒ
K
Kf(R)
V
Kf (∞) = the filter transfer function value at ω = ∞
Ǔ
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
Page 16
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and should be
consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are shown
in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to FIN-B because
of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at the VCO
input. The value of C2 should be equal to or less than one tenth the value of C1.
C2
R2
–
A
T1 = C1R1
T2 = C1R2
C1
V
R1
I
T1 = C1R1
(a) LAG FILTER
C1
V
O
V
T1 = C1R1
T2 = C1R2
R1
I
R2
C1
(b) LAG-LEAD FILTER
C2
V
O
V
I
R1
(c) ACTIVE FILTER
V
O
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the lag-lead filter shown in Figure 25(b) is;
V
O
V
IN
+
1)s@T2
1)s
(
T1)T2
@
)
Where
T1+R1
C1 and T2+R2@C1
@
Using this filter makes the closed loop PLL system a second-order type 1 system. The response curves of this
system to a unit step are shown in Figure 26.
the active filter
When using the active integrator shown in Figure 25(c), the phase detector inputs must be reversed since the
integrator adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B
terminal and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 25(c) is:
F(s)
Using this filter makes the closed loop PLL system a second-order type 2 system. The response curves of this
system to a unit step are shown in Figure 27.
1)s@R2@C1
+
s
@R1@
C1
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 17
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
basic design example (continued)
Assume the loop has to have a 100 µs settling time (ts) with a countdown N = 8. Using the Type 1, second order
response curves of Figure 26, a value of 4.5 radians is selected for ωnts with a damping factor of 0.7. This
selection gives a good combination for settling time, accuracy , and loop gain margin. The initial parameters are
summarized in Table 5. The loop constants, K
Table 6 shows these values.
The natural loop frequency is calculated as follows:
Since
and Kp, are calculated from the data sheet specifications and
V
TLC2932
Then
wnts+
wn+
4.5
4.5
+
100ms
45 k-radiansńsec
Table 5. Design Parameters
PARAMETER SYMBOL VALUE UNITS
Division factor N 8
Lockup time t 100 µs
Radian value to selected lockup time ωnt 4.5 rad
Damping factor ζ 0.7
Table 6. Device Specifications
PARAMETER SYMBOL VALUE UNITS
VCO gain 76.6 Mrad/V/s
f
MAX
f
MIN
VIN
MAX
VIN
MIN
PFD gain K
K
V
p
70 MHz
20 MHz
0.9 V
0.342357 V/rad
5 V
Table 7. Calculated Values
PARAMETER SYMBOL VALUE UNITS
Natural angular frequency ω
K = (KV • Kp)/N 3.277 Mrad/sec
Lag-lead filter
Calculated value
Nearest standard value
Calculated value
Nearest standard value
Selected value C1 0.1 µF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
n
R1
R2
45000 rad/sec
15870
16000
308
300
Ω
Ω
17
Page 18
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
Using the low-pass filter in Figure 25(b) and divider ratio N, the transfer function for phase and frequency are
shown in equations 1 and 2. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider value N. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is
ȱ
K
K
@
N
@
p
(
T1)T2
F
2(s)
+
F
1(s)
and the transfer function for frequency is
ȧ
ȧ
V
ȧ
)
ȧ
s2)
sƪ1
Ȳ
1)s@T2
K
K
p
@
)
N@(T1)T2)
T2
@
V
ƫ
)
K
N
(T1)T2)
@
@
p
ȱ
F
OUT(s)
F
REF(s)
The standard two-pole denominator is D = s2 + 2 ζ ωn s + ω
of equation 1 and 2 with the standard two-pole denominator gives the following results.
wn+
Solving for T1 + T2
+
(
Ǹ
T1)T2
K
K
@
p
V
T1)T2
)
K
@
p
N@(T1)T2)
K
@
p
+
N@w
ȧ
ȧ
ȧ
ȧ
Ȳ
K
K
s2)
V
V
2
n
1)s@T2
K
K
T2
@
@
p
ƪ
s
1
)
@
V
N@(T1)T2)
ƫ
K
K
@
p
)
N
@
2
and comparing the coefficients of the denominator
n
V
(T1)T2)
ȳ
ȧ
ȧ
ȧ
K
ȧ
V
ȴ
ȳ
ȧ
ȧ
ȧ
ȧ
ȴ
(1)
(2)
(3)
and by using this value for T1 + T2 in equation 3 the damping factor is
w
n
z
+
solving for T2
T2
+
then by substituting for T2 in equation 3
T1
+
18
@
2
2
z
w
K
@
V
N@w
ǒ
T2
N
–
K
@
p
K
p
–
2
n
)
N
K
p
K
V
2
z
w
n
Ǔ
K
@
V
N
)
K
K
@
p
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 19
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
2
ȱ
ȧ
Ȳ
z
ƪ
w
n
K
@
p
2
w
n
R2
+
R1
+
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculated
values are listed in Table 7.
*
@
N
K
@
p
K
v
2
*
w
N
1
ƫ
K
C1
V
@
ȳ
N
1
ȧ
K
C1
V
ȴ
z
)
K
n
p
TLC2932
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
Page 20
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
1.9
1.8
= 0.1
z
1.7
1.6
1.5
1.4
1.3
1.2
1.1
= 0.6
z
= 0.7
z
= 0.8
z
= 0.2
z
= 0.3
z
= 0.4
z
= 0.5
z
1
0.9
= 1.0
z
0.8
(t), Normalized Responseφ
2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
012345678910111213
= 1.5
z
= 2.0
z
ωnts = 4.5
ω
nt
20
Figure 26. Type 1 Second-Order Step Response
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 21
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
1.9
1.8
1.7
1.6
1.5
1.4
1.3
ζ = 0.1
ζ = 0.2
ζ = 0.3
ζ = 0.4
ζ = 0.5
ζ = 0.6
ζ = 0.7
1.2
1.1
1
0.9
ζ = 0.8
0.8
ζ = 1.0
(t), Normalized Output Frequencyφ
0
0.7
ζ = 2.0
0.6
0.5
0.4
0.3
0.2
0.1
0
012345678910111213
ω
nt
Figure 27. Type 2 Second-Order Step Response
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
21
Page 22
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
APPLICATION INFORMATION
V
DD
1
LOGIC VDD (Digital)
SELECT
2
3
VCO OUT
REF IN
DGND
4
5
PFD OUT
6
FIN–A
FIN–B
Phase
Comparator
VCO
1/2 f
osc
VCO INHIBIT
PFD INHIBIT
VCO V
DD
BIAS
VCO IN
VCO GND
14
13
12
11
10
9
†
R1
0.22 µF
AGND
AV
DD
R3
R2C2
C1
7
LOGIC GND (Digital)
Divide
By
N
†
R
resistor
BIAS
DGND
DV
DD
8
NC
R4 R5 R6
S3
S4
S5
DGND
Figure 28. Evaluation and Operation Schematic
PCB layout considerations
The TLC2932 contains a high frequency analog oscillator; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2932 user:
D
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
D
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
22
D
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
D
LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
D
VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
D
The no-connection (NC) terminal on the package should be connected to GND.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 23
TLC2932
HIGH-PERFORMANCE PHASE-LOCKED LOOP
SLAS097E – SEPTEMBER 1994 – REVISED MA Y 1997
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,65
14
1
1,20 MAX
A
7
0,10 MIN
0,32
0,17
8
6,70
4,70
4,30
6,10
M
0,13
Seating Plane
0,10
0,15 NOM
Gage Plane
0,25
0°–8°
0,70
0,40
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
8
3,30
2,90
14
5,30
4,90
16
5,30
20
6,80
6,404,90
24
8,10
7,70
28
10,00
9,60
4040064/B 10/94
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
Page 24
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