Datasheet TLC1541IN, TLC1541IFN, TLC1541IDWR, TLC1541IDW, TLC1541CN Datasheet (Texas Instruments)

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Page 1

TLC1541

10-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10-Bit Resolution A/D Converter

Microprocessor Peripheral or Standalone Operation

On-Chip 12-Channel Analog Multiplexer

Built-In Self-Test Mode

Software-Controllable Sample-and-Hold Function

T otal Unadjusted Error...±1 LSB Max

Pinout and Control Signals Compatible With TLC540 and TLC549 Families of 8-Bit A/D Converters

CMOS Technology

PARAMETER VALUE

Channel Acquisition Sample Time Conversion Time (Max) Samples Per Second (Max) Power Dissipation (Max)

5.5 µs 21 µs

32 × 10

6 mW

description

The TLC1541 is a CMOS A/D converter built around a 10-bit switched-capacitor successiveapproximation A/D converter. The device is designed for serial interface to a microprocessor or peripheral using a 3-state output with up to four control inputs ( including independent SYSTEM CLOCK, I/O CLOCK, chip select [CS

], and ADDRESS INPUT ). A 2.1-MHz system clock for the TLC1541, with a design that includes simultaneous read/write operation, allows highspeed data transfers and sample rates up to 32 258 samples per second. In addition to the high-speed converter and versatile control logic, there is an on-chip, 12-channel analog multiplexer that can be used to sample any one of 11 inputs or an internal self-test voltage and a sample-andhold function that operates automatically.

AVAILABLE OPTIONS

PACKAGE

SMALL

OUTLINE

(DW)

PLASTIC CHIP

CARRIER

(FN)

PLASTIC

DIP

(N)

0°C to 70°C TLC1541CDW TLC1541CFN TLC1541CN

–40°C to 85°C TLC1541IDW TLC1541IFN TLC1541IN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

INPUT A0 INPUT A1 INPUT A2 INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8

GND

SYSTEM CLOCK I/O CLOCK ADDRESS INPUT DATA OUT CS REF+ REF– INPUT A10 INPUT A9

DW OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

4 5 6 7 8

18 17 16 15 14

I/O CLOCK ADDRESS INPUT DATA OUT CS REF+

INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7

FN PACKAGE

(TOP VIEW)

INPUT A2

INPUT A1

INPUT A0

INPUT A10

REF–

SYSTEM CLOCK

INPUT A8

GND

INPUT A9

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Page 2

TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The converters incorporated in the TLC1541 feature differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally switched-capacitor design allows low-error conversion in 21 µs over the full operating temperature range.

The TLC1541 is available in DW, FN, and N packages. The C-suffix versions are characterized for operation from 0°C to 70°C. The I-suffix versions are characterized for operation from –40°C to 85°C.

functional block diagram

12-Channel

Analog

Multiplexer

Sample and

Hold

10-Bit

Switched-Capacitors

Analog-to-Digital

Converter

Self-Test

Reference

Output

Data

10-to-1 Data

Selector and

Driver

Control Logic

and I/O

Counters

Input

Multiplexer

Input Address

REF+ REF–

DATA OUT

ANALOG

INPUTS

ADDRESS

INPUT

I/O CLOCK

SYSTEM

CLOCK

1 2 3 4 5 6 7 8 9 11 12

14 13

18 15 19

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

Ci = 60 pF TYP (equivalent input capacitance)

5 MΩ TYP

INPUT

A0–A10

INPUT

A0–A10

Page 3

TLC1541

10-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating sequence

MSB LSB

Don’t Care Don’t Care

MSB LSB

wH(CS)

conv

See Note A

See Note C

HI-Z

State

HI-Z State

Sample Cycle C

Access Cycle C

Sample Cycle B

Access Cycle B

Previous Conversion Data A

Conversion Data B

A9 B9

MSB LSB MSB MSB LSB MSB

(

see Note B

)

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

B3 B2 B1 B0 C3 C2 C1 C0

Don’t Care

1 2 3 4 56 78 9 10 1 2 3 4 56 78 9 10

I/O

CLOCK

ADDRESS

INPUT

DATA

OUT

NOTES: A. The conversion cycle, which requires 44 system clock periods, initiates on the tenth falling edge of the I/O clock after CS goes low

for the channel whose address exists in memory at that time. When CS

is kept low during conversion, the I/O clock must remain

low for at least 44 system clock cycles to allow the conversion to complete.

B. The most significant bit (MSB) is automatically placed on the DAT A OUT bus after CS

is brought low. The remaining nine bits (A8–A0)

clock out on the first nine I/O clock falling edges.

C. To minimize errors caused by noise at the CS

input, the internal circuitry waits for three system clock cycles (or less) after a chip-select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the minimum chip-select setup time elapses.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

(see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package 260°C. . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted).

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TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.75 5 5.5 V

Positive reference voltage, V

ref+

(see Note 2) 2.5 V

CCVCC

+0.1 V

Negative reference voltage, V

ref–

(see Note 2) –0.1 0 2.5 V

Differential reference voltage, V

ref+

– V

ref–

(see Note 2) 1 V

CCVCC

+0.2 V

Analog input voltage (see Note 2) 0 V

High-level control input voltage, V

2 V

Low-level control input voltage, V

0.8 V

Input/output clock frequency, f

clock(I/O)

0 1.1 MHz

System clock frequency, f

clock(SYS)

clock(I/O)

2.1 MHz

Setup time, address bits before I/O CLOCK↑, t

su(A)

400 ns

Hold time, address bits after I/O CLOCK↑, t

h(A)

0 ns

Setup time, CS low before clocking in first address bit, t

su(CS)

(see Note 3 and Operating Sequence)

System

clock

cycles

Pulse duration, CS high during conversion, t

wH(CS)

(see Operating Sequence) 44

System

clock

cycles

Pulse duration, SYSTEM CLOCK high, t

wH(SYS)

210 ns

Pulse duration, SYSTEM CLOCK low, t

wL(SYS)

190 ns

Pulse duration, I/O CLOCK high, t

wH(I/O)

404 ns

Pulse duration, I/O CLOCK low, t

wL(I/O)

404 ns

clock(SYS)

≤ 1048 kHz 30

System

clock(SYS)

> 1048 kHz 20

Clock transition time (see Note 4)

clock(I/O)

≤ 525 kHz 100

I/O

clock(I/O)

> 525 kHz 40

C suffix 0 70

O erating free-air tem erature, T

I suffix –40 85

°C

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

to REF– convert as all zeros (0000000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.

3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three system clock cycles (or less) after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum chip select setup time elapses.

4. The amount of time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

Page 5

TLC1541

10-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating temperature range, V

= V

ref+

= 4.75 V to 5.5 V, f

clock(I/O)

= 1.1 MHz, f

clock(SYS)

= 2.1 MHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

High-level output voltage (terminal 16) VCC = 4.75 V , IOH = 360 µA 2.4 V

Low-level output voltage VCC = 4.75 V , IOL = 3.2 mA 0.4 V

VO = VCC, CS at V

IOZHigh-impedance-state output current

VO = 0, CS at V

–10

High-level input current VI = V

0.005 2.5 µA

Low-level input current VI = 0 –0.005 –2.5 µA

Operating supply current CS at 0 V 1.2 2.5 mA

Selected channel at VCC, Unselected channel at 0 V

0.4 1

Selected channel leakage current

Selected channel at 0 V , Unselected channel at V

–0.4 –1

ICC + I

ref

Supply and reference current V

ref+

= VCC, CS at 0 V 1.3 3 mA

Analog inputs 7 55

CiInput capacitance

Control inputs 5 15

†

All typical values are at VCC = 5 V and TA = 25°C.

Page 6

TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating temperature range, V

= V

ref+

= 4.75 V to 5.5 V, f

clock(I/O)

= 1.1 MHz, f

clock(SYS)

= 2.1 MHz

PARAMETER TEST CONDITIONS MIN MAX UNIT

Linearity error See Note 5 ±1 LSB

Zero-scale error See Notes 2 and 6 ±1 LSB

Full-scale error See Notes 2 and 6 ±1 LSB

Total unadjusted error See Note 7 ±1 LSB Self-test output code Input A11 address = 1011 (see Note 8)

0111110100

(500)

1000001100

(524)

conv

Conversion time 21 µs Total access and conversion time 31 µs

Channel acquisition time (sample cycle) See Operating Sequence 6

I/O

clock

cycles

Time output data remains valid after I/O CLOCK↓

10 ns

Delay time, I/O CLOCK↓ to DATA OUT valid 400 ns

Output enable time 150 ns

dis

Output disable time

See Figure 1

150 ns

r(bus)

Data bus rise time 300 ns

f(bus)

Data bus fall time 300 ns

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference between 1111111111 and the converted output for full-scale input voltage.

7. Total unadjusted error includes linearity, zero-scale, and full-scale errors.

8. Both the input address and the output codes are expressed in positive logic. The A11 analog input signal is internally genera ted and used for test purposes.

Page 7

TLC1541

10-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

See Note B

0.4 V

2.4 V

f(bus)

Output

r(bus)

0.4 V

2.4 V

0.4 V

DATA OUT

VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES

VOLTAGE WAVEFORMS FOR DELAY TIME

3 kΩ

See Note B

SYSTEM

CLOCK

50%

0 V

PLZ

I/O CLOCK

VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES

Output Waveform 1

(see Note C)

PHZ

PZH

90%

10%

PZL

0 V

50%

LOAD CIRCUIT FOR

PZL

AND t

PLZ

LOAD CIRCUIT FOR

PZH

AND t

PHZ

LOAD CIRCUIT FOR

td, tr, AND t

See Note B

(see Note A)

Output

Under Test

Test Point

3 kΩ

1.4 V

Output Waveform 2

(see Note C)

(see Note A)

Output

Under Test

Test Point

(see Note A)

Output

Under Test

Test Point

NOTES: A. CL = 50 pF

B. ten = t

PZH

or t

PZL

and t

dis

= t

PHZ

or t

PLZ

C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

Figure 1. Load Circuits and Voltage Waveforms

Page 8

TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 2, the time required to charge the analog input capacitance from 0 V to V

within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

= VS 1–e

–t

c/RtCi

( )

(1)

where

= Rs + r

The final voltage to 1/2 LSB is given by

(2)V

(1/2 LSB) = VS – (VS/2048)

Equating equation 1 to equation 2 and solving for time (t

) gives

–(VS/2048) = V

1–e

( )

(3)

–t

c/RtCi

and

(1/2 LSB) = Rt × Ci × ln(2048) (4)

Therefore, with the values given, the time for the analog input signal to settle is

(5)

(1/2 LSB) = (Rs + 1 kΩ) × 55 pF × ln(2048)

This time must be less than the converter sample time shown in the timing diagrams.

VI= Input Voltage at INPUT A0–A10 VS= External Driving Source Voltage Rs= Source Resistance ri= Input Resistance Ci= Input Capacitance

†

Driving source requirements:

• Noise and distortion levels for the source must be at least equivalent to the resolution of the converter.

• Rs must be real at the input frequency.

55 pF MAX

1 kΩ MAX

Driving Source

†

TLC1541

Figure 2. Equivalent Input Circuit Including the Driving Source

Page 9

TLC1541

10-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The TLC1541 is a complete data acquisition system on a single chip. The device includes such functions as sample and hold, 10-bit A/D converter, data and control registers, and control logic. For flexibility and access speed, there are four control inputs: chip select (CS

), address input, I/O clock, and system clock. These control inputs and a TTL-compatible, 3-state output are intended for serial communications with a microprocessor or microcomputer. The TLC1541 can complete conversions in a maximum of 21 µs, while complete input-conversion output cycles can be repeated at a maximum of 31 µs.

The system and I/O clocks are normally used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device. Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and software need only be concerned with addressing the desired analog channel, reading the previous conversion result, and starting the conversion by using I/O CLOCK. SYSTEM CLOCK drives the conversion-crunching circuitry so that the control hardware and software need not be concerned with this task.

When CS

is high, DA TA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature

allows each of these terminals, with the exception of the CS

terminal, to share a control logic point with its counterpart terminals on additional A/D devices when using additional TLC1541 devices. In this way , the above feature serves to minimize the required control logic terminals when using multiple A/D devices.

The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is:

1. CS

is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two

rising edges and then a falling edge of SYSTEM CLOCK after a low CS

transition before recognizing the low transition. This technique protects the device against noise when the device is used in a noisy environment. The MSB of the previous conversion result automatically appears on DATA OUT.

2. A new positive-logic multiplexer address shifts in on the first four rising edges of I/O CLOCK. The MSB of the address shifts in first. The negative edges of these four I/O clock pulses shift out the second, third, fourth, and fifth most-significant bits of the previous conversion result. The on-chip sample-and-hold begins sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage.

3. Five clock cycles are then applied to the I/O CLOCK, and the sixth, seventh, eighth, ninth, and tenth conversion bits shift out on the negative edges of these clock cycles.

4. The final tenth-clock cycle is applied to the I/O CLOCK. The falling edge of this clock cycle completes the analog sampling process and initiates the hold function. Conversion is then performed during the next 44 system clock cycles. After this final I/O clock cycle, CS

must go high or the I/O CLOCK must remain low

for at least 44 system-clock cycles to allow for the conversion function.

can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. When glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, when CS

goes high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion in progress.

A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 44 system-clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion.

Page 10

TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

It is possible to connect SYSTEM CLOCK and I/O CLOCK together in special situations in which controlling-circuitry points must be minimized. In this case, the following special points must be considered in addition to the requirements of the normal control sequence previously described.

1. This device requires the first two clocks to recognize that CS

is at a valid low level when the common clock

signal is used as an I/O CLOCK. When CS

is recognized by the device to be at a high level, the common clock

signal is used for the conversion clock also.

2. A low CS

must be recognized before the I/O CLOCK can shift in an analog channel address. The device

recognizes a CS

transition when the SYSTEM CLOCK terminal receives two positive edges and then a

negative edge. For this reason, after a CS

negative edge, the first two clock cycles do not shift in the address.

Also, upon shifting in the address, CS

must be raised after the tenth valid (12 total) I/O CLOCK. Otherwise,

additional common-clock cycles are recognized as I/O CLOCK cycles and shift in an erroneous address.

For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time. This device accommodates these applications. Although the on-chip sample-and-hold begins sampling upon the negative edge of the fourth valid I/O CLOCK cycle, the hold function does not initiate until the negative edge of the tenth valid I/O CLOCK cycle. Thus, the control circuitry can leave the I/O CLOCK signal in its high state during the tenth valid I/O CLOCK cycle until the moment at which the analog signal must be converted. The TLC1541 continues sampling the analog input until the eighth valid falling edge of the I/O CLOCK. The control circuitry or software then immediately lowers the I/O CLOCK signal and holds the analog signal at the desired point in time and starts the conversion.

Page 11

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet TLC1541IN, TLC1541IFN, TLC1541IDWR, TLC1541IDW, TLC1541CN Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual