Datasheet TL16C550AN, TL16C550AFN, TL16C550AFNR Datasheet (Texas Instruments)

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Capable of Running With All Existing
TL16C450 Software

D

After Reset, All Registers Are Identical to
the TL16C450 Register Set

D

In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU

D

In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise

Synchronization Between the CPU and
Serial Data

D

Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2

16

–1) and Generates an Internal 16×

Clock

D

Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream

D

Independent Receiver Clock Input

D

Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled

D

Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation

and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)

D

False-Start Bit Detection

D

Complete Status Reporting Capabilities

D

3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus

D

Line Break Generation and Detection

D

Internal Diagnostic Capabilities:
– Loopback Controls for Communications

Link Fault Isolation
– Break, Parity , Overrun, Framing Error

Simulation

D

Fully Prioritized Interrupt System Controls

D

Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)

D

Faster Plug-In Replacement for National
Semiconductor NS16550A

description

The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
Functionally identical to the TL16C450 on power up (character mode

†

), the TL16C550A can be placed in an

alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver

FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency , all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.

The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.

The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (2

16

–1) and producing a 16× clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.

†

The TL16C550A can also be reset to the TL16C450 mode under software control.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1996, Texas Instruments Incorporated

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D0
D1
D2
D3
D4
D5
D6
D7

RCLK

SIN

SOUT

CS0
CS1
CS2

BAUDOUT

XIN

XOUT

WR1
WR2

V

SS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

V

CC

RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
ADS
TXRDY
DDIS
RD2
RD1

N PACKAGE

(TOP VIEW)

MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
A0
A1
AS

39
38
37
36
35
34
33
32
31
30
29

1819

7
8
9
10
11
12
13
14
15
16
17

D5
D6
D7

RCLK

SIN

NC

SOUT

CS0
CS1
CS2

BAUDOUT

20 21 22 23

FN PACKAGE

(TOP VIEW)

RI

DCD

DSR

CTS

54 321644

D4D3D2D1D0NCV

RD2

DDIS

TXRDY

ADS

XIN

XOUT

WR1

WR2

NC

RD1

42 41 4043

24 25 26 27 28

NC–No internal connection

CC

V

SS

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

block diagram

Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding

Register

Modem

Control

Register

Modem

Status

Register

Receiver

Buffer

Register

Line

Control

Register

Receiver

Timing and

Control

Line

Control

Register

Transmitter

FIFO

S
e

l
e
c

t

Line

Control

Register

Modem
Control

Logic

Interrupt

Enable

Register

Interrupt

I/O

Register

FIFO

Control

Register

Select

and

Control

Logic

Power
Supply

Interrupt

Control

Logic

S
e

l
e
c

t

Line

Control

Register

BAUDOUT

SIN

RCLK

SOUT

RTS
CTS
DTR
DSR
DCD
RI
OUT1
OUT2

INTRPT

32
36
33
37
38
39
34
31

30

11

9

10

15

CS0
CS1
CS2

ADS

MR
RD1
RD2

WR1

12
13
14
25
35
21
22
18

WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

19
23
24
16
17
29

A0
A1
A2

28
27
26

D7–D0

8–1

Internal

Data Bus

V

CC

V

SS

40
20

NOTE A: Terminal numbers shown are for the N package.

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

†

I/O

DESCRIPTION

A0
A1
A2

28 [31]
27 [30]
26 [29]

I Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from

or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS

) signal description.

ADS

25 [28] I

Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0,
CS1, CS2

) drive the internal select logic directly; when high, the register select and chip select signals are held in

the state they were in when the low-to-high transition of ADS

occurred.

BAUDOUT

15 [17] O

Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established by
the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output to the RCLK input.

CS0
CS1
CS2

12 [14]
13 [15]
14 [16]

I

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are
inactive, the ACE remains inactive. Refer to the ADS

(address strobe) signal description.

CTS

36 [40] I

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS

changes state, an

interrupt is generated.

D0 – D7 1 – 8

[2 – 9]

I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the

ACE and the CPU.

DCD

38 [42] I

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD

changes

state, an interrupt is generated.

DDIS 23 [26] O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable

an external transceiver.

DSR

37 [41] I

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR

changes state,

an interrupt is generated.

DTR

33 [37] O

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR

is placed in the active state by setting the DTR bit of the modem control register to a high level.

DTR

is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing

bit 0 (DTR) of the modem control register.

INTRPT 30 [33] O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode
only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset
(deactivated) either when the interrupt is serviced or as a result of a master reset.

MR 35 [39] I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer

to Table 2.

OUT1
OUT2

34 [38]
31 [35]

O

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting
their respective modem control register bits (OUT1 and OUT2) high. OUT1

and OUT2 are set to their inactive (high)
states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
modem control register.

RCLK 9 [10] I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
RD1

RD2

21 [24]
22 [25]

I

Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is
allowed to read status information or data from a selected ACE register. Only one of these inputs is required for
the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low
or RD1

tied high).

†

Terminal numbers shown in brackets are for the FN package.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

5

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Terminal Functions (continued)

TERMINAL

NAME NO.

†

I/O

DESCRIPTION

RI

39 [43] I Ring indicator . RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status

register. Bit 2 (TERI) of the modem status register indicates that the RI

input has transitioned from a low to a high
state since the last read from the modem status register. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.

RTS

32 [36] O

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register .

RXRDY

29 [32] O

Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY . When operating
in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450
mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between
CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least 1 character
in the receiver FIFO or receiver holding register, RXRDY

is active (low). When RXRDY has been active but there

are no characters in the FIFO or holding register, RXRDY

goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3

= 1), when the trigger level or the timeout has been reached, RXRDY

goes active (low); when it has been active

but there are no more characters in the FIFO or holding register, it goes inactive (high).

SIN 10 [11] I Serial input. SIN is a serial data input from a connected communications device.
SOUT 11 [13] O Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the

marking (high) state as a result of master reset.

TXRDY

24 [27] O

Transmitter ready output. T ransmitter DMA signalling is available with TXRDY . When operating in the FIFO mode,
one of two types of DMA signalling can be selected with FCR3. When operating in the TL16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles.
Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has
been filled.

V

CC

40 [44] 5-V supply voltage

V

SS

20 [22] Supply common

WR1
WR2

18 [20]
19 [21]

I

Write inputs. When either WR1 or WR2 are active (high or low respectively) while the ACE is selected, the CPU
is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer
data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1

tied high).

XIN
XOUT

16 [18]
17 [19]

I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

†

Terminal numbers shown in brackets are for the FN package.

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

I

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

C

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package 260°C. . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

High-level input voltage, V

IH

2 V

CC

V

Low-level input voltage, V

IL

–0.5 0.8 V

Operating free-air temperature, T

A

0 70 °C

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

OH

‡

High-level output voltage IOH = –1 mA 2.4 V

V

OL

‡

Low-level output voltage IOL = 1.6 mA 0.4 V

p

VCC = 5.25 V , VSS = 0,

I

lk

g

In ut leakage current

CC

VI = 0 to 5.25 V,

SS

All other terminals floating

±10

µA

p

p

V

CC

= 5.25 V,

V

SS

=

0

IOZHigh-im edance out ut current

V

O

= 0 to 5.25 V,

±20

µA

Chi

p selected in write mode or chip deselecte

d

°

V

CC

= 5.25 V,

T

A

=

25 C

,

pp

SIN, DSR, DCD, CTS

, and RI at 2 V,

ICCSu ly current

,,,, ,

p

10

mA

All other in uts at 0.8 V,XTAL1 at 4 MHz

,

No load

on outputs,

Baud

rate = 50

kbit/

s

C

XIN

Clock input capacitance

15 20 pF

C

XOUT

Clock output capacitance

VCC = 0, VSS = 0,

20 30 pF

C

i

Input capacitance

All other terminals grounded

,

f = 1 MHz

,

T

= 25°

C

6 10 pF

C

o

Output capacitance

f = 1 MHz

,

T

A

=

25 C

10 20 pF

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

These parameters apply for all outputs except XOUT.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature

ALT. SYMBOL FIGURE MIN MAX UNIT

t

cR

Cycle time, read (tw7 + td8 + td9) RC 175 ns

t

cW

Cycle time, write (tw6 + td5 + td6) WC 175 ns

t

w5

Pulse duration, ADS low

t

ADS

2, 3 15 ns

t

w6

Pulse duration, write strobe t

WR

2 80 ns

t

w7

Pulse duration, read strobe tRD 3 80 ns

t

w8

Pulse duration, master reset t

MR

1 µs

t

su1

Setup time, address valid before ADS↑ t

AS

2, 3 15 ns

t

su2

Setup time, CS before ADS↑ t

CS

2, 3 15 ns

t

su3

Setup time, data valid before WR1↓ or WR2↑ t

DS

2 15 ns

t

h1

Hold time, address low after ADS↑ t

AH

2, 3 0 ns

t

h2

Hold time, CS valid after ADS↑ t

CH

2, 3 0 ns

t

h3

Hold time, CS valid after WR1↑ or WR2↓ t

WCS

2 20 ns

t

h4

§

Hold time, address valid after WR1↑ or WR2↓ t

WA

2 20 ns

t

h5

Hold time, data valid after WR1↑ or WR2↓ t

DH

2 15 ns

t

h6

Hold time, CS valid after RD1↑orRD2↓

t

RCS

3 20 ns

t

h7

§

Hold time, address valid after RD1↑ or RD2↓ t

RA

3 20 ns

t

d4

§

Delay time, CS valid before WR1↓ or WR2↑ t

CSW

2 15 ns

t

d5

§

Delay time, address valid before WR1↓ or WR2↑ t

AW

2 15 ns

t

d6

§

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

WC

2 80 ns

t

d7

§

Delay time, CS valid to RD1↓

or RD2

↑

t

CSR

3 15 ns

t

d8

§

Delay time, address valid to RD1↓ or RD2↑ t

AR

3 15 ns

t

d9

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 3 80 ns

§

Applicable only when ADS is tied low.

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t

w1

Pulse duration, clock high t

XH

1 f = 9 MHz maximum 50 ns

t

w2

Pulse duration, clock low t

XL

1 f = 9 MHz maximum 50 ns

t

d10

Delay time, RD1↓ or RD2↑ to data valid t

RVD

3 CL = 100 pF 60 ns

t

d11

Delay time, RD1↑ or RD2↓ to floating data t

HZ

3 CL = 100 pF 0 60 ns

t

dis(R)

Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ t

RDD

3 CL = 100 pF 60 ns

NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t

w3

Pulse duration, BAUDOUT low t

LW

1

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

80 ns

t

w4

Pulse duration, BAUDOUT high t

HW

1

f = 9 MHz, CLK ÷ 2,

CL = 100 pF

100 ns

t

d1

Delay time, XIN↑ to BAUDOUT↑ t

BLD

1 CL = 100 pF 125 ns

t

d2

Delay time, XIN↑↓ to BAUDOUT↓ t

BHD

1 CL = 100 pF 125 ns

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t

d12

Delay time, RCLK to sample clock t

SCD

4 100 ns

t

d13

Delay time, stop to set RCV error interrupt or
read RBR to LSI interrupt or stop to
RXRDY

↓

t

SINT

4,5,6,7,8 1

RCLK
cycles

t

d14

Delay time, read RBR/LSR to reset interrupt t

RINT

4,5,6,7,8 CL = 100 pF 150 ns

NOTE 3: In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identification register or

line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t

d15

Delay time, INTRPT to transmit start t

IRS

9 8 24

baudout

cycles

t

d16

Delay time, start to interrupt t

STI

9 8 8

baudout

cycles

t

d17

Delay time, WR THR to reset interrupt t

HR

9 CL = 100 pF 140 ns

t

d18

Delay time, initial write to interrupt (THRE) t

SI

9 16 32

baudout

cycles

t

d19

Delay time, read IIR to reset interrupt (THRE) t

IR

9 CL = 100 pF 140 ns

t

d20

Delay time, write to TXRDY inactive t

WXI

10,11 CL = 100 pF 195 ns

t

d21

Delay time, start to TXRDY active t

SXA

10,11 CL = 100 pF 8

baudout

cycles

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t

d22

Delay time, WR MCR to output t

MDO

12 CL = 100 pF 100 ns

t

d23

Delay time, modem interrupt to set interrupt t

SIM

12 CL = 100 pF 170 ns

t

d24

Delay time, RD MSR to reset interrupt t

RIM

12 CL = 100 pF 140 ns

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

XIN or RCLK

(9 MHz Max)

BAUDOUT

(1/1)

XIN

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N > 3)

2 XIN Cycles

(N-2) XIN Cycles

t

w3

t

w4

t

d1

t

d2

t

d1

t

d2

N

t

w2

t

w1

2.4 V

0.4 V

0.8 V

2 V

Figure 1. Baud Generator Timing Waveforms

TL16C550A
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PARAMETER MEASUREMENT INFORMATION

ADS

t

w5

t

h1

t

su1

t

h2

t

su2

t

su3

t

h5

t

h3

t

w6

t

d4

†

t

d5

†

t

d6

†

t

h4

†

Valid Data

Valid Valid

†

Valid Valid

†

Active

A0–A2

CS0, CS1, CS2

WR1, WR2

D7–D0

50%50%

50%

50%50%

50% 50%

50% 50%

50%

†

Applicable only when ADS is tied low.

Figure 2. Write Cycle Timing Waveforms

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PARAMETER MEASUREMENT INFORMATION

ADS

t

w5

t

h1

t

su1

t

h2

t

su2

t

d10

t

d11

t

h6

t

w7

t

d7

†

td8†

t

d9

t

h7

†

Valid Data

Valid Valid

†

Valid Valid

†

Active

A0–A2

CS0, CS1, CS2

RD1, RD2

D7–D0

t

dis(R)

t

dis(R)

DDIS

50%50%

50%

50%

50%

50% 50%

50% 50%

50%

50%

50% 50%

†

Applicable only when ADS is tied low.

Figure 3. Read Cycle Timing Waveforms

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PARAMETER MEASUREMENT INFORMATION

t

d13

Active

Active

RD1

, RD2

(read RBR)

RCLK

t

d14

8 Clocks

t

d12

Parity StopStart Data Bits 5–8

Sample Clock

TL16C450 Mode:

Sample Clock

SIN

INTRPT

(data ready)

INTRPT

(RCV error)

RD1

, RD2

(read LSR)

50%50%

50%

50%

50%

50%

t

d14

Figure 4. Receiver Timing Waveforms

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

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PARAMETER MEASUREMENT INFORMATION

t

d13

(see Note A)

t

d14

Stop

Data Bits 5-8

Sample Clock

SIN

Trigger-Level

Interrupt

(FCR6, 7 = 0, 0)

LSI Interrupt

t

d14

RD1

(RD LSR)

RD1

(RD RBR)

Active

Active

(FIFO at or Above
Trigger Level)

(FIFO Below
Trigger Level)

NOTE A: For a timeout interrupt, t

d13

= 8 RCLKs.

Figure 5. Receiver FIFO First Byte (Sets DR Bit) Waveforms

t

d13

(see Note A)

t

d14

Stop

Top Byte of FIFO

Sample Clock

SIN

Time Out or

Trigger Level

Interrupt

LSI Interrupt

t

d13

(FIFO at or Above
Trigger Level)

(FIFO Below
Trigger Level)

RD1, RD2

(RDLSR)

RD1, RD2

(RDRBR)

Active Active

t

d14

Previous Byte

Read From FIFO

NOTE A: For a timeout interrupt, t

d13

= 8 RCLKs.

Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

TL16C550A
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PARAMETER MEASUREMENT INFORMATION

t

d13

(see Note B)

t

d14

Sample Clock

SIN

(first byte)

Active

RD

(RD RBR)

RXRDY

See Note A

Stop

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a timeout interrupt, t

d13

= 8 RCLKs.

Figure 7. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (mode 0)

t

d13

(see Note B)

t

d14

Sample Clock

SIN

(first byte that reaches

the trigger level)

Active

RD

(RD RBR)

RXRDY

See Note A

NOTES: A. This is the reading of the last byte in the FIFO.

B. For a timeout interrupt, t

d13

= 8 RCLKs.

Figure 8. Receiver Ready (RXRDY) Waveforms, FCR = 1 or FCR3 = 1 (mode 1)

TL16C550A

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PARAMETER MEASUREMENT INFORMATION

t

d16

Parity Stop

Start

Data Bits

SOUT

Start

t

d15

t

d17

t

d17

t

d18

t

d19

INTRPT

(THRE)

WR THR

RD IIR

50% 50% 50% 50% 50%

50%

50%

50%

50%

50%

50%

Figure 9. Transmitter Timing Waveforms

t

d20

WR

(WR THR)

t

d21

Parity

Stop

Data

Start

Byte #1

SOUT

TXRDY

Figure 10. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (mode 0)

t

d20

WR

(WR THR)

t

d21

Parity

Stop

Data

Start

Byte #16

SOUT

TXRDY

FIFO Full

Figure 11. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (mode 1)

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PARAMETER MEASUREMENT INFORMATION

t

d22

t

d22

WR

(WR MCR)

RTS, DTR,

OUT1

, OUT2

CTS, DSR, DCD

t

d23

t

d24

t

d23

INTRPT

(modem)

RD2

(RD MSR)

RI

50% 50%

50% 50%

50%

50%

50%

50%

50%

50%

Figure 12. Modem Control Timing Waveforms

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

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APPLICATION INFORMATION

D7–D0

MEMR

or I/OR

MEMW or I/ON

INTR

RESET

A0
A1
A2

CS

L

H

EIA

232-D Drivers

and Receivers

XOUT

XIN

RCLK

BAUDOUT

RI

CTS

DCD

DSR

DTR

RTS

SOUT

SIN

INTRPT

D7–D0

RD1
WR1

MR
A0

A1
A2

ADS
WR2
RD2

CS2
CS1
CS0

TL16C550A

(ACE)

3.072 MHz

C
P
U

B
u

s

Figure 13. Basic TL16C550A Configuration

Receiver Disable

Microcomputer

System

Data Bus Data Bus

Driver Disable

8-Bit

Bus Transceiver

WR

WR1

D7–D0

DDIS

TL16C550A

(ACE)

Figure 14. Typical Interface for a High-Capacity Data Bus

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APPLICATION INFORMATION

Buffer

Address
Decoder

A16–A23

ADS

AD0–AD15

RSI/ABT

PHI1 PHI2

PHI1 PHI2

ADS

ADS

CPU

RSTO

A16–A23

CS0
CS1
CS2

MR

A0–A2

D0–D2

AD0–AD7

RD1

WR1

AD0–AD15

RD2
WR2

XIN

XOUT

BAUDOUT

RCLK

DTR

RTS

OUT1
OUT2

RI
DCD
DSR

CTS

SIN

SOUT

INTRPT

TXRDY

DDIS

RXRDY

GND

(V

SS)

5 V

(V

CC)

20 40

Alternate

XTAL Control

TL16C550A

†

EIA-232-D

Connector

20

1

8
6
5

2

3

7
1

16

17
15
9

33
32
34
31

39
38
37
36

10
30
24
23

11

2919

22

18

21

25

35

12
13
14

TCU

RD

WR

†

Terminal numbers for the TL16C550A are for the N package.

Figure 15. Typical TL16C550A Connection to a CPU

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PRINCIPLES OF OPERATION

Table 1. Register Selection

DLAB

†

A2 A1 A0 REGISTER

0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H L FIFO control register (write)
X L H H Line control register
X H L L Modem control register
X H L H Line status register
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)

†

The divisor latch access bit (DLAB) is the most significant bit of the line control register . The DLAB signal
is controlled by writing to this bit location (see Table 3).

Table 2. ACE Reset Functions

REGISTER/SIGNAL

RESET

CONTROL

RESET STATE

Interrupt Enable Register Master Reset All bits cleared (0–3 forced and 4–7 permanent)
Interrupt Identification Register Master Reset

Bit 0 is set, bits 1–3 are cleared, and bits 4–7 are permanently

cleared
FIFO Control Register Master Reset All bits cleared
Line Control Register Master Reset All bits cleared
Modem Control Register Master Reset All bits cleared (5–7 permanent)
Line Status Register Master Reset Bits 5 and 6 are set, all other bits are cleared
Modem Status Register Master Reset Bits 0–3 are cleared, bits 4–7 are input signals
SOUT Master Reset High
INTRPT (receiver error flag) Read LSR/MR Low
INTRPT (received data available) Read RBR/MR Low

INTRPT (transmitter holding register empty)

Read IR/Write

THR/MR

Low
INTRPT (modem status changes) Read MSR/MR Low

OUT2

Master Reset High

RTS

Master Reset High

DTR

Master Reset High

OUT1

Master Reset High
Scratch Register Master Reset No effect
Divisor Latch (LSB and MSB) Registers Master Reset No effect
Receiver Buffer Registers Master Reset No effect
Transmitter Holding Registers Master Reset No effect

RCVR FIFO

MR/FCR1-FCR0/

∆FCR0

All bits low

XMIT FIFO

MR/FCR2-FCR0/

∆FCR0

All bits low

Bit
No.

TL16C550A
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PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.

T able 3. Summary of Accessible Registers

REGISTER ADDRESS

0DLAB=0 0 DLAB =0 1DLAB = 0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1

Receiver

Buffer

Register

(Read
Only)

Transmitter

Holding
Register

(Write

Only)

Interrupt

Enable

Register

Interrupt

Ident.

Register

(Read
Only)

FIFO

Control

Register

(Write

Only)

Line

Control

Register

Modem
Control

Register

Line

Status

Register

Modem

Status

Register

Scratch
Register

Divisor

Latch
(LSB)

Latch
(MSB)

RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM

0 Data Bit 0†Data Bit 0

Enable

Received

Data

Available

Interrupt

(ERB)

”0“ If
Interrupt
Pending

FIFO

Enable

Word

Length

Select

Bit 0

(WLS0)

Data

Terminal

Ready
(DTR)

Data

Ready

(DR)

Delta

Clear

to Send
(

∆CTS)

Bit 0 Bit 0 Bit 8

1 Data Bit 1 Data Bit 1

Enable

Transmitter

Holding

Register

Empty
Interrupt
(ETBEI)

Interrupt

ID

Bit 0

Receiver

FIFO

Reset

Word

Length

Select

Bit 1

(WLS1)

Request

to Send

(RTS)

Overrun

Error
(OE)

Delta

Data

Set

Ready

(

∆DSR)

Bit 1 Bit 1 Bit 9

2 Data Bit 2 Data Bit 2

Enable

Receiver

Line Status

Interrupt

(ELSI)

Interrupt

ID

Bit (1)

Transmitter

FIFO

Reset

Number

of

Stop Bits

(STB)

Out1

Parity

Error
(PE)

Trailing

Edge Ring

Indicator

(TERI)

Bit 2 Bit 2 Bit 10

3 Data Bit 3 Data Bit 3

Enable

Modem

Status
Interrupt
(EDSSI)

Interrupt

ID

Bit (2)

(Note 4)

DMA

Mode

Select

Parity

Enable

(PEN)

Out2

Framing

Error
(FE)

Delta

Data
Carrier
Detect

(

∆DCD)

Bit 3 Bit 3 Bit 11

4 Data Bit 4 Data Bit 4 0 0 Reserved

Even

Parity

Select

(EPS)

Loop

Break

Interrupt

(BI)

Clear

to

Send

(CTS)

Bit 4 Bit 4 Bit 12

5 Data Bit 5 Data Bit 5 0 0 Reserved

Stick

Parity

0

Transmitter

Holding

Register

(THRE)

Data

Set

Ready

(DSR)

Bit 5 Bit 5 Bit 13

6 Data Bit 6 Data Bit 6 0

FIFOs
Enabled
(Note 4)

Receiver

Trigger

(LSB)

Set

Break

0

Transmitter

Empty

(TEMT)

Ring

Indicator

(RI)

Bit 6 Bit 6 Bit 14

7 Data Bit 7 Data Bit 7 0

FIFOs
Enabled
(Note 4)

Receiver

Trigger

(MSB)

Divisor

Latch

Access

Bit

(DLAB)

0

Error in

RCVR

FIFO

(Note 4)

Data
Carrier
Detect

(DCD)

Bit 7 Bit 7 Bit 15

†

Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

NOTE 4: These bits are always cleared in the TL16C450 mode.

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PRINCIPLES OF OPERATION

FIFO control register (FCR)

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.

D

Bit 0: This bit (FCR0), when set, enables the transmit and receive FIFOs. Bit 0 must be set when other FCR
bits are written to or they are not programmed. Changing this bit clears the FIFOs.

D

Bit 1: This bit (FCR1), when set, clears all bytes in the receiver FIFO and clears its counter . The shift register
is not cleared. The 1 that is written to this bit position is self clearing.

D

Bit 2: This bit (FCR2), when set, clears all bytes in the transmit FIFO and clears its counter . The shift register
is not cleared. The 1 that is written to this bit position is self clearing.

D

Bit 3: When this bit (FCR0) and FCR3 are set, RXRDY and TXRDY change from mode 0 to mode 1.

D

Bits 4 and 5: These two bits (FCR4 and FCR5) are reserved for future use.

D

Bits 6 and 7: These two bits (FCR6 and FCR7) set the trigger level for the receiver FIFO interrupt.
Table 4 shows the trigger level for the receiver FIFO interrupt.

Table 4. Receiver FIFO Trigger Level

BIT 7 BIT 6

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

0 0 01
0 104
1008
1114

FIFO interrupt mode operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1) receiver interrupts occur as
follows:

1. The receive data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared as soon as the FIFO drops below its programmed trigger level.

2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and, like the
interrupt, it is cleared when the FIFO drops below the trigger level.

3. The receiver line status interrupt (IIR = 06), as before, has higher priority than the received data
available (IIR = 04) interrupt.

4. The data ready bit (LSR0) is set as soon as a character is transferred from the shift register to the
receiver FIFO. It is cleared when the FIFO is empty.

When the receiver FIFO and receiver interrupts are enabled, receiver FIFO timeout interrupts occur as follows:

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT

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PRINCIPLES OF OPERATION

FIFO interrupt mode operation (continued)

1. FIFO timeout interrupt occurs when the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character received was longer than 4 continuous character times ago (when

2 stop bits are programmed, the second one is included in this time delay).

c. The most recent microprocessor read of the FIFO was longer than 4 continuous character times

ago. This causes a maximum character received to interrupt issued delay of 160 ms at 300 baud
with 12-bit characters.

2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay
proportional to the baud rate).

3. When a timeout interrupt has occurred, it is cleared and the timer reset when the microprocessor reads
one character from the receiver FIFO.

4. When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.

When the transmit FIFO and transmitter interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur
as follows:

1. The THR interrupt (02) occurs when the transmit FIFO is empty. It is cleared as soon as the THR is
written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR
is read.

2. The transmit FIFO empty indications are delayed 1 character time minus the last stop bit time when the
following occurs: THRE = 1 and there have not been at least two bytes at the same time in the transmit
FIFO since the last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, if it is
enabled.

Character timeout interrupt and receiver FIFO trigger level interrupts have the same priority as the current
received data available interrupt. The transmit FIFO empty interrupt has the same priority as the current THRE
interrupt.

FIFO polled mode operation

When FCR0 is set, clearing IER0, IER1, IER2, IER3, or all four puts the ACE in the FIFO polled mode of
operation. Since the receiver and transmitter are controlled separately , either one or both can be in the polled
mode of operation.

In this mode, the user program checks the receiver and transmitter status using the LSR.

D

LSR0 is set as long as there is one byte in the receiver FIFO.

D

LSR1 – LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode and the IIR is not affected since IER2 = 0.

D

LSR5 indicates when the transmit FIFO is empty.

D

LSR6 indicates that both the transmit FIFO and shift registers are empty.

D

LSR7 indicates whether there are any errors in the receiver FIFO.

There is no trigger level reached or timeout conditions indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

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PRINCIPLES OF OPERATION

interrupt enable register (IER)

The IER enables each of the four types of interrupts (refer to T able 5) and the INTRPT output signal in response
to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The
contents of this register are summarized in Table3 and are described in the following bulleted list.

D

Bit 0: This bit, when set, enables the received data available interrupt.

D

Bit 1: This bit, when set, enables the THRE interrupt.

D

Bit 2: This bit, when set, enables the receiver line status interrupt.

D

Bit 3: This bit, when set, enables the modem status interrupt.

D

Bits 4 – 7: These bits in the IER are not used and are always cleared.

interrupt identification register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.

The ACE provides four prioritized levels of interrupts:

D

Priority 1– Receiver line status (highest priority)

D

Priority 2– Receiver data ready or receiver character time out

D

Priority 3–Transmitter holding register empty

D

Priority 4–Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt is defined
by the interrupt’s three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in
Table 3 and described in Table 4. Details of each bit are as follows:

D

Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.

D

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 5.

D

Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a timeout interrupt is pending.

D

Bits 4 thru 5: These two bits are not used and are always cleared.

D

Bits 6 and 7: These two bits are always cleared in the TL16C450 mode. They are set when bit 0 of the FCR
is set.

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT

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PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

Table 5. Interrupt Control Functions

INTERRUPT

IDENTIFICATION

REGISTER (IIR)

PRIORITY

LEVEL

INTERRUPT TYPE INTERRUPT SOURCE

INTERRUPT RESET

METHOD

BIT 3 BIT 2 BIT 1 BIT 0

0 0 0 1 None None None –
0 1 1 0 1 Receiver line status

Overrun error, parity error,
framing error, or break interrupt

Reading the line status register
(LSR)

0 1 0 0 2 Received data available

Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode.

Reading the receiver buffer
register (RBR)

1 1 0 0 2

Character timeout
indication

No characters have been
removed from or input to the
receiver FIFO during the last
four character times and there
is at least one character in it
during this time

Reading the receiver buffer
register (RBR)

0 0 1 0 3

Transmitter holding
register empty

Transmitter holding register
empty

Reading the interrupt
identification register (IIR) (if
source of interrupt) or writing
into the transmitter holding
register (THR)

0 0 0 0 4 Modem status

Clear to send, data set ready,
ring indicator, or data carrier
detect

Reading the modem status
register (MSR)

line control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.

D

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 6.

T able 6. Serial Character Word Length

Bit 1 Bit 0 Word Length

0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits

D

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character . When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks the first stop bit only,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 7.

TL16C550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS057D – AUGUST 1989 – REVISED MARCH 1996

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PRINCIPLES OF OPERATION

line control register (LCR) (continued)

Table 7. Number of Stop Bits Generated

Bit 2

Word Length Selected

by Bits 1 and 2

Number of Stop

Bits Generated

0 Any word length 1
1 5 bits 1 1/2
1 6 bits 2
1 7 bits 2
1 8 bits 2

D

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in the transmitted data
between the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked.
When bit 3 is cleared, no parity is generated or checked.

D

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1’s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.

D

Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. When
bit 5 is cleared, stick parity is disabled.

D

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e., a condition where the serial
output (SOUT) terminal is forced to the spacing (low) state. When bit 6 is cleared, the break condition is
disabled. The break condition has no affect on the transmitter logic; it only affects the serial output.

D

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.

line status register (LSR)

†

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are described in the following bulleted list and summarized in Table 3.

D

Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO and is cleared by reading all of the
data in the RBR or the FIFO.

D

Bit 1‡: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator
is cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO
beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been
completely received in the shift register. OE is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten but is not transferred to the FIFO.

†

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environmen

t

‡

Bits 1 through 4 are the error conditions that produce a receiver line status Interrupt.

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PRINCIPLES OF OPERATION

line status register (LSR)

†

(continued)

D

Bit 2‡.: This bit is the parity error (PE) indicator . When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character
in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top
of the FIFO.

D

Bit 3‡: This bit is the framing error (FE) indicator . When bit 3 is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE then samples this start bit twice and then accepts the input data.

D

Bit 4‡: This bit is the break interrupt (BI) indicator . When bit 4 is set, it indicates that the received data input
was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the
total time of the start, data, parity , and stop bits. The BI bit is cleared every time the CPU reads the contents
of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When
break occurs, only the 0 character is loaded into the FIFO. The next character transfer is enabled after SIN
goes to the marking state and receives the next valid start bit.

D

Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when the
transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.

D

Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO
mode, this bit is set when the transmitter FIFO and shift register are both empty.

D

Bit 7: In the TL16C550A, this bit is always cleared. In the TL16C450 mode, this bit is cleared. In the FIFO
mode, LSR7 is set when there is at least one parity , framing, or break error in the FIFO. It is cleared when
the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in T able 3 and are described in the following
bulleted list.

D

Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its low state. When bit 0 is cleared, DTR

goes high.

D

Bit 1: This bit (RTS) controls the request to send (R TS) output in a manner identical to bit 0’ s control over
the DTR

output.

D

Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR

output.

†

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environmen

t

‡

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

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PRINCIPLES OF OPERATION

modem control register (MCR) (continued)

D

Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user-designated output signal, in a manner
identical to bit 0’s control over the DTR

output.

D

Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the
following occurs:

1. The SOUT is set high.

2. The SIN is disconnected.

3. The output of the TSR is looped back into the RSR input.

4. The four modem control inputs (CTS

, DSR, DCD, and RI) are disconnected.

5. The four modem control outputs (DTR

, RTS, OUT1, and OUT2) are internally connected to the four

modem control inputs.

6. The four modem control output terminals are forced to their inactive states (high).
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify

the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational but the modem control interrupt’s sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.

D

Bit 5 – 7: These bits are permanently cleared.

modem status register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.

D

Bit 0: This bit is the change in clear to send (∆CTS) indicator . Bit 0 indicates that the CTS input has changed
states since the last time it was read by the CPU . When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.

D

Bit 1: This bit is the change in data set ready (∆DSR) indicator. Bit 1 indicates that the DSR input has
changed states since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.

D

Bit 2: This bit is the trailing edge of ring indicator (TERI) detector . Bit 2 indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a
modem status interrupt is generated.

D

Bit 3: This bit is the change in data carrier detect (∆DCD) indicator. Bit 3 indicates that the DCD input to
the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.

D

Bit 4: This bit is the compliment of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set,
bit 4 is equivalent to the MCR bit 1 (RTS).

D

Bit 5: This bit is the compliment of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
bit 5 is equivalent to the MCR bit 1 (DTR).

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PRINCIPLES OF OPERATION

modem status register (MSR) (continued)

D

Bit 6: This bit is the compliment of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6
is equivalent to the MCR bit 2 (OUT1).

D

Bit 7: This bit is the compliment of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
bit 7 is equivalent to the MCR bit 3 (OUT2).

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 8 MHz
and divides it by a divisor in the range between 1 and (2

16

–1). The output frequency of the baud generator is

16× the baud rate. The formula for the divisor is:

divisor # = XIN frequency input ÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

Tables 8 and 9, which follow, illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz
and 3.072 MHz, respectively For baud rates of 38.4 kbit/s and below, the error obtained is very small. The
accuracy of the selected baud rate is dependent on the selected crystal frequency.

Refer to Figure 16 for examples of typical clock circuits.

Table 8. Baud Rates Using a 1.8432-MHz Crystal

DESIRED

BAUD RATE

DIVISOR USED
TO GENERATE

16× CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

50 2304
75 1536

110 1047 0.026

134.5 857 0.058
150 768
300 384
600 192

1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16

9600 12
19200 6
38400 3
56000 2 2.86

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PRINCIPLES OF OPERATION

programmable baud generator (continued)

Table 9. Baud Rates Using a 3.072-MHz Crystal

DESIRED

BAUD RATE

DIVISOR USED
TO GENERATE

16× CLOCK

PERCENT ERROR

DIFFERENCE BETWEEN

DESIRED AND ACTUAL

50 3840
75 2560

110 1745 0.026

134.5 1428 0.034
150 1280
300 640
600 320

1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23

9600 20
19200 10
38400 5

Driver

Optional
Driver

External

Clock

Optional

Clock

Output

Oscillator Clock
to Baud
Generator Logic

XIN

XOUT

V

CC

Crystal

Oscillator Clock
to Baud
Generator Logic

XIN

RX2

V

CC

XOUT

C1

R

p

C2

TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

R

P

RX2 C1 C2

3.1 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

1.8 MHz 1 MΩ 1.5 kΩ 10–30 pF 40–60 pF

Figure 16. Typical Clock Circuits

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receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.

The ACEs RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it
into the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data
available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of
the RBR. in the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

scratch register

The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is suppled by the baud out (BAUDOUT

) clock signal. Transmitter section control is a

function of the ACE line control register.
The ACE THR receives data off the internal data bus and, when the shift register is idle, moves it into the TSR.

The TSR serializes the data and outputs it at the serial output (SOUT). In the TL16C450 mode, when the THR
is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.

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