Datasheet TL071CP Specification

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Page 1

−

IN+

IN−

OUT

IN+

IN−

OUT

TL072 (each amplifier) TL074 (each amplifier)

TL071

OFFSET N1

OFFSET N2

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

TL07xx Low-Noise FET-Input Operational Amplifiers

1 Features

• High slew rate: 20 V/μs (TL07xH, typ)

• Low offset voltage: 1 mV (TL07xH, typ)

• Low offset voltage drift: 2 μV/°C

• Low power consumption: 940 μA/ch (TL07xH, typ)

• Wide common-mode and differential voltage ranges

– Common-mode input voltage range

includes V

CC+

• Low input bias and offset currents

• Low noise: Vn = 18 nV/√Hz (typ) at f = 1 kHz

• Output short-circuit protection

• Low total harmonic distortion: 0.003% (typ)

• Wide supply voltage: ±2.25 V to ±20 V, 4.5 V to 40 V

2 Applications

• Solar energy: string and central inverter

• Motor drives: AC and servo drive control and

power stage modules

• Single phase online UPS

• Three phase UPS

• Pro audio mixers

• Battery test equipment

3 Description

The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industry-standard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive applications, with features including low offset (1 mV, typical), high slew rate (20 V/μs), and common-mode input to the positive supply. High ESD

(1.5 kV, HBM), integrated EMI and RF filters, and operation across the full –40°C to 125°C enable the TL07xH devices to be used in the most rugged and demanding applications.

Device Information

PART NUMBER

TL071x

TL072x

TL072M

TL074x

TL074M

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(1)

PACKAGE BODY SIZE (NOM)

PDIP (8) 9.59 mm × 6.35 mm SC70 (5) 2.00 mm × 1.25 mm SO (8) 6.20 mm × 5.30 mm SOIC (8) 4.90 mm × 3.90 mm SOT-23 (5) 1.60 mm × 1.20 mm PDIP (8) 9.59 mm × 6.35 mm SO (8) 6.20 mm × 5.30 mm SOIC (8) 4.90 mm × 3.90 mm SOT-23 (8) 2.90 mm × 1.60 mm TSSOP (8) 4.40 mm × 3.00 mm CDIP (8) 9.59 mm × 6.67 mm CFP (10) 6.12 mm × 3.56 mm LCCC (20) 8.89 mm × 8.89 mm PDIP (14) 19.30 mm × 6.35 mm SO (14) 10.30 mm × 5.30 mm SOIC (14) 8.65 mm × 3.91 mm SOT-23 (14) 4.20 mm × 2.00 mm SSOP (14) 6.20 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm CDIP (14) 19.56 mm × 6.92 mm CFP (14) 9.21 mm × 6.29 mm LCCC (20) 8.89 mm × 8.89 mm

Logic Symbols

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Page 2

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

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1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................5

6 Specifications................................................................ 12

6.1 Absolute Maximum Ratings: TL07xH .......................12

6.2 Absolute Maximum Ratings: All Devices Except

TL07xH........................................................................12

6.3 ESD Ratings: TL07xH ..............................................12

6.4 ESD Ratings: All Devices Except TL07xH................13

6.5 Recommended Operating Conditions: TL07xH ....... 13

6.6 Recommended Operating Conditions: All

Devices Except TL07xH..............................................13

6.7 Thermal Information for Single Channel: TL071H ... 13

6.8 Thermal Information: TL071x....................................14

6.9 Thermal Information for Dual Channel: TL072H ......14

6.10 Thermal Information: TL072x..................................14

6.11 Thermal Information: TL072x (cont.).......................15

6.12 Thermal Information for Quad Channel: TL074H ...15

6.13 Thermal Information: TL074x..................................15

6.14 Thermal Information: TL074x (cont)........................16

6.15 Thermal Information: TL074x (cont)........................16

6.16 Thermal Information................................................16

6.17 Electrical Characteristics: TL07xH .........................17

6.18 Electrical Characteristics: TL071C, TL072C,

TL074C........................................................................19

6.19 Electrical Characteristics: TL071AC, TL072AC,

TL074AC..................................................................... 20

6.20 Electrical Characteristics: TL071BC, TL072BC,

TL074BC..................................................................... 21

6.21 Electrical Characteristics: TL071I, TL072I,

TL074I......................................................................... 22

6.22 Electrical Characteristics: TL071M, TL072M.......... 23

6.23 Electrical Characteristics: TL074M......................... 24

6.24 Switching Characteristics: TL07xM.........................25

6.25 Switching Characteristics: TL07xC, TL07xAC,

TL07xBC, TL07xI........................................................ 25

6.26 Typical Characteristics: TL07xH............................. 26

6.27 Typical Characteristics: All Devices Except

TL07xH........................................................................33

7 Parameter Measurement Information..........................37

8 Detailed Description......................................................38

8.1 Overview...................................................................38

8.2 Functional Block Diagram.........................................38

8.3 Feature Description...................................................39

8.4 Device Functional Modes..........................................39

9 Application and Implementation..................................40

9.1 Application Information............................................. 40

9.2 Typical Application....................................................40

9.3 Unity Gain Buffer.......................................................41

9.4 System Examples..................................................... 42

10 Power Supply Recommendations..............................43

11 Layout...........................................................................43

11.1 Layout Guidelines................................................... 43

11.2 Layout Example...................................................... 44

12 Device and Documentation Support..........................45

12.1 Receiving Notification of Documentation Updates..45

12.2 Support Resources................................................. 45

12.3 Trademarks.............................................................45

12.4 Electrostatic Discharge Caution..............................45

12.5 Glossary..................................................................45

13 Mechanical, Packaging, and Orderable

Information.................................................................... 45

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision R (June 2021) to Revision S (July 2021) Page

• Deleted preview note from TL071H SOIC (8), SOT-23 (5) and SC70 (5) packages throughout the data sheet 1

Changes from Revision Q (June 2021) to Revision R (June 2021) Page

• Deleted preview note from TL072H SOIC (8), SOT-23 (8) and TSSOP (8) packages throughout the data

sheet...................................................................................................................................................................1

• Added ESD information for TL072H................................................................................................................. 12

• Added IQ spec for TL072H................................................................................................................................17

Changes from Revision P (November 2020) to Revision Q (June 2021) Page

• Deleted VSSOP (8) package from the Device Information section.................................................................... 1

• Added DBV, DCK, and D packages to TL071H in Pin Configuration and Functions section..............................5

• Deleted DGK package from TL072x in Pin Configuration and Functions section.............................................. 5

• Deleted tables with duplicate information from the Specifications section....................................................... 12

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TL071, TL071A, TL071B, TL071H

TL072, TL072A, TL072B, TL072H, TL072M

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TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

• Added D, DCK, and DBV package thermal information in Thermal Information for Single Channel: TL071H

section.............................................................................................................................................................. 13

• Added D, DDF, and PW package thermal information in Thermal Information for Dual Channel: TL072H

section.............................................................................................................................................................. 14

• Added IB and IOS specification for single channel DCK and DBV package...................................................... 17

• Added IQ spec for TL071H................................................................................................................................17

• Deleted Related Links section from the Device and Documentation Support section......................................45

Changes from Revision O (October 2020) to Revision P (November 2020) Page

• Added SOIC and TSSOP package thermal information in Thermal Information for Quad Channel: TL074H

section ........................................................................................................................................................... 15

• Added Typical Characteristics:TL07xH section in Specifications section......................................................... 26

Changes from Revision N (July 2017) to Revision O (October 2020) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document..................1

• Features of TL07xH added to the Features section........................................................................................... 1

• Added link to applications in the Applications section........................................................................................ 1

• Added TL07xH in the Description section...........................................................................................................1

• Added TL07xH device in the Device Information section................................................................................... 1

• Added SOT-23 (14), VSSOP (8), SOT-23 (8), SC70 (5), and SOT-23 (5) packages to the Device Information

section................................................................................................................................................................ 1

• Added TSSOP, VSSOP and DDF packages to TL072x in Pin Configuration and Functions section.................5

• Added DYY package to TL074x in Pin Configuration and Functions section.....................................................5

• Removed Table of Graphs from the Typical Characteistics section..................................................................33

• Deleted reference to obsolete documentation in Layout Guidelines section....................................................43

• Removed Related Documentation section....................................................................................................... 45

Changes from Revision M (February 2014) to Revision N (July 2017) Page

• Updated data sheet text to latest documentation and translation standards......................................................1

• Added TL072M and TL074M devices to data sheet ..........................................................................................1

• Rewrote text in Description section ................................................................................................................... 1

• Changed TL07x 8-pin PDIP package to 8-pin CDIP package in Device Information table ............................... 1

• Deleted 20-pin LCCC package from Device Information table ..........................................................................1

• Added 2017 copyright statement to front page schematic..................................................................................1

• Deleted TL071x FK (LCCC) pinout drawing and pinout table in Pin Configurations and Functions section ..... 5

• Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................5

• Deleted differential input voltage parameter from Absolute Maximum Ratings table ...................................... 12

• Deleted table notes from Absolute Maximum Ratings table ............................................................................12

• Added new table note to Absolute Maximum Ratings table ............................................................................ 12

• Changed minimum supply voltage value from –18 V to –0.3 V in Absolute Maximum Ratings table...............12

• Changed maximum supply voltage from 18 V to 36 V in Absolute Maximum Ratings table............................ 12

• Changed minimum input voltage value from –15 V to V

• Changed maximum input voltage from 15 V to V

CC–

– 0.3 V in Absolute Maximum Ratings table....... 12

CC–

+ 36 V in Absolute Maximum Ratings table...................12

• Added input clamp current parameter to Absolute Maximum Ratings table ....................................................12

• Changed common-mode voltage maximum value from V

– 4 V to V

CC+

in the Recommended Operating

CC+

Conditions table................................................................................................................................................13

• Changed devices in Recommended Operating Conditions table from TL07xA and TL07xB to TL07xAC and

TL07xBC ..........................................................................................................................................................13

• Added TL07xI operating free-air temperature minimum value of –40°C to Recommended Operating

Conditions table ...............................................................................................................................................13

• Added U (CFP) package thermal values to Thermal Information: TL072x (cont.) table................................... 15

• Added W (CFP) package thermal values to Thermal Information: TL074x (cont.) table.................................. 16

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

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• Added Figure 6-59 to Typical Characteristics section.......................................................................................33

• Added second Typical Application section application curves .........................................................................41

• Reformatted document references in Layout Guidelines section .................................................................... 43

Changes from Revision L (February 2014) to Revision M (February 2014) Page

• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply

Recommendations section, Layout section........................................................................................................ 1

Changes from Revision K (January 2014) to Revision L (February 2014) Page

• Moved T

to Handling Ratings table ..............................................................................................................13

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Page 5

1OUT

2V±

3IN+ 4 IN±

5 V+

Not to scale

1NC 8 NC

2IN– 7 VCC+

3IN+ 6 OUT

4VCC– 5 NC

Not to scale

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5 Pin Configuration and Functions

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

Figure 5-1. TL071H DBV and DCK Package

5-Pin SOT-23, and SC70

Top View

Table 5-1. Pin Functions: TL071H

NAME DBV, DCK D

IN– 4 2 I Inverting input IN+ 3 3 I Noninverting input NC 8 — Do not connect NC 1 — Do not connect NC 5 — Do not connect OUT 1 6 O Output VCC– 2 4 — Power supply VCC+ 5 7 — Power supply

I/O DESCRIPTION

NC- no internal connection

Figure 5-2. TL071H D Package

8-Pin SOIC

Top View

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TL074B TL074H TL074M

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1OFFSET N1 8 NC

2IN± 7 VCC+

3IN+ 6 OUT

4VCC± 5 OFFSET N2

Not to scale

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

NC- no internal connection

Figure 5-3. TL071x D, P, and PS Package

8-Pin SOIC, PDIP, and SO

Top View

Table 5-2. Pin Functions: TL071x

NAME NO.

IN– 2 I Inverting input IN+ 3 I Noninverting input NC 8 — Do not connect OFFSET N1 1 — Input offset adjustment OFFSET N2 5 — Input offset adjustment OUT 6 O Output VCC– 4 — Power supply VCC+ 7 — Power supply

I/O DESCRIPTION

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11OUT 8 VCC+

21IN± 7 2OUT

31IN+ 6 2IN±

4VCC± 5 2IN+

Not to scale

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Figure 5-4. TL072x D, DDF, JG, P, PS, and PW Package

8-Pin SOIC, SOT-23 (8), CDIP, PDIP, SO, and TSSOP

Table 5-3. Pin Functions: TL072x

NAME NO.

1IN– 2 I Inverting input 1IN+ 3 I Noninverting input 1OUT 1 O Output 2IN– 6 I Inverting input 2IN+ 5 I Noninverting input 2OUT 7 O Output VCC– 4 — Power supply VCC+ 8 — Power supply

I/O DESCRIPTION

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

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1NC 10 NC

21OUT 9 VCC+

31IN± 8 2OUT

41IN+ 7 2IN±

5VCC± 6 2IN+

Not to scale

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

NC- no internal connection

Figure 5-5. TL072x U Package

Table 5-4. Pin Functions: TL072x

NAME NO.

1IN– 3 I Inverting input 1IN+ 4 I Noninverting input 1OUT 2 O Output 2IN– 7 I Inverting input 2IN+ 6 I Noninverting input 2OUT 8 O Output NC 1, 10 — Do not connect VCC– 5 — Power supply VCC+ 9 — Power supply

I/O DESCRIPTION

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10-Pin CFP

Top View

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Page 9

4NC

51IN±

6NC

71IN+

8NC

9NC

10VCC±

11NC

122IN+

13NC

14 NC

15 2IN±

16 NC

17 2OUT

18 NC

19 NC

20 VCC+

1 NC

2 1OUT

3 NC

Not to scale

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NC- no internal connection

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

Figure 5-6. TL072 FK Package

20-Pin LCCC

Top View

Table 5-5. Pin Functions: TL072x

NAME NO.

1IN– 5 I Inverting input 1IN+ 7 I Noninverting input 1OUT 2 O Output 2IN– 15 I Inverting input 2IN+ 12 I Noninverting input 2OUT 17 O Output

1, 3, 4, 6, 8,

9, 11, 13, 14,

16, 18, 19 VCC– 10 — Power supply VCC+ 20 — Power supply

I/O DESCRIPTION

— Do not connect

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11OUT 14 4OUT

21IN± 13 4IN±

31IN+ 12 4IN+

4VCC+ 11 VCC±

52IN+ 10 3IN+

62IN± 9 3IN±

72OUT 8 3OUT

Not to scale

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

Figure 5-7. TL074x D, N, NS, PW, J, DYY, and W Package

14-Pin SOIC, PDIP, SO, TSSOP, CDIP, SOT-23 (14), and CFP

Table 5-6. Pin Functions: TL074x

NAME NO.

1IN– 2 I Inverting input 1IN+ 3 I Noninverting input 1OUT 1 O Output 2IN– 6 I Inverting input 2IN+ 5 I Noninverting input 2OUT 7 O Output 3IN– 9 I Inverting input 3IN+ 10 I Noninverting input 3OUT 8 O Output 4IN– 13 I Inverting input 4IN+ 12 I Noninverting input 4OUT 14 O Output V

CC–

CC+

11 — Power supply

4 — Power supply

I/O DESCRIPTION

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41IN+

5NC

6VCC+

7NC

82IN+

92IN±

102OUT

11NC

123OUT

133IN±

14 3IN+

15 NC

16 VCC±

17 NC

18 4IN+

19 4IN±

20 4OUT

1 NC

2 1OUT

3 1IN±

Not to scale

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NC- no internal connection

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

Figure 5-8. TL074 FK Package

20-Pin LCCC

Top View

Table 5-7. Pin Functions: TL074x

NAME NO.

1IN– 3 I Inverting input 1IN+ 4 I Noninverting input 1OUT 2 O Output 2IN– 9 I Inverting input 2IN+ 8 I Noninverting input 2OUT 10 O Output 3IN– 13 I Inverting input 3IN+ 14 I Noninverting input 3OUT 12 O Output 4IN– 19 I Inverting input 4IN+ 18 I Noninverting input 4OUT 20 O Output

1, 5, 7, 11, 15,

17 VCC– 16 — Power supply VCC+ 6 — Power supply

I/O DESCRIPTION

— Do not connect

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

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6 Specifications

6.1 Absolute Maximum Ratings: TL07xH

over operating ambient temperature range (unless otherwise noted)

Supply voltage, VS = (V

Signal input pins

Output short-circuit Operating ambient temperature, T Junction temperature, T Storage temperature, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability. (2) Short-circuit to ground, one amplifier per package. (3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

) – (V

CC+

(2)

stg

) 0 42 V

CC–

Common-mode voltage Differential voltage

(3)

Current

(3)

(1)

MIN MAX UNIT

) – 0.5 (V

CC–

–10 10 mA

Continuous

–55 150 °C

–65 150 °C

CC+

VS + 0.2 V

) + 0.5 V

150 °C

6.2 Absolute Maximum Ratings: All Devices Except TL07xH

over operating free-air temperature range (unless otherwise noted)

- V

CC+

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the

dissipation rating is not exceeded. (3) Differential voltage only limited by input voltage.

Supply voltage –0.3 36 V

CC–

Input voltage

(3)

Input clamp current –50 mA Duration of output short circuit

(2)

Operating virtual junction temperature 150 °C Case temperature for 60 seconds - FK package 260 °C Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 °C Storage temperature –65 150 °C

(1)

MIN MAX UNIT

– 0.3 V

CC–

+ 36 V

CC–

Unlimited

6.3 ESD Ratings: TL07xH

VALUE UNIT

TL074H

(ESD)

Electrostatic discharge

TL072H and TL071H

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1)

±1500

(2)

±1000

±2000

(2)

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

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SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.4 ESD Ratings: All Devices Except TL07xH

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

(2)

C101

(1)

6.5 Recommended Operating Conditions: TL07xH

over operating ambient temperature range (unless otherwise noted)

MIN MAX UNIT

Supply voltage, (V Input voltage range (V Specified temperature –40 125 °C

CC+

) – (V

) 4.5 40 V

CC–

) + 2 (V

CC–

CC+

6.6 Recommended Operating Conditions: All Devices Except TL07xH

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

CC+

CC–

Supply voltage Supply voltage Common-mode voltage V

Operating free-air temperature

(1)

5 15 V

–5 –15 V

+ 4 V

CC–

TL07xM –55 125 TL08xQ –40 125 TL07xI –40 85 TL07xAC, TL07xBC, TL07xC 0 70

VALUE UNIT

±2000

CC+

±1000

) + 0.1 V

°C

(1) V

CC+

and V

are not required to be of equal magnitude, provided that the total VCC (V

CC–

CC+

– V

) is between 10 V and 30 V.

CC–

6.7 Thermal Information for Single Channel: TL071H

TL071H

(SOIC)

8 PINS 5 PINS 5 PINS

θJA

θJC(top)

θJB

θJC(bot)

THERMAL METRIC

Junction-to-ambient thermal resistance 158.8 217.5 212.2 °C/W Junction-to-case (top) thermal resistance 98.6 113.1 111.1 °C/W Junction-to-board thermal resistance 102.3 63.8 79.4 °C/W Junction-to-top characterization parameter 45.8 34.8 51.8 °C/W Junction-to-board characterization parameter 101.5 63.5 79.0 °C/W Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W

(1)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

DCK

(SC70)

DBV

(SOT-23)

UNIT

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

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6.8 Thermal Information: TL071x

TL071x

THERMAL METRIC

(1)

UNITD (SOIC) P (PDIP) PS (SO)

8 PINS 8 PINS 8 PINS

θJA

θJC(top)

Junction-to-ambient thermal resistance 97 85 95 °C/W Junction-to-case (top) thermal resistance — — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.9 Thermal Information for Dual Channel: TL072H

TL072H

θJA

θJC(top)

θJB

θJC(bot)

THERMAL METRIC

Junction-to-ambient thermal resistance 147.8 181.5 200.3 °C/W Junction-to-case (top) thermal resistance 88.2 112.5 89.4 °C/W Junction-to-board thermal resistance 91.4 98.2 131.0 °C/W Junction-to-top characterization parameter 36.8 17.2 22.2 °C/W Junction-to-board characterization parameter 90.6 97.6 129.3 °C/W Junction-to-case (bottom) thermal resistance N/A N/A N/A °C/W

(1)

(SOIC)

8 PINS 8 PINS 8 PINS

DDF

(SOT-23)

(TSSOP)

UNIT

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.10 Thermal Information: TL072x

TL072x

THERMAL METRIC

θJA

θJC(top)

Junction-to-ambient thermal resistance 97 — 85 95 °C/W Junction-to-case (top) thermal resistance — 15.05 — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(1)

UNITD (SOIC) JG (CDIP) P (PDIP) PS (SO)

8 PINS 8 PINS 8 PINS 8 PINS

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6.11 Thermal Information: TL072x (cont.)

TL072x

THERMAL METRIC

(1)

UNITPW (TSSOP) U (CFP) FK (LCCC)

8 PINS 10 PINS 20 PINS

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance 150 169.8 — °C/W Junction-to-case (top) thermal resistance — 62.1 5.61 °C/W Junction-to-board thermal resistance — 176.2 — °C/W Junction-to-top characterization parameter — 48.4 — °C/W Junction-to-board characterization parameter — 144.1 — °C/W Junction-to-case (bottom) thermal resistance — 5.4 — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.12 Thermal Information for Quad Channel: TL074H

TL074H

(2)

DYY

(SOT-23)

(TSSOP)

UNIT

θJA

θJC(top)

θJB

θJC(bot)

THERMAL METRIC

Junction-to-ambient thermal resistance 114.2 TBD 134.4 °C/W Junction-to-case (top) thermal resistance 70.3 TBD 62.6 °C/W Junction-to-board thermal resistance 70.2 TBD 77.6 °C/W Junction-to-top characterization parameter 28.8 TBD 13.0 °C/W Junction-to-board characterization parameter 69.8 TBD 77.0 °C/W Junction-to-case (bottom) thermal resistance N/A TBD N/A °C/W

(1)

(SOIC)

14 PINS 14 PINS 14 PINS

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) This package option is preview for TL074H.

6.13 Thermal Information: TL074x

TL074x

THERMAL METRIC

θJA

θJC(top)

Junction-to-ambient thermal resistance 86 80 76 °C/W Junction-to-case (top) thermal resistance — — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(1)

UNITD (SOIC) N (PDIP) NS (SO)

14 PINS 14 PINS 14 PINS

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6.14 Thermal Information: TL074x (cont).

TL074x

THERMAL METRIC

(1)

UNITJ (CDIP) PW (TSSOP) W (CFP)

14 PINS 14 PINS 14 PINS

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance — 113 128.8 °C/W Junction-to-case (top) thermal resistance 14.5 — 56.1 °C/W Junction-to-board thermal resistance — — 127.6 °C/W Junction-to-top characterization parameter — — 29 °C/W Junction-to-board characterization parameter — — 106.1 °C/W Junction-to-case (bottom) thermal resistance — — 0.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.15 Thermal Information: TL074x (cont).

TL074x

(1)

UNITFK (LCCC)

20 PINS

θJA

θJC(top)

THERMAL METRIC

Junction-to-ambient thermal resistance — °C/W Junction-to-case (top) thermal resistance 5.61 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.16 Thermal Information

TL071/TL072/TL074

THERMAL METRIC

Junction-to-ambient

θJA

thermal resistance Junction-to-case (top)

θJC(top)

thermal resistance

(1)

D (SOIC)

8 PINS

PINS

97 86 — — — 85 80 95 76 150 113 °C/W

— — 5.61 15.05 14.5 — — — — — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(LCCC)

J (CDIP) N (PDIP) NS (SO) PW (TSSOP)

20 PINS 8 PINS

PINS

8 PINS

PINS

8 PINS 14 PINS

PINS

UNIT

PINS

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6.17 Electrical Characteristics: TL07xH

For VS = (V V

= VS / 2, unless otherwise noted.

OUT

OFFSET VOLTAGE

dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±2 µV/℃

PSRR

INPUT BIAS CURRENT

NOISE

INPUT VOLTAGE RANGE

CMRR

INPUT CAPACITANCE

ICM

OPEN-LOOP GAIN

FREQUENCY RESPONSE

GBW Gain-bandwidth product 5.25 MHz SR Slew rate VS = 40 V, G = +1, CL = 20 pF 20 V/μs

CC+

) – (V

) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

CC–

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input offset voltage

Input offset voltage versus power supply

VS = 5 V to 40 V, VCM = VS / 2

TA = –40°C to 125°C ±5

TA = –40°C to 125°C ±1 ±10 μV/V

±1 ±4

Channel separation f = 0 Hz 10 µV/V

±1 ±120 pA

Input bias current

DCK and DBV packages ±1 ±300 pA TA = –40°C to 125°C

(1)

±5 nA

±0.5 ±120 pA

Input offset current

Input voltage noise f = 0.1 Hz to 10 Hz

Input voltage noise density

f = 1 kHz 37 f = 10 kHz 21

DCK and DBV packages ±0.5 ±250 pA TA = –40°C to 125°C

(1)

±5 nA

9.2 μV

1.4 µV

nV/√Hz

Input current noise f = 1 kHz 80 fA/√Hz

Common-mode voltage range

Common-mode rejection ratio

VS = 40 V, (V VCM < (V

CC+

VS = 40 V, (V VCM < (V

CC+

) + 2.5 V <

CC–

) – 1.5 V

) + 2.5 V <

CC–

)

TA = –40°C to 125°C 95 dB

TA = –40°C to 125°C 80 dB

) + 1.5 (V

CC–

100 105 dB

90 105 dB

CC+

) V

Differential 100 || 2 MΩ || pF Common-mode 6 || 1 TΩ || pF

VS = 40 V, VCM = VS / 2,

Open-loop voltage gain

) + 0.3 V < VO < (V

CC–

– 0.3 V

)

TA = –40°C to 125°C 118 125 dB

CC+

VS = 40 V, VCM = VS / 2, RL =

Open-loop voltage gain

Settling time

2 kΩ, (V (V

CC+

) – 1.2 V

) + 1.2 V < VO <

CC–

To 0.1%, VS = 40 V, V To 0.1%, VS = 40 V, V To 0.01%, VS = 40 V, V To 0.01%, VS = 40 V, V

TA = –40°C to 125°C 115 120 dB

= 10 V , G = +1, CL = 20 pF 0.63

STEP

= 2 V , G = +1, CL = 20 pF 0.56

STEP

= 10 V , G = +1, CL = 20 pF 0.91

STEP

= 2 V , G = +1, CL = 20 pF 0.48

STEP

Phase margin G = +1, RL = 10kΩ, CL = 20 pF 56 ° Overload recovery time V

× gain > V

300 ns

RMS

μs

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6.17 Electrical Characteristics: TL07xH (continued)

For VS = (V V

= VS / 2, unless otherwise noted.

OUT

THD+N

EMIRR EMI rejection ratio f = 1 GHz 53 dB

OUTPUT

LOAD

POWER SUPPLY

) – (V

CC+

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Total harmonic distortion + noise

Voltage output swing from rail

Short-circuit current ±26 mA Capacitive load drive 300 pF Open-loop output

impedance

Quiescent current per amplifier

Turn-On Time At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs 60 μs

) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and

CC–

VS = 40 V, VO = 6 V

Positive rail headroom

Negative rail headroom

f = 1 MHz, IO = 0 A 125 Ω

IO = 0 A 937.5 1125 IO = 0 A, (TL071H) 960 1156 IO = 0 A IO = 0 A, (TL072H) 1143 IO = 0 A, (TL071H) 1160

, G = +1, f = 1 kHz 0.00012 %

RMS

VS = 40 V, RL = 10 kΩ 115 210 VS = 40 V, RL = 2 kΩ 520 965 VS = 40 V, RL = 10 kΩ 105 215 VS = 40 V, RL = 2 kΩ 500 1030

1130

TA = –40°C to 125°C

µA

(1) Max IB and Ios data is specified based on characterization results.

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6.18 Electrical Characteristics: TL071C, TL072C, TL074C

= ±15 V (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS

ICR

Input offset voltage

Temperature coefficient of input offset voltage

Input offset current VO = 0

Input bias current

(3)

Common-mode input voltage range

VO = 0 RS = 50 Ω

VO = 0

TA = 25°C ±11 –12 to 15 V

TA = 25°C 3 10 TA = Full range 13

TA = Full range 18 µV/°C

TA = 25°C 5 100 pA TA = Full range 10 nA TA = 25°C 65 200 pA TA = Full range 7 nA

RL= 10 kΩ TA = 25°C ±12 ±13.5

CMRR

SVR

Maximum peak output voltage swing

Large-signal differential voltage amplification

RL≥ 2 kΩ ±10

VO = ±10 V RL≥ 2 kΩ

TA = Full range

TA = 25°C 25 200

TA = Full range 15 Utility-gain bandwidth TA = 25°C 3 MHz Input resistance TA = 25°C 10

VIC = V

Common-mode rejection ratio

Supply voltage rejection ratio (ΔV

/ΔVIO)

CC±

Supply current (each amplifier)

ICR(min)

VO = 0

TA = 25°C 70 100 dB

RS = 50 Ω VCC = ±9 V to ±15 V

VO = 0

TA = 25°C 70 100 dB

RS = 50 Ω

VO = 0; no load TA = 25°C 1.4 2.5 mA

VO1 / VO2Crosstalk attenuation AVD = 100 TA = 25°C 120 dB

(1) (2)

MIN TYP MAX UNIT

±12

VRL≥ 10 kΩ

V/mV

(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. (2) Full range is TA = 0°C to 70°C. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.

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6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC

= ±15 V (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS

ICR

Input offset voltage

Temperature coefficient of input offset voltage

Input offset current VO = 0

Input bias current

(3)

Common-mode input voltage range

VO = 0 RS = 50 Ω

VO = 0

TA = 25°C ±11 –12 to 15 V

RL= 10 kΩ TA = 25°C ±12 ±13.5

Maximum peak output voltage swing

RL≥ 2 kΩ ±10

Large-signal differential voltage amplification

Utility-gain bandwidth TA = 25°C 3 MHz Input resistance TA = 25°C 10

CMRR Common-mode rejection ratio

VO = ±10 V RL≥ 2 kΩ

VIC = V

ICR(min)

VO = 0 RS = 50 Ω

SVR

Supply-voltage rejection ratio (ΔV

/ ΔVIO)

CC±

Supply current (each amplifier)

VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω

VO = 0; no load TA = 25°C 1.4 2.5 mA

VO1 / VO2Crosstalk attenuation AVD = 100 TA = 25°C 120 dB

(1) (2)

MIN TYP MAX UNIT

TA = 25°C 3 6 TA = Full range 7.5

TA = Full range 18 µV/°C

TA = 25°C 5 100 pA TA = Full range 2 nA TA = 25°C 65 200 pA TA = Full range 7 nA

TA = Full range

±12

TA = 25°C 50 200 TA = Full range 25

TA = 25°C 75 100 dB

TA = 25°C 80 100 dB

VRL≥ 10 kΩ

V/mV

shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.

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6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC

= ±15 V (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS

ICR

Input offset voltage

Temperature coefficient of input offset voltage

Input offset current VO = 0

Input bias current

(3)

Common-mode input voltage range

VO = 0 RS = 50 Ω

VO = 0

TA = 25°C ±11 –12 to 15 V

RL= 10 kΩ TA = 25°C ±12 ±13.5

Maximum peak output voltage swing

RL≥ 2 kΩ ±10

CMRR

SVR

Large-signal differential voltage amplification

Utility-gain bandwidth TA = 25°C 3 MHz Input resistance TA = 25°C 10

Common-mode rejection ratio

Supply-voltage rejection ratio (ΔV

CC±

/ΔVIO)

Supply current (each amplifier)

VO = ±10 V RL ≥ 2 kΩ

VIC = V

ICR(min)

VO = 0 RS = 50 Ω

VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω

VO = 0; no load TA = 25°C 1.4 2.5 mA

VO1 / VO2Crosstalk attenuation AVD = 100 TA = 25°C 120 dB

(1) (2)

MIN TYP MAX UNIT

TA = 25°C 2 3 TA = Full range 5

TA = Full range 18 µV/°C

TA = 25°C 5 100 pA TA = Full range 2 nA TA = 25°C 65 200 pA TA = Full range 7 nA

TA = Full range

±12

TA = 25°C 50 200 TA = Full range 25

TA = 25°C 75 100 dB

TA = 25°C 80 100 dB

VRL≥ 10 kΩ

V/mV

shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.

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6.21 Electrical Characteristics: TL071I, TL072I, TL074I

= ±15 V (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS

ICR

Input offset voltage

Temperature coefficient of input offset voltage

Input offset current VO = 0

Input bias current

(3)

Common-mode input voltage range

VO = 0 RS = 50 Ω

VO = 0

TA = 25°C ±11 –12 to 15 V

RL= 10 kΩ TA = 25°C ±12 ±13.5

Maximum peak output voltage swing

RL ≥ 2 kΩ ±10

CMRR

SVR

Large-signal differential voltage amplification

Utility-gain bandwidth TA = 25°C 3 MHz Input resistance TA = 25°C 10

Common-mode rejection ratio

Supply-voltage rejection ratio (ΔV

CC±

/ΔVIO)

Supply current (each amplifier)

VO = ±10 V RL ≥ 2 kΩ

VIC = V

ICR(min)

VO = 0 RS = 50 Ω

VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω

VO = 0; no load TA = 25°C 1.4 2.5 mA

VO1 / VO2Crosstalk attenuation AVD = 100 TA = 25°C 120 dB

(1) (2)

MIN TYP MAX UNIT

TA = 25°C 3 6 TA = Full range 8

TA = Full range 18 µV/°C

TA = 25°C 5 100 pA TA = Full range 2 nA TA = 25°C 65 200 pA TA = Full range 7 nA

TA = Full range

±12

TA = 25°C 50 200 TA = Full range 25

TA = 25°C 75 100 dB

TA = 25°C 80 100 dB

VRL ≥ 10 kΩ

V/mV

(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. (2) TA = –40°C to 85°C. (3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Input Bias Current vs Free-Air Temperature. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.

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6.22 Electrical Characteristics: TL071M, TL072M

= ±15 V (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS

VIO

ICR

CMRR

SVR

VO1 / V

Input offset voltage

Temperature coefficient of input offset voltage

Input offset current VO = 0

Input bias current VO = 0

Common-mode input voltage range

Maximum peak output voltage swing

Large-signal differential voltage amplification

Unity-gain bandwidth 3 MHz Input resistance 10

Common-mode rejection ratio

Supply-voltage rejection ratio (ΔV

CC±

/ΔVIO)

Supply current (each amplifier)

Crosstalk attenuation AVD = 100 TA = 25°C 120 dB

VO = 0 RS = 50 Ω

TA = 25°C ±11 –12 to 15 V

RL = 10 kΩ TA = 25°C ±12 ±13.5

RL ≥ 2 kΩ ±10

VO = ±10 V RL ≥ 2 kΩ

VIC = V

ICR(min)

, VO = 0 RS = 50 Ω

VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω

VO = 0; no load TA = 25°C 1.4 2.5 mA

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SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

(1) (2)

TA = 25°C 3 6 TA = Full range 9

TA = Full range 18 μV/°C

TA = 25°C 5 100 pA TA = Full range 20 nA TA = 25°C 65 200 pA TA = Full range 50 nA

TA = Full range

TA = 25°C 35 200 TA = Full range 15

TA = 25°C 80 86 dB

MIN TYP MAX UNIT

±12

VRL ≥ 10 kΩ

V/mV

(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Input Bias Current vs Free-Air Temperature. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.

(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is

TA = –55°C to +125°C.

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6.23 Electrical Characteristics: TL074M

= ±15 V (unless otherwise noted)

CC±

PARAMETER TEST CONDITIONS

VIO

ICR

CMRR

SVR

VO1 / V

Input offset voltage

Temperature coefficient of input offset voltage

Input offset current VO = 0

Input bias current VO = 0

Common-mode input voltage range

Maximum peak output voltage swing

Large-signal differential voltage amplification

Unity-gain bandwidth 3 MHz Input resistance 10

Common-mode rejection ratio

Supply-voltage rejection ratio (ΔV

CC±

/ΔVIO)

Supply current (each amplifier)

Crosstalk attenuation AVD = 100 TA = 25°C 120 dB

VO = 0 RS = 50 Ω

VO = 0, RS = 50 Ω TA = Full range 18 μV/°C

TA = 25°C ±11 –12 to 15 V

RL = 10 kΩ TA = 25°C ±12 ±13.5

RL ≥ 2 kΩ ±10

VO = ±10 V RL ≥ 2 kΩ

VIC = V

ICR(min)

VO = 0 RS = 50 Ω

VCC = ±9 V to ±15 V VO = 0 RS = 50 Ω

VO = 0; no load TA = 25°C 1.4 2.5 mA

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(1) (2)

TA = 25°C 3 9 TA = Full range 15

MIN TYP MAX UNIT

TA = 25°C 5 100 pA TA = Full range 20 nA TA = 25°C 65 200 pA TA = Full range 20 nA

TA = Full range

TA = 25°C 35 200 TA = Full range 15

±12

V/mV

Ω

TA = 25°C 80 86 dB

VRL ≥ 10 kΩ

(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as

shown in Input Bias Current vs Free-Air Temperature. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must be used .

(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is

TA = –55°C to +125°C.

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6.24 Switching Characteristics: TL07xM

= ±15 V, TA = 25°C

CC±

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SR Slew rate at unity gain

Rise-time overshoot factor

Equivalent input noise voltage RS = 20 Ω

Equivalent input noise current RS = 20 Ω f = 1 kHz 0.01 pA/√ Hz

THD Total harmonic distortion

VI = 10 V CL = 100 pF

VI = 20 V CL = 100 pF

VIrms = 6 V RL ≥ 2 kΩ f = 1 kHz

RL = 2 kΩ See Figure 7-1

f = 1 kHz 18 nV/√ Hz f = 10 Hz to 10 kHz 4 μV

AVD = 1 RS ≤ 1 kΩ

6.25 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI

= ±15 V, TA = 25°C

CC±

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SR Slew rate at unity gain

Rise-time overshoot factor

Equivalent input noise voltage RS = 20 Ω

Equivalent input noise current RS = 20 Ω f = 1 kHz 0.01 pA/√ Hz

THD Total harmonic distortion

VI = 10 V CL = 100 pF

VI = 20 V CL = 100 pF

VIrms = 6 V RL ≥ 2 kΩ f = 1 kHz

RL = 2 kΩ See Figure 7-1

f = 1 kHz 18 nV/√ Hz f = 10 Hz to 10 kHz 4 μV

AVD = 1 RS ≤ 1 kΩ

TL071, TL071A, TL071B, TL071H

5 13 V/μs

0.1 μs

20%

0.003%

8 13 V/μs

0.1 μs

20%

0.003%

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.26 Typical Characteristics: TL07xH

www.ti.com

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, R

TA = 25°C

Figure 6-1. Offset Voltage Production Distribution

= 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

LOAD

Figure 6-2. Offset Voltage Drift Distribution

VCM = VS / 2

Figure 6-3. Offset Voltage vs Temperature

TA = 125°C

Figure 6-5. Offset Voltage vs Common-Mode Voltage

TA = 25°C

Figure 6-4. Offset Voltage vs Common-Mode Voltage

TA = –40°C

Figure 6-6. Offset Voltage vs Common-Mode Voltage

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Page 27

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6.26 Typical Characteristics: TL07xH (continued)

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, R

Figure 6-7. Offset Voltage vs Power Supply

= 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

LOAD

Figure 6-8. Open-Loop Gain and Phase vs Frequency

Figure 6-9. Closed-Loop Gain vs Frequency

Figure 6-11. Input Bias Current vs Temperature Figure 6-12. Output Voltage Swing vs Output Current (Sourcing)

Figure 6-10. Input Bias Current vs Common-Mode Voltage

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TL074B TL074H TL074M

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.26 Typical Characteristics: TL07xH (continued)

www.ti.com

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, R

Figure 6-13. Output Voltage Swing vs Output Current (Sinking)

= 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

LOAD

Figure 6-14. CMRR and PSRR vs Frequency

f = 0 Hz

Figure 6-15. CMRR vs Temperature (dB)

Figure 6-17. 0.1-Hz to 10-Hz Noise

f = 0 Hz

Figure 6-16. PSRR vs Temperature (dB)

Figure 6-18. Input Voltage Noise Spectral Density vs Frequency

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Page 29

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6.26 Typical Characteristics: TL07xH (continued)

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, R

BW = 80 kHz, V

Figure 6-19. THD+N Ratio vs Frequency

OUT

= 1 V

RMS

= 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

LOAD

BW = 80 kHz, f = 1 kHz

Figure 6-20. THD+N vs Output Amplitude

VCM = VS / 2

Figure 6-21. Quiescent Current vs Supply Voltage

Figure 6-23. Open-Loop Voltage Gain vs Temperature (dB)

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

Figure 6-22. Quiescent Current vs Temperature

Figure 6-24. Open-Loop Output Impedance vs Frequency

TL074B TL074H TL074M

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.26 Typical Characteristics: TL07xH (continued)

www.ti.com

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, R

G = –1, 25-mV output step

Figure 6-25. Small-Signal Overshoot vs Capacitive Load

= 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

LOAD

G = 1, 10-mV output step

Figure 6-26. Small-Signal Overshoot vs Capacitive Load

Figure 6-27. Phase Margin vs Capacitive Load

G = –10

Figure 6-29. Positive Overload Recovery

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VS = ±10 V, VIN = V

Figure 6-28. No Phase Reversal

G = –10

Figure 6-30. Negative Overload Recovery

OUT

Page 31

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6.26 Typical Characteristics: TL07xH (continued)

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, R

CL = 20 pF, G = 1, 10-mV step response

Figure 6-31. Small-Signal Step Response, Rising

= 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

LOAD

CL = 20 pF, G = 1, 10-mV step response

Figure 6-32. Small-Signal Step Response, Falling

CL = 20 pF, G = 1

Figure 6-33. Large-Signal Step Response (Rising)

CL = 20 pF, G = 1

Figure 6-35. Large-Signal Step Response

CL = 20 pF, G = 1

Figure 6-34. Large-Signal Step Response (Falling)

Figure 6-36. Short-Circuit Current vs Temperature

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

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TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.26 Typical Characteristics: TL07xH (continued)

www.ti.com

at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, R

Figure 6-37. Maximum Output Voltage vs Frequency

= 10 kΩ connected to VS / 2, and CL = 20 pF (unless otherwise noted)

LOAD

Figure 6-38. Channel Separation vs Frequency

Figure 6-39. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency

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Page 33

IIB− Input Bias Current − nA

− Free-Air Temperature − °C

0.1

0.01

100

−75 −50 −25 0 25 50 75 100 125

= ±15 V

RL= 10 kΩ TA= 25°C See Figure 2

±15

±12.5

±10

±7.5

±5

±2.5

VOM − Maximum Peak Output V

oltage − V

f − Frequency − Hz

100 1 k 10 k 100 k 1 M 10 M

= ±5 V

= ±10 V

= ±15 V

10 M1 M100 k10 k1 k100

f − Frequency − Hz

VOM − Maximum Peak Output V

oltage − V

±2.5

±5

±7.5

±10

±12.5

±15

See Figure 2

TA= 25°C

RL= 2 k

= ±10 V

= ±5 V

= ±15 V

−75

VOM − Maximum Peak Output V

oltage − V

− Free-Air Temperature − °C

125

±15

−50 −25 0 25 50 75 100

±2.5

±5

±7.5

±10

±12.5

RL= 10 k

= ±15 V

See Figure 2

RL= 2 kΩ

0.1

− Load Resistance − k

±15

±2.5

±5

±7.5

±10

±12.5

= ±15 V TA= 25°C See Figure 2

0.2 0.4 0.7 1 2 4 7

VOM − Maximum Peak Output V

oltage − V

www.ti.com

6.27 Typical Characteristics: All Devices Except TL07xH

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

Figure 6-40. Input Bias Current vs Free-Air Temperature

Figure 6-42. Maximum Peak Output Voltage vs Frequency

Figure 6-41. Maximum Peak Output Voltage vs Frequency

Figure 6-43. Maximum Peak Output Voltage vs Frequency

Figure 6-44. Maximum Peak Output Voltage vs Free-Air

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

Temperature

Figure 6-45. Maximum Peak Output Voltage vs Load Resistance

TL074B TL074H TL074M

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VOM − Maximum Peak Output V

oltage − V

| − Supply Voltage − V

±15

2 4 6 8 10 12 14

±2.5

±5

±7.5

±10

±12.5

RL= 10 k

TA= 25°C

−75

Voltage

Amplification − V/mV

− Free-Air Temperature − °C

125

1000

−50 −25 0 25 50 75 100

100

200

400

= ±15 V

VO= ±10 V RL= 2 k

AVD − Large-Signal Differential

1.02

1.01

0.99

0.98

1.03

0.97

−75

0.7

Normalized Unity-Gain Bandwidth

− Free-Air Temperature − °C

125

1.3

−50 −25 0 25 50 75 100

0.8

0.9

1.1

1.2

Unity-Gain Bandwidth

= ±15 V

RL= 2 k

f = B1for Phase Shift

Phase Shift

Normalized Phase Shift

−75

CMRR − Common-Mode Rejection Ratio − dB

− Free-Air Temperature − °C

125

−50 −25 0 25 50 75 100

= ±15 V

RL= 10 k

| − Supply Voltage − V

2 4 6 8 10 12 14

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

TA= 25°C No Signal No Load

ICC − Supply Current Per

Amplifier − mA

CC±

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.27 Typical Characteristics: All Devices Except TL07xH (continued)

www.ti.com

Figure 6-46. Maximum Peak Output Voltage vs Supply Voltage

Figure 6-48. Large-Signal Differential Voltage Amplification and

Figure 6-50. Common-Mode Rejection Ratio vs Free-Air

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Phase Shift vs Frequency

Temperature

Figure 6-47. Large-Signal Differential Voltage Amplification vs

Free-Air Temperature

Figure 6-49. Normalized Unity-Gain Bandwidth and Phase Shift

vs Free-Air Temperature

Figure 6-51. Supply Current Per Amplifier vs Supply Voltage

TL074B TL074H TL074M

Page 35

−75

− Free-Air Temperature − °C

125

−50 −25 0 25 50 75 100

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

= ±15 V

No Signal No Load

ICC − Supply Current Per

Amplifier − mA

CC±

−75

−

Free-Air Temperature −C°

125

250

−50 −25 0 25 50 75 100

100

125

150

175

200

225

= 15 V±

No Signal No Load

TL074

TL071

TL072

− Total Power Dissipation − mW

− Equivalent Input Noise V

oltage − nV/Hz

f − Frequency − Hz

100 k

= ±15 V AVD= 10 RS= 20

TA= 25°C

40 100 400 1 k 4 k 10 k 40 k

nV/

0.001

THD − T

otal Harmonic Distortion − %

40 k10 k4 k1 k400 100 k

f − Frequency − Hz

100

0.004

0.01

0.04

0.1

0.4

= ±15 V AVD= 1 V

I(RMS)

= 6 V

TA= 25°C

−6

t − Time −

3.5

0.5 1 1.5 2 2.5 3

−4

−2

Output

Input

= ±15 V

RL= 2 k

TA= 25°C

CL= 100 pF

− Input and Output V

oltages − V

and

TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

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SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.27 Typical Characteristics: All Devices Except TL07xH (continued)

TL071, TL071A, TL071B, TL071H

Figure 6-52. Supply Current Per Amplifier vs Free-Air

Temperature

Figure 6-54. Normalized Slew Rate vs Free-Air Temperature

Figure 6-53. Total Power Dissipation vs Free-Air Temperature

Figure 6-55. Equivalent Input Noise Voltage vs Frequency

Figure 6-56. Total Harmonic Distortion vs Frequency

Figure 6-57. Voltage-Follower Large-Signal Pulse Response

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Page 36

VCM (V)

VIO (mV)

-13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 13 15 17

-10

-8

-6

-4

-2

D003

VCCr = r15 V

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

6.27 Typical Characteristics: All Devices Except TL07xH (continued)

www.ti.com

Figure 6-58. Output Voltage vs Elapsed Time

Figure 6-59. VIO vs V

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Page 37

CL= 100 pF

RL= 2 kΩ

−

OUT

10 kΩ

1 kΩ

CL= 100 pF

−

OUT

www.ti.com

7 Parameter Measurement Information

Figure 7-1. Unity-Gain Amplifier

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

Figure 7-2. Gain-of-10 Inverting Amplifier

Figure 7-3. Input Offset-Voltage Null Circuit

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

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Page 38

CC+

IN+

CC−

1080 Ω

IN−

TL071 Only

64 Ω

128 Ω

64 Ω

All component values shown are nominal.

OFFSET

OUT

18 pF

COMPONENT COUNT

†

COMPONENT

TYPE

TL071 TL072 TL074

Resistors 11 22 44Resistors Transistors

11 14

22 28

44 56

Transistors JFET

JFET Diodes

2 1

4 2

6 4

Diodes Capacitors

1 1

2 2

4 4

Capacitors epi-FET

1 1

2 2

4 4

†

Includes bias and trim circuitry

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

www.ti.com

8 Detailed Description

8.1 Overview

The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industrystandard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive applications, with features including low offset (1 mV, typ), high slew rate (25 V/μs, typ), and common-mode input to the positive supply. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and operation across the full –40°C to 125°C enable the TL07xH devices to be used in the most rugged and demanding applications.

The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to +85°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to +125°C.

8.2 Functional Block Diagram

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Page 39

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M

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TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

8.3 Feature Description

The TL07xH family of devices improve many specifications as compared to the industry-standard TL07x family. Several comparisons of key specifications between these families are included below to show the advantages of the TL07xH family.

8.3.1 Total Harmonic Distortion

Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These devices have a very low THD of 0.003% meaning that the TL07x device adds little harmonic distortion when used in audio signal applications.

8.3.2 Slew Rate

The slew rate is the rate at which an operational amplifier can change the output when there is a change on the input. These devices have a 13-V/μs slew rate.

8.4 Device Functional Modes

These devices are powered on when the supply is connected. These devices can be operated as a single-supply operational amplifier or dual-supply amplifier depending on the application.

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

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Page 40

Vsup+

VOUT

VIN

Vsup-

VOUT

A =

1.8

A = 3.6

0.5

= -

A =

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

www.ti.com

9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage on the input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative voltages positive.

9.2 Typical Application

Figure 9-1. Inverting Amplifier

9.2.1 Design Requirements

The supply voltage must be selected so the supply voltage is larger than the input voltage range and output range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient to accommodate this application.

9.2.2 Detailed Design Procedure

Vo= Vi+ Vio* 1 +

1MΩ

1kΩ

(1)

Determine the gain required by the inverting amplifier:

(2)

(3)

Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw too much current. This example uses 10 kΩ for RI which means 36 kΩ is used for RF. This is determined by

Equation 4.

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(4)

Page 41

-2

-1.5

-1

-0.5

0.5

1.5

0 0.5 1 1.5 2

Volts

Time (ms)

VIN

VOUT

10 k

U1 TL072

VOUT

VIN

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9.2.3 Application Curve

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

Figure 9-2. Input and Output Voltages of the Inverting Amplifier

9.3 Unity Gain Buffer

Figure 9-3. Single-Supply Unity Gain Amplifier

9.3.1 Design Requirements

• VCC must be within valid range per Section 6.6. This example uses a value of 12 V for VCC.

• Input voltage must be within the recommended common-mode range, as shown in Section 6.6. The valid common-mode range is 4 V to 12 V (V

• Output is limited by output range, which is typically 1.5 V to 10.5 V, or V

9.3.2 Detailed Design Procedure

• Avoid input voltage values below 1 V to prevent phase reversal where output goes high.

• Avoid input values below 4 V to prevent degraded VIO that results in an apparent gain greater than 1. This may cause instability in some second-order filter designs.

+ 4 V to V

CC–

CC+

+ 1.5 V to V

CC–

CC+

– 1.5 V.

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Page 42

VIN (V)

VOUT (V)

0 2 4 6 8 10 12

D001

VIN (V)

Gain (V/V)

0 2 4 6 8 10 12

-1.5

-1

-0.5

0.5

1.5

D002

Output

CC–

–

CC+

R1 R2 2R3 1.5 M

C1 C2 110 pF

f 1kHz

2 R1C1

= = = W

= = =

= =

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

9.3.3 Application Curves

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Figure 9-4. Output Voltage vs Input Voltage

9.4 System Examples

Figure 9-6. 0.5-Hz Square-Wave Oscillator

Figure 9-5. Gain vs Input Voltage

Figure 9-7. High-Q Notch Filter

Figure 9-8. 100-kHz Quadrature Oscillator

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Figure 9-9. AC Amplifier

TL074B TL074H TL074M

Page 43

TL071, TL071A, TL071B, TL071H

TL072, TL072A, TL072B, TL072H, TL072M

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TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

10 Power Supply Recommendations

CAUTION

Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply can permanently damage the device (see Section 6.2).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.

– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Section 11.2.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

to ground is applicable for single-

CC+

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

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Page 44

VCC+

IN1í

IN1+

VCCí

OUT

RIN

GND

VIN

VS-GND

VS+

GND

as possible

Only needed for

dual-supply

operation

Place components close to device and to each other to

reduce parasitic errors

Use low-ESR, ceramic

bypass capacitor

(or GND for single supply) Ground (GND) plane on another layerVOUT

RIN

VOUT

TL071, TL071A, TL071B, TL071H TL072, TL072A, TL072B, TL072H, TL072M TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

11.2 Layout Example

Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration

www.ti.com

Figure 11-2. Operational Amplifier Schematic for Noninverting Configuration

44 Submit Document Feedback

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

Page 45

TL071, TL071A, TL071B, TL071H

TL072, TL072A, TL072B, TL072H, TL072M

www.ti.com

TL074, TL074A, TL074B, TL074H, TL074M

SLOS080S – SEPTEMBER 1978 – REVISED JULY 2021

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation.

Product Folder Links: TL071 TL071A TL071B TL071H TL072 TL072A TL072B TL072H TL072M TL074 TL074A

TL074B TL074H TL074M

Submit Document Feedback

Page 46

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

81023052A ACTIVE LCCC FK 20 1 Non-RoHS

8102305HA ACTIVE CFP U 10 1 Non-RoHS

8102305PA ACTIVE CDIP JG 8 1 Non-RoHS

81023062A ACTIVE LCCC FK 20 1 Non-RoHS

8102306CA ACTIVE CDIP J 14 1 Non-RoHS

8102306DA ACTIVE CFP W 14 1 Non-RoHS

JM38510/11905BPA ACTIVE CDIP JG 8 1 Non-RoHS

M38510/11905BPA ACTIVE CDIP JG 8 1 Non-RoHS

PTL071HIDBVR ACTIVE SOT-23 DBV 5 3000 Non-RoHS &

PTL071HIDCKR ACTIVE SC70 DCK 5 3000 Non-RoHS &

PTL071HIDR ACTIVE SOIC D 8 3000 Non-RoHS &

PTL072HIPWR ACTIVE TSSOP PW 8 3000 Non-RoHS &

TL071ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& Green

Non-Green

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

SNPB N / A for Pkg Type -55 to 125 81023052A

TL072MFKB

SNPB N / A for Pkg Type -55 to 125 8102305HA

TL072M

SNPB N / A for Pkg Type -55 to 125 8102305PA

TL072M

SNPB N / A for Pkg Type -55 to 125 81023062A

TL074MFKB

SNPB N / A for Pkg Type -55 to 125 8102306CA

TL074MJB

SNPB N / A for Pkg Type -55 to 125 8102306DA

TL074MWB

SNPB N / A for Pkg Type -55 to 125 JM38510

/11905BPA

SNPB N / A for Pkg Type -55 to 125 JM38510

/11905BPA

Call TI Call TI -40 to 125

14-Jul-2021

Samples

(4/5)

TL071ACDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC

TL071ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071AC

TL071ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071ACP

TL071BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071BC

Addendum-Page 1

Page 47

PACKAGE OPTION ADDENDUM

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Orderable Device Status

TL071BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 071BC

TL071BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071BCP

TL071CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C

TL071CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C

TL071CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C

TL071CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL071C

TL071CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071CP

TL071CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL071CP

TL071CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T071

TL071ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I

TL071IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

14-Jul-2021

Op Temp (°C) Device Marking

(4/5)

Samples

TL071IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL071I

TL071IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL071IP

TL072ACD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC

TL072ACDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC

TL072ACDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC TL072ACDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072AC

TL072ACP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072ACP

TL072ACPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072ACP

TL072BCD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC

Addendum-Page 2

Page 48

PACKAGE OPTION ADDENDUM

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Orderable Device Status

TL072BCDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC

TL072BCDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC

TL072BCDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC TL072BCDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 072BC

TL072BCP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072BCP

TL072BCPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072BCP

TL072CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C TL072CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C

TL072CDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C

TL072CDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

14-Jul-2021

Op Temp (°C) Device Marking

(4/5)

Samples

TL072CDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL072C

TL072CP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072CP

TL072CPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL072CP

TL072CPS ACTIVE SO PS 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072

TL072CPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072

TL072CPSRE4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPSRG4 ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072

TL072CPWR ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPWRE4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072 TL072CPWRG4 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T072

Addendum-Page 3

Page 49

PACKAGE OPTION ADDENDUM

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Orderable Device Status

TL072HIDDFR ACTIVE SOT-23-THIN DDF 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 O72F

TL072HIDR ACTIVE SOIC D 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TL072D

TL072ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDE4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I TL072IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I

TL072IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I

TL072IDRE4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I

TL072IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL072I

TL072IP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL072IP TL072IPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL072IP

TL072MFKB ACTIVE LCCC FK 20 1 Non-RoHS

TL072MJG ACTIVE CDIP JG 8 1 Non-RoHS

TL072MJGB ACTIVE CDIP JG 8 1 Non-RoHS

TL072MUB ACTIVE CFP U 10 1 Non-RoHS

TL074ACD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& Green

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

SNPB N / A for Pkg Type -55 to 125 81023052A

TL072MFKB

SNPB N / A for Pkg Type -55 to 125 TL072MJG

SNPB N / A for Pkg Type -55 to 125 8102305PA

TL072M

SNPB N / A for Pkg Type -55 to 125 8102305HA

TL072M

14-Jul-2021

Samples

(4/5)

TL074ACDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC

TL074ACDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC TL074ACDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC

TL074ACN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074ACN

Addendum-Page 4

Page 50

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TL074ACNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074ACN

TL074ACNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074A

TL074BCD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC

TL074BCDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC

TL074BCDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC TL074BCDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074BC

TL074BCN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074BCN

TL074BCNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074BCN

TL074CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C

TL074CDBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

14-Jul-2021

Op Temp (°C) Device Marking

(4/5)

Samples

TL074CDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C

TL074CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM 0 to 70 TL074C

TL074CDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074C

TL074CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074CN

TL074CNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TL074CN

TL074CNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074 TL074CNSRG4 ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TL074

TL074CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074

TL074CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074

TL074CPWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074

Addendum-Page 5

Page 51

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

TL074CPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 T074

TL074HIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL074HID

TL074HIPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL074PW

TL074ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I TL074IDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I

TL074IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I

TL074IDRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I

TL074IDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I

TL074IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TL074IN TL074MFK ACTIVE LCCC FK 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 TL074MFK

& Green

TL074MFKB ACTIVE LCCC FK 20 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 81023062A

& Green

TL074MJ ACTIVE CDIP J 14 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 TL074MJ

& Green

TL074MJB ACTIVE CDIP J 14 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 8102306CA

& Green

TL074MWB ACTIVE CFP W 14 1 Non-RoHS

SNPB N / A for Pkg Type -55 to 125 8102306DA

& Green

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

14-Jul-2021

Op Temp (°C) Device Marking

(4/5)

TL074MFKB

TL074MJB

TL074MWB

Samples

Addendum-Page 6

Page 52

PACKAGE OPTION ADDENDUM

www.ti.com

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M :

Catalog : TL072, TL074

•

14-Jul-2021

Enhanced Product : TL072-EP, TL072-EP, TL074-EP, TL074-EP

•

Military : TL072M, TL074M

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Addendum-Page 7

Page 53

PACKAGE OPTION ADDENDUM

www.ti.com

Military - QML certified for Military and Defense Applications

•

14-Jul-2021

Addendum-Page 8

Page 54

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TL071ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL071BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL071CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL071CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL071CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

TL071IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072ACDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072BCDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL072CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL072CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL072CPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

TL072CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1

TL072HIDDFR SOT-

23-THIN

TL072HIDR SOIC D 8 3000 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL072IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

TL072IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TL074ACDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

DDF 8 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

Page 55

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2021

Device Package

TL074ACNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

TL074BCDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TL074CDBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

TL074CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL074CDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL074CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

TL074CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TL074HIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

TL074HIPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

TL074IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Type

Package

Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL071ACDR SOIC D 8 2500 340.5 338.1 20.6 TL071BCDR SOIC D 8 2500 340.5 338.1 20.6

TL071CDR SOIC D 8 2500 340.5 338.1 20.6

TL071CDR SOIC D 8 2500 853.0 449.0 35.0

TL071CPSR SO PS 8 2000 853.0 449.0 35.0

TL071IDR SOIC D 8 2500 340.5 338.1 20.6

TL072ACDR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2

Page 56

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2021

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL072BCDR SOIC D 8 2500 340.5 338.1 20.6

TL072CDR SOIC D 8 2500 340.5 338.1 20.6

TL072CDR SOIC D 8 2500 853.0 449.0 35.0

TL072CPSR SO PS 8 2000 853.0 449.0 35.0

TL072CPWR TSSOP PW 8 2000 853.0 449.0 35.0

TL072HIDDFR SOT-23-THIN DDF 8 3000 210.0 185.0 35.0

TL072HIDR SOIC D 8 3000 853.0 449.0 35.0

TL072IDR SOIC D 8 2500 853.0 449.0 35.0 TL072IDR SOIC D 8 2500 340.5 338.1 20.6

TL074ACDR SOIC D 14 2500 333.2 345.9 28.6

TL074ACNSR SO NS 14 2000 853.0 449.0 35.0

TL074BCDR SOIC D 14 2500 333.2 345.9 28.6 TL074CDBR SSOP DB 14 2000 853.0 449.0 35.0

TL074CDR SOIC D 14 2500 333.2 345.9 28.6

TL074CDRG4 SOIC D 14 2500 333.2 345.9 28.6

TL074CNSR SO NS 14 2000 853.0 449.0 35.0

TL074CPWR TSSOP PW 14 2000 853.0 449.0 35.0

TL074HIDR SOIC D 14 2500 853.0 449.0 35.0

TL074HIPWR TSSOP PW 14 2000 853.0 449.0 35.0

TL074IDR SOIC D 14 2500 333.2 345.9 28.6

Pack Materials-Page 3

Page 57

Page 58

PACKAGE OUTLINE

PIN 1

INDEX AREA

2X 0.95

1.9

0.5

0.3

0.2 C A B

3.05

2.75

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

0.1 C

1.45

0.90

(1.1)

0.15

0.00

TYP

SCALE 4.000

3.0

2.6

1.75

1.45

1.9

0.25

GAGE PLANE

TYP

0.6

0.3

TYP

SEATING PLANE

0.22

0.08

TYP

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

www.ti.com

Page 59

EXAMPLE BOARD LAYOUT

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

2X (0.95)

(R0.05) TYP

SOLDER MASK OPENING

5X (0.6)

5X (1.1)

PKG

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

METAL

METAL UNDER SOLDER MASK

SYMM

(1.9)

SOLDER MASK OPENING

EXPOSED METAL

0.07 MAX ARROUND

NON SOLDER MASK

DEFINED

(PREFERRED)

EXPOSED METAL

0.07 MIN ARROUND

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

4214839/E 09/2019

www.ti.com

Page 60

5X (0.6)

2X(0.95)

EXAMPLE STENCIL DESIGN

SOT-23 - 1.45 mm max heightDBV0005A

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

SYMM

(1.9)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

Page 61

Page 62

PACKAGE OUTLINE

12X .100

[2.54]

PIN 1 ID

(OPTIONAL)

-.785.754

-19.9419.15[ ]

SCALE 0.900

4X .005 MIN

14X -.065.045

[0.13]

-1.651.15[ ]

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

TYP-.060.015

-1.520.38[ ]

14X -.026.014

-0.660.36[ ]

.010 [0.25] C A B

B -.283.245

AT GAGE PLANE

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This package is hermitically sealed with a ceramic lid using glass frit.

4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.

5. Falls within MIL-STD-1835 and GDIP1-T14.

TYP

-7.196.22[ ]

-.314.308

-7.977.83[ ]

-15

.015 GAGE PLANE [0.38]

14X .008-.014 [0.2-0.36]

.2 MAX TYP

[5.08]

.13 MIN TYP [3.3]

SEATING PLANE

4214771/A 05/2017

www.ti.com

Page 63

SEE DETAIL A

(.300 ) TYP

[7.62]

EXAMPLE BOARD LAYOUT

CDIP - 5.08 mm max heightJ0014A

CERAMIC DUAL IN LINE PACKAGE

SEE DETAIL B

12X (.100 )

[2.54]

14X ( .039)

[1]

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED

SCALE: 5X

SYMM

MAX.002

[0.05]

ALL AROUND

(R.002 ) TYP

[0.05]

(.063)

[1.6]

DETAIL A

SCALE: 15X

SOLDER MASK OPENING

METAL

www.ti.com

METAL

SOLDER MASK

OPENING

( .063)

[1.6]

.002 MAX [0.05] ALL AROUND

DETAIL B

13X, SCALE: 15X

4214771/A 05/2017

Page 64

Page 65

Page 66

Page 67

Page 68

PACKAGE OUTLINE

.189-.197 [4.81-5.00]

NOTE 3

.228-.244 TYP [5.80-6.19]

B .150-.157

[3.81-3.98]

PIN 1 ID AREA

NOTE 4

SCALE 2.800

6X .050

[1.27]

.150 [3.81]

8X .012-.020 [0.31-0.51]

.010 [0.25] C A B

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.004 [0.1] C

4X (0 -15 )

.069 MAX

[1.75]

.005-.010 TYP [0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010 [0.25]

0 - 8

.016-.050 [0.41-1.27]

(.041) [1.04]

DETAIL A

TYPICAL

.004-.010 [0.11-0.25]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

Page 69

8X (.061 )

8X (.024)

6X (.050 )

[1.27]

[0.6]

[1.55]

SYMM

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

EXAMPLE BOARD LAYOUT

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

SEE DETAILS

SYMM

(R.002 ) TYP

[0.05]

EXPOSED

METAL

NON SOLDER MASK

SOLDER MASK OPENING

.0028 MAX [0.07] ALL AROUND

DEFINED

SOLDER MASK

OPENING

EXPOSED

METAL

.0028 MIN [0.07] ALL AROUND

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL UNDER SOLDER MASK

4214825/C 02/2019

www.ti.com

Page 70

8X (.061 )

8X (.024)

6X (.050 )

[1.27]

[0.6]

[1.55]

EXAMPLE STENCIL DESIGN

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

SYMM

(R.002 ) TYP

(.213)

[5.4]

[0.05]

BASED ON .005 INCH [0.125 MM] THICK STENCIL

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SCALE:8X

4214825/C 02/2019

SOLDER PASTE EXAMPLE

www.ti.com

Page 71

Page 72

Page 73

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.063 (1,60)

0.015 (0,38)

0.100 (2,54)

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.023 (0,58)

0.015 (0,38)

0.280 (7,11)

0.245 (6,22)

0.310 (7,87)

0.290 (7,37)

0.200 (5,08) MAX Seating Plane

0.130 (3,30) MIN

0°–15°

0.014 (0,36)

0.008 (0,20)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

4040107/C 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 74

Page 75

Page 76

PACKAGE OUTLINE

3.1

2.9

NOTE 3

SCALE 2.800

6.6 TYP

6.2

PIN 1 ID AREA

4.5

4.3

NOTE 4

6X 0.65

1.95

0.30

0.19

0.1 C A B

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

SEATING PLANE

0.1 C

1.2 MAX

SEE DETAIL A

(0.15) TYP

0.25

GAGE PLANE

0 - 8

0.75

0.50

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

0.15

0.05

www.ti.com

Page 77

EXAMPLE BOARD LAYOUT

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

8X (0.45)

6X (0.65)

SOLDER MASK OPENING

8X (1.5)

METAL

SYMM

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER SOLDER MASK

(R ) TYP

SYMM

0.05

SOLDER MASK OPENING

0.05 MAX ALL AROUND

NON SOLDER MASK

DEFINED

0.05 MIN ALL AROUND

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

4221848/A 02/2015

Page 78

EXAMPLE STENCIL DESIGN

TSSOP - 1.2 mm max heightPW0008A

SMALL OUTLINE PACKAGE

8X (0.45)

6X (0.65)

8X (1.5)

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

(R ) TYP0.05

SYMM

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

Page 79

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

2,00 MAX

0,38 0,22

0,05 MIN

0,15

5,60 5,00

8,20 7,40

Seating Plane

0,10

0,25 0,09

0°–ā8°

Gage Plane

0,25

0,95 0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

6,50

5,905,90

2016

7,50

6,90

8,50

10,50

9,907,90

10,50

9,90

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 80

PACKAGE OUTLINE

.045 MAX

TYP

8X .050 .005

10X .017 .002

.010 .002

PIN 1 ID

5X .32 .01

SCALE 1.400

.27 MAX

GLASS

+.019

-.003

CFP - 2.03 mm max heightU0010A

CERAMIC FLATPACK

.005 MIN TYP

.27 MAX

GLASS

5X .32 .01.241

.005 .001

4225582/A 01/2020

NOTES:

1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

.067

.045 .026

+.013

-.012

www.ti.com

Page 81

Page 82

Page 83

PACKAGE OUTLINE

2.95

2.85

NOTE 3

SCALE 4.000

2.95 TYP

2.65

PIN 1 ID AREA

1.65

1.55

6X 0.65

1.95

0.4

0.2

0.1 C A B

SOT-23 - 1.1 mm max heightDDF0008A

PLASTIC SMALL OUTLINE

SEATING PLANE

0.1 C

1.1 MAX

0.20 TYP

0.08

SEE DETAIL A

0.25

GAGE PLANE

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side.

0.1

0.0

www.ti.com

Page 84

EXAMPLE BOARD LAYOUT

SOT-23 - 1.1 mm max heightDDF0008A

PLASTIC SMALL OUTLINE

SOLDER MASK OPENING

8X (1.05)

8X (0.45)

6X (0.65)

(R )

0.05

TYP

SYMM

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

METAL

METAL UNDER SOLDER MASK

SYMM

SOLDER MASK OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

4222047/B 11/2015

Page 85

EXAMPLE STENCIL DESIGN

SOT-23 - 1.1 mm max heightDDF0008A

PLASTIC SMALL OUTLINE

8X (1.05)

8X (0.45)

6X (0.65)

SYMM

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

(R ) TYP0.05

SYMM

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

Page 86

Page 87

Page 88

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datasheet TL071CP Specification

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings: TL07xH

6.2 Absolute Maximum Ratings: All Devices Except TL07xH

6.3 ESD Ratings: TL07xH

6.4 ESD Ratings: All Devices Except TL07xH

6.5 Recommended Operating Conditions: TL07xH

6.6 Recommended Operating Conditions: All Devices Except TL07xH

6.7 Thermal Information for Single Channel: TL071H

6.8 Thermal Information: TL071x

6.9 Thermal Information for Dual Channel: TL072H

6.10 Thermal Information: TL072x

6.11 Thermal Information: TL072x (cont.)

6.12 Thermal Information for Quad Channel: TL074H

6.13 Thermal Information: TL074x

6.14 Thermal Information: TL074x (cont).

6.15 Thermal Information: TL074x (cont).

6.16 Thermal Information

6.17 Electrical Characteristics: TL07xH

6.18 Electrical Characteristics: TL071C, TL072C, TL074C

6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC

6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC

6.21 Electrical Characteristics: TL071I, TL072I, TL074I

6.22 Electrical Characteristics: TL071M, TL072M

6.23 Electrical Characteristics: TL074M

6.24 Switching Characteristics: TL07xM

6.25 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI

6.26 Typical Characteristics: TL07xH

6.27 Typical Characteristics: All Devices Except TL07xH

7 Parameter Measurement Information

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Total Harmonic Distortion

8.3.2 Slew Rate

8.4 Device Functional Modes

9 Application and Implementation

9.1 Application Information

9.2 Typical Application

9.2.1 Design Requirements

9.2.2 Detailed Design Procedure

9.2.3 Application Curve

9.3 Unity Gain Buffer

9.3.1 Design Requirements

9.3.2 Detailed Design Procedure

9.3.3 Application Curves

9.4 System Examples

10 Power Supply Recommendations

11 Layout

11.1 Layout Guidelines

11.2 Layout Example

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

12.2 Support Resources

12.3 Trademarks

12.4 Electrostatic Discharge Caution

12.5 Glossary

13 Mechanical, Packaging, and Orderable Information