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TL05xA

Datasheet TL 05 x, TL 05 x A Datasheet (Texas Instruments)

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Page 1
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D
Direct Upgrades to TL07x and TL08x BiFET Operational Amplifiers
D
Faster Slew Rate (20 V/µs Typ) Without Increased Power Consumption
TL051
D OR P PACKAGE
(TOP VIEW)
D
TL052
D, P, OR PS PACKAGE
(TOP VIEW)
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
On-Chip Offset-Voltage Trimming for Improved DC Performance and Precision Grades Are Available (1.5 mV, TL051A)
D, DB, N, OR NS PACKAGE
TL054
(TOP VIEW)
OFFSET N1
IN–
IN+
V
CC–
1 2 3 4
NC
8
V
7
CC+
OUT
6
OFFSET N2
5
1OUT
1IN– 1IN+
V
CC–
1 2 3 4
8 7 6 5
V
CC+
2OUT 2IN– 2IN+
1OUT
1IN– 1IN+
V
CC+
2IN+ 2IN–
2OUT
1 2 3 4 5 6 7
14 13 12 11 10
9 8
4OUT 4IN– 4IN+ V 3IN+ 3IN– 3OUT
description/ordering information
The TL05x series of JFET-input operational amplifiers of fers improved dc and ac characteristics over the TL07x and TL08x families of BiFET operational amplifiers. On-chip Zener trimming of offset voltage yields precision grades as low as 1.5 mV (TL051A) for greater accuracy in dc-coupled applications. T exas Instruments improved BiFET process and optimized designs also yield improved bandwidth and slew rate without increased power consumption. The TL05x devices are pin-compatible with the TL07x and TL08x and can be used to upgrade existing circuits or for optimal performance in new designs.
BiFET operational amplifiers offer the inherently higher input impedance of the JFET -input transistors, without sacrificing the output drive associated with bipolar amplifiers. This makes them better suited for interfacing with high-impedance sensors or very low-level ac signals. They also feature inherently better ac response than bipolar or CMOS devices having comparable power consumption.
The TL05x family was designed to offer higher precision and better ac response than the TL08x, with the low noise floor of the TL07x. Designers requiring significantly faster ac response or ensured lower noise should consider the Excalibur TLE208x and TLE207x families of BiFET operational amplifiers.
CC–
Because BiFET operational amplifiers are designed for use with dual power supplies, care must be taken to observe common-mode input voltage limits and output swing when operating from a single supply . DC biasing of the input signal is required, and loads should be terminated to a virtual-ground node at mid-supply. Texas Instruments TLE2426 integrated virtual ground generator is useful when operating BiFET amplifiers from single supplies.
The TL05x are fully specified at ±15 V and ±5 V. For operation in low-voltage and/or single-supply systems, Texas Instruments LinCMOS families of operational amplifiers (TLC-prefix) are recommended. When moving from BiFET to CMOS amplifiers, particular attention should be paid to the slew rate and bandwidth requirements, and also the output loading.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
1
Page 2
TL05x, TL05xA
PDIP (P)
Tube of 50
052AC
PDIP (P)
Tube of 50
TL051C
0°C to 70°C
SOIC (D)
TL052C
TL054C
4 mV
SOIC (D)
TL054C
SOIC (D)
052AI
PDIP (P)
Tube of 50
40°C to 85°C
1.5 mV
TL052I
TL054AI
SOIC (D)
TL054I
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
ORDERING INFORMATION
T
A
–
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
VIOmax AT 25°C
800 µV
1.5 mV
800 µV
4 mV
PACKAGE
SOIC (D)
PDIP (N) Tube of 25 TL054ACN TL054ACN
SOP (PS) Reel of 2000 TL052CPSR TL052 SSOP (DB) Reel of 2000 TL054CDBR TL054 PDIP (N) Tube of 25 TL054CN TL054CN
SOP (NS) Reel of 2000 TL054CNSR TL054 PDIP (P) Tube of 50 TL052AIP TL052AI
PDIP (N) Tube of 25 TL054AIN TL054AIN
SOIC (D)
PDIP (N) Tube of 25 TL054IN TL054IN
†
Tube of 75 TL051ACD 051AC Tube of 75 TL052ACD Reel of 2500 TL052ACDR
Tube of 75 TL051CD Reel of 2500 TL051CDR Tube of 75 TL052CD Reel of 2500 TL052CDR Tube of 50 TL054ACD Reel of 2500 TL054ACDR
Tube of 50 TL054CD Reel of 2500 TL054CDR
Tube of 75 TL052AID Reel of 2500 TL052AIDR
Tube of 75 TL051ID TL051I Tube of 75 TL052ID Reel of 2500 TL052IDR Tube of 50 TL054AID Reel of 2500 TL054AIDR
Tube of 50 TL054ID Reel of 2500 TL054IDR
ORDERABLE
PART NUMBER
TL051ACP TL051ACP TL052ACP TL052ACP
TL051CP TL051CP TL052CP TL052CP
TL051IP TL051IP TL052IP TL052IP
TOP-SIDE MARKING
2
Page 3
T
symbol (each amplifier)
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
IN–
IN+
equivalent schematic (each amplifier)
Q2
Q3
IN+ IN–
JF1 JF2
Q4
Q1
See Note A
OFFSET N1 OFFSET N2
R1
R2 R3
Q5
–
+
Q6
Q7
D1
C1
R4
OUT
Q8
V
CC+
R5
R6
Q10
Q11
Q9
Q12
R8
Q13
R7
R9
Q14
R10 D2
Q17
Q15
Q16
JF3
OU
NOTE A: OFFSET N1 and OFFSET N2 are available only on the TL051x.
ACTUAL DEVICE COMPONENT COUNT
COMPONENT TL051 TL052 TL054
Transistors 20 34 62 Resistors 10 19 37 Diodes 2 3 5 Capacitors 1 2 4
†
These figures include all four amplifiers and all ESD, bias, and trim circuitry.
V
CC–
†
3
Page 4
TL05x, TL05xA
UNIT
VICCommon-mode input voltage
V
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V Supply voltage, V
Differential input voltage (see Note 2) ±30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V Input current, I
I
Output current, I Total current into V Total current out of V
Duration of short-circuit current at (or below) 25°C Unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Operating virtual junction temperature, T
Lead temperature 1,6 mm (1/16inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V
2. Differential voltages are at IN+ with respect to IN–.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. Maximum power dissipation is a function of TJ(max), ambient temperature is PD = (TJ(max) – TA)/
5. The package thermal impedance is calculated in accordance with JESD 51-7.
(see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC+
(see Note 1) –18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC–
(any input, see Notes 1 and 3) ±15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(each input) ±1 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(each output) ±80 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
160 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC+
160 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC–
(see Notes 4 and 5): D package (8 pin) 97°C/W. . . . . . . . . . . . . . . . . . . . . .
JA
D package (14 pin) 86°C/W. . . . . . . . . . . . . . . . . . . . .
DB package (14 pin) 96°C/W. . . . . . . . . . . . . . . . . . .
N package (14 pin) 80°C/W. . . . . . . . . . . . . . . . . . . . .
NS package (14 pin) 76°C/W. . . . . . . . . . . . . . . . . . .
P package (8 pin) 85°C/W. . . . . . . . . . . . . . . . . . . . . .
PS package (8 pin) 95°C/W. . . . . . . . . . . . . . . . . . . .
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J
and V
CC+
θ
, and TA. The maximum allowable power dissipation at any allowable
θ
JA
JA
. Operating at the absolute maximum TJ of 150°C can impact reliability.
CC–.
†
recommended operating conditions
V
T
CC±
A
Supply voltage ±5 ±15 ±5 ±15 V
p
Operating free-air temperature 0 70 –40 85 °C
C SUFFIX I SUFFIX MIN MAX MIN MAX
V
= ±5 V –1 4 –1 4
CC±
V
= ±15 V –11 11 –11 11
CC±
4
Page 5
†
TL051C
VIOInput offset voltage
mV
TL051AC
V
0
a
R
S
Ω
V/°C
IIOInput offset current
OIC
IIBInput bias current
OIC
V
V
R
10 kΩ
V
V
R
2 kΩ
R
10 kΩ
V
g
V
R
2 kΩ
L
diff
l
voltage am lification
C
V
V
i
rejection ratio
V
O
R
S
Ω
S
ratio (∆V
CC±
/∆VIO)
CCyO
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051C and TL051AC electrical characteristics at specified free-air temperature
TL051C, TL051AC
PARAMETER TEST CONDITIONS
p
,
=
O
Temperature coefficient
V
IO
of input offset voltage
Input offset-voltage long-term drift
p
p
ICR
OM+
OM–
A
VD
r
i
c
i
CMRR
k
SVR
I
CC
†
Full range is 0°C to 70°C.
‡
This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
§
Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV .
For V
Common-mode input voltage range
Maximum positive peak output voltage swing
Maximum negative peak output voltage swing
arge-signal
Input resistance 25°C 10 Input capacitance 25°C 10 12 pF
ommon-mode
upply-voltage rejection
Supply current VO = 0, No load
= ±5 V, VO = ±2.3 V, or for V
CC±
p
‡
§
erentia
VIC = 0, R
= 50 Ω
= 50
VO = 0, VIC = 0, See Figure 5
VO = 0, VIC = 0, See Figure 5
=
L
=
L
=
L
=
L
RL = 2 kΩ
=
IC
= 0,
VO = 0, RS = 50 Ω
= ±15 V, VO = ±10 V.
CC±
ICR
TL051C
TL051AC
n,
m
= 50
T
A
25°C 0.75 3.5 0.59 1.5
Full range 4.5 2.5
25°C 0.55 2.8 0.35 0.8
Full range 3.8 1.8
25°C to
70°C
25°C to
70°C
25°C 0.04 0.04 µV/mo 25°C 4 100 5 100 pA
70°C 0.02 1 0.025 1 nA 25°C 20 200 30 200 pA 70°C 0.15 4 0.2 4 nA
25°C
Full range
25°C 3 4.2 13 13.9
Full range 3 13
25°C 2.5 3.8 11.5 12.7
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
Full range –2.5 –12
25°C –2.3 –3.2 –11 –12
Full range –2.3 –11
25°C 25 59 50 105
0°C 30 65 60 129
70°C 20 46 30 85
25°C 65 85 75 93
0°C 65 84 75 92 70°C 65 84 75 91 25°C 75 99 75 99
0°C 75 98 75 98 70°C 75 97 75 97 25°C 2.6 3.2 2.7 3.2
0°C 2.7 3.2 2.8 3.2 70°C 2.6 3.2 2.7 3.2
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
8 8
8 8 25
–1
–2.3
to
to
4
5.6
–1
to 4
12
–11
–11
to
11
to
11
CC±
= ±15 V
–12.3
to
15.6
12
10
UNIT
µ
V/mV
Ω
dB
dB
mA
°
5
Page 6
TL05x, TL05xA
†
Positi
L
,
L
,
V/µs
N
ns
C
L
100 F
g
V
q V/√H
C
L
See Figure 4
Ph
V
10 mV,R
2 kΩ
gain
C
L
See Figure 4
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051C and TL051AC operating characteristics at specified free-air temperature
TL051C, TL051AC
PARAMETER TEST CONDITIONS
SR+
SR–
t
r
t
f
n
V
N(PP)
I
n
THD
B
1
φ
m
†
Full range is 0°C to 70°C.
‡
For V
CC±
§
This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
For V
CC±
ve slew rate
§
‡
‡
= ±1 V; for V
I(PP)
O(RMS)
= 1 V; for V
at unity gain
egative slew rate
at unity gain
Rise time
Fall time
Overshoot factor
Equivalent input noise voltage
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
Total harmonic distortion
Unity-gain bandwidth
ase margin at unity
= ±5 V, V
= ±5 V, V
R
= 2 kΩ,C
See Figure 1
V
= ±10 mV ,
I(PP)
RL = 2 kΩ,
See Figures 1 and 2
RS = 20 Ω, See Figure 3
f = 1 kHz 25°C 0.01 0.01 RS = 1 kΩ,
f = 1 kHz
VI = 10 mV, RL = 2 kΩ,
I
CC±
=
= 25 F,
=
= 25 F,
=
= ±15 V, V
= ±15 V, V
CC±
p
p
p
= 100 pF,
,
f = 10 Hz 25°C 75 75 f = 1 kHz 25°C 18 18 30 f = 10 Hz to
10 kHz
RL = 2 kΩ,
=
L
= ±5 V.
I(PP)
= 6 V.
O(RMS)
T
A
25°C 16 13 20
Full
range
25°C 15 13 18
Full
range
25°C 55 56
0°C 54 55 70°C 63 63 25°C 55 57
0°C 54 56 70°C 62 64 25°C 24 19
0°C 24 19 70°C 24 19
25°C 4 4 µV
25°C 0.003 0.003 % 25°C 3 3.1
0°C 3.2 3.3 70°C 2.7 2.8 25°C 59 62
,
0°C 58 62 70°C 59 62
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
16.4 11 22.6
16 11 19.3
CC±
= ±15 V
UNIT
%
n
pA/√Hz
MHz
deg
z
6
Page 7
†
A
TL051I
VIOInput offset voltage
mV
TL051AI
V
0
a
R
S
Ω
V/°C
IIOInput offset current
OIC
IIBInput bias current
OIC
V
V
R
10 kΩ
V
V
R
2 kΩ
R
10 kΩ
V
g
V
R
2 kΩ
L
diff
l
voltage am lification
,
C
V
IC
V
ICR
min,
rejection ratio
S
V
0
ratio (∆V
CC±
/∆VIO)
R
S
Ω
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051I and TL051AI electrical characteristics at specified free-air temperature
TL051I, TL051AI
PARAMETER TEST CONDITIONS
p
,
=
O
Temperature coefficient of
V
IO
input offset voltage
Input offset-voltage long-term drift
p
p
ICR
OM +
OM –
A
VD
r
i
c
i
CMRR
k
SVR
I
CC
†
Full range is –40°C to 85°C
‡
This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
§
Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV .
For V
Common-mode input voltage range
Maximum positive peak output voltage swing
Maximum negative peak output voltage swing
arge-signal
Input resistance 25°C Input capacitance 25°C 10 12 pF
ommon-mode
upply-voltage rejection
Supply current VO = 0, No load –40°C 2.4 3.2 2.6 3.2 mA
= ±5 V, VO = ±2.3 V, or for V
CC±
‡
§
erentia
p
VIC = 0, R
= 50 Ω
= 50
VO = 0, VIC = 0, See Figure 5
VO = 0, VIC = 0, See Figure 5
=
L
=
L
=
L
=
L
RL = 2 kΩ –40°C 30 74 60 145 V/mV
V
= V VO = 0, RS = 50 Ω
=
O
= 50
= ±15 V, VO = ±10 V.
CC±
TL051I
TL051AI
min
,
T
A
25°C 0.75 3.5 0.59 1.5
Full range 5.3 3.3
25°C 0.55 2.8 0.35 0.8
Full range 4.6 2.6
25°C to
85°C
25°C to
85°C
25°C 0.04 0.04 µV/mo 25°C 4 100 5 100 pA
85°C 0.06 10 0.07 10 nA 25°C 20 200 30 200 pA 85°C 0.6 20 0.7 20 nA
25°C
Full range
25°C 3 4.2 13 13.9
Full range 3 13
25°C 2.5 3.8 11.5 12.7
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
Full range –2.5 –12
25°C –2.3 –3.2 –11 –12
Full range –2.3 –11
25°C 25 59 50 105
85°C 20 43 30 76
25°C 65 85 75 93
–40°C 65 83 75 90 dB
85°C 65 84 75 93 25°C 75 99 75 99
–40°C 75 98 75 98 dB
85°C 75 99 75 99 25°C 2.6 3.2 2.7 3.2
85°C 2.5 3.2 2.6 3.2
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
7 8
8 8 25
–1
–2.3
to
to
4
5.6
–1
to
4
12
10
–11
–11
to
11
to
11
CC±
= ±15 V
–12.3
to
15.6
12
10
UNIT
µ
Ω
°
7
Page 8
TL05x, TL05xA
†
Positi
L
,
L
,
V/µs
N
ns
()
C
L
100 F
g
g
V
q V/√H
C
L
See Figure 4
Ph
V
10 mV,R
2 kΩ
gain
C
L
See Figure 4
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL051I and TL051AI operating characteristics at specified free-air temperature
TL051I, TL051AI
PARAMETER TEST CONDITIONS
SR+
SR–
t
r
t
f
n
V
N(PP)
I
n
THD Total harmonic distortion
B
1
φ
m
†
Full range is –40°C to 85°C.
‡
For V
CC±
§
This parameter is tested on a sample basis for the TL051A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
For V
CC±
ve slew rate
§
‡
‡
= ±1 V; for V
I(PP)
O(RMS)
= 1 V; for V
at unity gain
egative slew rate
at unity gain
Rise time
Fall time
Overshoot factor
Equivalent input noise voltage
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
Unity-gain bandwidth
ase margin at unity
= ±5 V, V
= ±5 V, V
R
= 2 kΩ,C
See Figure 1
V
= ±10 mV ,
I(PP)
RL = 2 kΩ,
See Fi
RS = 20 Ω, See Figure 3
f = 1 kHz 25°C 0.01 0.01 pA/√Hz RS = 1 kΩ,
f = 1 kHz
VI = 10 mV, RL = 2 kΩ,
I
CC±
=
= 25 F,
=
= 25 F,
=
= ±15 V, V
= ±15 V, V
CC±
p
ures 1 and 2
p
p
= 100 pF,
,
f = 10 Hz 25°C 75 75 f = 1 kHz 25°C 18 18 30 f = 10 Hz to
10 kHz
RL = 2 kΩ,
=
L
= ±5 V.
I(PP)
= 6 V.
O(RMS)
T
A
25°C 16 13 20
Full
range
25°C 15 13 18
Full
range
25°C 55 56
–40°C 52 53
85°C 64 65 25°C 55 57
–40°C 51 53
85°C 64 65 25°C 24 19
–40°C 24 19
85°C 24 19
25°C 4 4 µV
25°C 0.003 0.003 % 25°C 3 3.1
–40°C 3.5 3.6
85°C 2.6 2.7 25°C 59 62
,
–40°C 58 61
85°C 59 62
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
11
11
CC±
= ±15 V
UNIT
%
n
MHz
deg
z
8
Page 9
A
TL052C
VIOInput offset voltage
mV
TL052AC
V
IC
R
S
Ω
TL052C
8
8
a
V/°C
TL052AC
8625
IIOInput offset current
O
,
V
0
IIBInput bias current
O
,
V
0
V
V
R
10 kΩ
V
V
R
2 kΩ
R
10 kΩ
V
g
V
R
2 kΩ
voltage am lification
C
V
V
i
rejection ratio
V
O
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL052C and TL052AC electrical characteristics at specified free-air temperature
TL052C, TL052AC
PARAMETER TEST CONDITIONS
p
VO = 0,
= 0,
= 50 Ω
50
R
Temperature coefficient
V
IO
of input offset voltage
Input offset-voltage long-term drift
p
p
Common-mode input
ICR
voltage range
Maximum positive peak
OM+
output voltage swing
Maximum negative peak
OM–
output voltage swing
A
r
i
c
CMRR
†
Full range is 0°C to 70°C.
‡
This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
§
Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV .
For V
Large-signal differential
VD
Input resistance 25°C Input capacitance 25°C 10 12 pF
i
ommon-mode
= ±5 V, VO = ±2.3 V; at V
CC±
p
‡
§
VO = 0, RS = 50 Ω
V
= 0,
See Figure 5 V
= 0,
See Figure 5
=
L
=
L
=
L
=
L
RL = 2 kΩ
=
IC
ICR
= 0,
=
= ±15 V, VO = ±10 V.
CC±
VIC = 0, 25°C 0.04 0.04 µV/mo
,
=
IC
,
=
IC
n,
m
RS = 50 Ω
†
T
A
25°C 0.73 3.5 0.65 1.5
Full range 4.5 2.5
25°C 0.51 2.8 0.4 0.8
Full range 3.8 1.8
25°C to
70°C
25°C to
70°C
25°C 4 100 5 100 pA 70°C 0.02 1 0.025 1 nA 25°C 20 200 30 200 pA 70°C
25°C
Full range
25°C 3 4.2 13 13.9
Full range 3 13
25°C 2.5 3.8 11.5 12.7
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
Full range –2.5 –12
25°C –2.3 –3.2 –11 –12
Full range –2.3 –11
25°C 25 59 50 105
0°C 30 65 60 129
70°C 20 46 30 85
25°C 65 85 75 93
0°C
70°C 65 84 75 91
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
0.15 4 0.2 4 nA
–1
–2.3
to
to
4
5.6
–1
to
4
12
10
65 84 75 92
–11
–11
to
11
to
11
CC±
= ±15 V
–12.3
to
15.6
12
10
UNIT
µ
V/mV
Ω
dB
9
Page 10
TL05x, TL05xA
A
ratio (∆V
CC±
/∆VIO)
(two am lifiers)
A
SR+Slew rate at unity gain
V/µs
SR
g
ns
()
C
L
100 F
g
g
V
q V/√H
C
L
See Figure 4
Ph
V
10 mV
R
2 kΩ
gain
C
L
See Figure 4
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL052C and TL052AC electrical characteristics at specified free-air temperature (continued)
TL052C, TL052AC
k
SVR
I
CC
VO1/V
PARAMETER TEST CONDITIONS
Supply-voltage rejection
Supply current
p
Crosstalk attenuation AVD = 100 25°C 120 120 dB
O2
VO = 0, RS = 50 Ω
VO = 0, No load
T
A
25°C 75 99 75 99
0°C 70°C 75 97 75 97 25°C 4.6 5.6 4.8 5.6
0°C 70°C 4.4 6.4 4.6 6.4
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
75 98 75 98
4.7 6.4 4.8 6.4
CC±
= ±15 V
TL052C and TL052AC operating characteristics at specified free-air temperature
TL052C, TL052AC
PARAMETER TEST CONDITIONS
RL = 2 kΩ, CL = 100 pF,
Negative slew rate
–
at unity gain
t
r
t
f
V
I
n
THD Total harmonic distortion
B
φ
†
Full range is 0°C to 70°C.
‡
For V
§
This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
For V
Rise time
Fall time
Overshoot factor
Equivalent input noise
n
voltage Peak-to-peak equivalent
N(PP)
input noise current Equivalent input
noise current
Unity-gain bandwidth
1
m
ase margin at unity
= ±5 V, V
CC±
= ±5 V, V
CC±
§
‡
= ±1 V; for V
I(PP)
O(RMS)
= 1 V; for V
See Figure 1
V
= ±10 mV ,
I(PP)
RL = 2 kΩ,
See Fi
RS = 20 Ω, See Figure 3
f = 1 kHz 25°C 0.01 0.01 pA/√Hz RS = 1 kΩ,
f = 1 kHz
VI = 10 mV,
CC±
=
= 25 F,
=
I
= 25 F,
=
= ±15 V, V
= ±15 V, V
CC±
p
,
ures 1 and 2
f = 10 Hz 25°C 71 71 f = 1 kHz 25°C 19 19 30 f = 10 Hz to
10 kHz
RL = 2 kΩ,
RL = 2 kΩ,
p
,
p
I(PP)
=
L
= ±5 V.
O(RMS)
,
= 6 V.
†
T
A
25°C 17.8 9 20.7
Full range
25°C 15.4 9 17.8
Full range 8
25°C 55 56
0°C 54 55 70°C 63 63 25°C 55 57
0°C 54 56 70°C 62 64 25°C 24 19
0°C 24 19 70°C 24 19
25°C 4 4 µV
25°C 0.003 0.003 % 25°C 3 3
0°C 3.2 3.2 70°C 2.6 2.7 25°C 60 63
0°C 59 63 70°C 60 63
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
CC±
8
= ±15 V
UNIT
dB
mA
UNIT
%
n
MHz
deg
z
10
Page 11
A
TL052I
VIOInput offset voltage
mV
V
0
TL052AI
V
IC
a
T
fficient
‡
V/°C
IIOInput offset current
O
,
IC
,
IIBInput bias current
O
,
IC
,
V
V
R
10 kΩ
V
V
R
2 kΩ
R
10 kΩ
V
g
V
R
2 kΩ
voltage am lification
C
V
V
i
rejection ratio
V
O
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL052I and TL052AI electrical characteristics at specified free-air temperature
TL052I, TL052AI
PARAMETER TEST CONDITIONS
p
,
=
O
=
= 0,
RS = 50 Ω
emperature coe
V
IO
Input offset-voltage long-term drift
p
p
Common-mode input
ICR
voltage range
Maximum positive peak
OM+
output voltage swing
Maximum negative peak
OM–
output voltage swing
A
r c
CMRR
† ‡
§
Large-signal differential
VD
Input resistance 25°C 10
i
Input capacitance 25°C 10 12 pF
i
ommon-mode
Full range is –40°C to 85°C. This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV . At V
= ±5 V, VO = ±2.3 V; at V
CC±
§
p
VO = 0, RS = 50 Ω
V
= 0, V
See Figure 5 V
= 0, V
See Figure 5
=
L
=
L
=
L
=
L
RL = 2 kΩ
=
IC
ICR
= 0,
=
= ±15 V, VO = ±10 V.
CC±
TL052I
TL052AI
VIC = 0, 25°C 0.04 0.04 µV/mo
= 0,
= 0,
n,
m
RS = 50 Ω
†
T
A
25°C 0.73 3.5 0.65 1.5
Full range 5.3 3.3
25°C 0.51 2.8 0.4 0.8
Full range 4.6 2.6
25°C to
85°C
25°C to
85°C
25°C 4 100 5 100 pA 85°C 0.06 10 0.07 10 nA 25°C 20 200 30 200 pA 85°C 0.6 20 0.7 20 nA
25°C
Full range
25°C 3 4.2 13 13.9
Full range 3 13
25°C 2.5 3.8 11.5 12.7
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
Full range –2.5 –12
25°C –2.3 –3.2 –11 –12
Full range –2.3 –11
25°C 25 59 50 105
–40°C 30 74 60 145
85°C 20 43 30 76
25°C 65 85 75 93
–40°C 65 83 75 90
85°C 65 84 75 93
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
7 6
6 6 25
–1
–2.3
to
to
4
5.6
–1
to
4
12
–11
–11
to
11
to
11
CC±
= ±15 V
–12.3
to
15.6
12
10
UNIT
µ
V/mV
Ω
dB
11
Page 12
TL05x, TL05xA
A
ratio (∆V
CC±
/∆VIO)
(two am lifiers)
A
SR
Sl
‡
L
,
L
,
V/µs
SR
g
ns
V
I(PP)
±10 mV
V
q V/√H
C
L
See Figure 4
Ph
V
10 mV
R
2 kΩ
gain
C
L
See Figure 4
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL052I and TL052AI electrical characteristics at specified free-air temperature (continued)
TL052I, TL052AI
k
SVR
I
CC
VO1/V
PARAMETER TEST CONDITIONS
Supply-voltage rejection
Supply current
p
Crosstalk attenuation AVD = 100 25°C 120 120 dB
O2
VO = 0, RS = 50 Ω
VO = 0, No load
T
A
25°C 75 99 75 99
–40°C
85°C 75 99 75 99 25°C 4.6 5.6 4.8 5.6
–40°C
85°C 4.4 6.4 4.6 6.4
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
75 98 75 98
4.5 6.4 4.7 6.4
CC±
= ±15 V
TL052I and TL052AI operating characteristics at specified free-air temperature
TL052I, TL052AI
PARAMETER TEST CONDITIONS
+
ew rate at unity gain
Negative slew rate at
–
unity gain
t
r
t
f
V
I
n
THD Total harmonic distortion
B
φ
†
Full range is –40°C to 85°C.
‡
For V
§
This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
For V
Rise time
Fall time
Overshoot factor
Equivalent input noise
n
voltage Peak-to-peak equivalent
N(PP)
input noise current Equivalent input noise
current
Unity-gain bandwidth
1
m
CC±
CC±
‡
§
ase margin at unity
= ±5 V, V
= ±5 V, V
= ±1 V; for V
I(PP)
O(RMS)
= 1 V; for V
R
= 2 kΩ, C
See Figure 1
=
= RL = 2 kΩ, CL = 100 pF, See Figures 1 and 2
RS = 20 Ω, See Figure 3
f = 1 kHz 25°C 0.01 0.01 pA/√Hz RS = 1 kΩ,
f = 1 kHz
VI = 10 mV,
= 25 F,
p
=
I
= 25 F,
=
p
= ±15 V, V
CC±
= ±15 V, V
CC±
= 100 pF,
,
f = 10 Hz 25°C 71 71 f = 1 kHz 25°C 19 19 30 f = 10 Hz to
10 kHz
RL = 2 kΩ,
RL = 2 kΩ,
,
I(PP)
=
L
O(RMS)
,
= ±5 V.
= 6 V.
†
T
A
25°C 17.8 9 20.7
Full range 8
25°C 15.4 9 17.8
Full range 8
25°C 55 56
–40°C 52 53
85°C 64 65 25°C 55 57
–40°C 51 53
85°C 64 65 25°C 24% 19%
–40°C 24% 19%
85°C 24% 19
25°C 4 4 µV
25°C 0.003 0.003 % 25°C 3 3
–40°C 3.5 3.6
85°C 2.5 2.6 25°C 60 63
–40°C 58 61
85°C 60 63
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
CC±
= ±15 V
UNIT
dB
mA
UNIT
%
n
MHz
deg
z
12
Page 13
†
TL054C
VIOInput offset voltage
mV
TL054AC
V
O
a
R
S
Ω
V/°C
IIOInput offset current
OIC
IIBInput bias current
OIC
V
V
R
10 kΩ
V
V
R
2 kΩ
R
10 kΩ
V
g
V
R
2 kΩ
L
diff
l
voltage am lification
§
C
V
V
i
rejection ratio
V
O
R
S
Ω
S
V
±5 V to ±15 V
ratio (∆V
CC±
/∆VIO)
V
O
R
S
Ω
S
t
(four am lifiers)
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054C and TL054AC electrical characteristics at specified free-air temperature
TL054C, TL054AC
PARAMETER TEST CONDITIONS
p
= 0,
V
IO
ICR
OM+
OM–
A
VD
r
i
c
i
CMRR
k
SVR
I
CC
VO1/V
†
Full range is 0°C to 70°C.
‡
Typical values are based on the input offset-voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV .
§
For V
Temperature coefficient of input offset voltage
Input offset-voltage long-term drift
p
p
Common-mode input voltage range
Maximum positive peak output voltage swing
Maximum negative peak output voltage swing
arge-signal
Input resistance 25°C Input capacitance 25°C 10 12 pF
ommon-mode
upply-voltage rejection
upply curren
Crosstalk attenuation AVD = 100 25°C 120 120 dB
O2
= ±5 V, VO = ±2.3 V, at V
CC±
‡
erentia
p
p
VIC = 0,
= 50 Ω
50
R
VO = 0, VIC = 0, See Figure 5
VO = 0, VIC = 0, See Figure 5
=
L
=
L
=
L
=
L
RL = 2 kΩ 0°C 30 88 60 173 V/mV
=
IC
= 0,
CC±
= 0,
VO = 0, No load 0°C 8.2 12.8 8.5 12.8 mA
= ±15 V, VO = ±10 V.B
CC±
=
ICR
TL054C
TL054AC
n,
m
= 50
= 50
T
A
25°C 0.64 5.5 0.56 4
Full range 7.7 6.2
25°C 0.57 3.5 0.5 1.5
Full range 5.7 3.7
25°C to
70°C
25°C to
70°C 25°C 0.04 0.04 µV/mo 25°C 4 100 5 100 pA
70°C 0.02 1 0.025 1 nA 25°C 20 200 30 200 pA 70°C 0.15 4 0.2 4 nA
25°C
Full range
25°C 3 4.2 13 13.9
Full range 3 13
25°C 2.5 3.8 11.5 12.7
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
Full range –2.5 –12
25°C –2.3 –3.2 –11 –12
Full range –2.3 –11
25°C 25 72 50 133
70°C 20 57 30 85
25°C 65 84 75 92
0°C 65 84 75 92 dB 70°C 65 84 75 93 25°C 75 99 75 99
,
0°C 75 99 75 99 dB 70°C 75 99 75 99 25°C 8.1 11.2 8.4 11.2
70°C 7.9 11.2 8.2 11.2
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
25 23
24 23
–1
–2.3
to
–1
to
to
4
5.6
4
12
10
–11
–11
11
11
to
to
CC±
= ±15 V
–12.3
to
15.6
12
10
UNIT
µ
Ω
°
13
Page 14
TL05x, TL05xA
†
SR
L L
V/µs
SR
g
ns
R
2 kΩ
C
L
100 F
g
See Figures 1 and 2
V
q
nV/√Hz
V
10 mV,R
2 kΩ
C
L
See Figure 4
Phase margin at
V
10 mV,R
2 kΩ
unity gain
C
L
See Figure 4
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054C and TL054AC operating characteristics at specified free-air temperature
TL054C, TL054C
PARAMETER TEST CONDITIONS
Positive slew rate
+
at unity gain
RL = 2 kΩ,CL = 100 pF,
Negative slew rate at
–
unity gain
t
r
t
f
n
V
N(PP)
I
n
THD
B
1
φ
m
†
Full range is 0°C to 70°C.
‡
For V
§
This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
For V
Rise time 0°C 54 55
Fall time
Overshoot factor 0°C 24% 19%
Equivalent input noise voltage
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
Total harmonic distortion
Unity-gain bandwidth
= ±5 V, V
CC±
= ±5 V, V
CC±
‡
§
= ±1 V; for V
I(PP)
O(RMS
) = 1 V; for V
See Figure 1 and Note 7
V
= ±10 mV ,
I(PP)
See Fi
RS = 20 Ω, See Figure 3
f = 1 kHz 25°C 0.01 0.01 RS = 1 kΩ,
f = 1 kHz
I
I
CC±
=
L
=
=
= 25 F,
=
= 25 F,
=
= ±15 V, V
CC±
,
p
,
ures 1 and 2
f = 10 Hz 25°C 75 75 f = 1 kHz 25°C 21 21 45 f = 10 Hz to
10 kHz
RL = 2 kΩ,
=
p
p
= ±15 V, V
L
=
L
I(PP)
O(RMS)
= ±5 V.
T
A
25°C 15.4 10 17.8
0°C 15.7 8 17.9
70°C 14.4 8 17.5
25°C 13.9 10 15.9
0°C 14.3 8 16.1
70°C 13.3 8 15.5
25°C 55 56
70°C 63 63 25°C 55 57
0°C 54 56 70°C 62 64 25°C 24% 19%
70°C 24% 19
25°C 4 4 µV
25°C 0.003 0.003 % 25°C 2.7 2.7
,
0°C 3 3 MHz 70°C 2.4 2.4 25°C 61 64
,
0°C 60 64 deg 70°C 61 63
= 6 V.
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
CC±
= ±15 V
UNIT
%
pA/√Hz
14
Page 15
†
A
TL054I
VIOIn ut offset voltage
mV
TL054AI
V
O
R
S
Ω
V/°C
IIOInput offset current
OIC
IIBInput bias current
OIC
V
V
R
10 kΩ
V
V
R
2 kΩ
R
10 kΩ
V
g
V
R
2 kΩ
L
diff
l
voltage am lification
§
C
V
V
i
rejection ratio
V
O
R
S
Ω
S
V
±5 V to ±15 V
ratio (∆V
CC±
/∆VIO)
V
O
R
S
Ω
S
t
(four am lifiers)
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054I and TL054AI electrical characteristics at specified free-air temperature
TL054I, TL054AI
PARAMETER TEST CONDITIONS
p
= 0,
a
V
IO
ICR
OM+
OM–
A
VD
r
i
c
i
CMRR
k
SVR
I
CC
VO1/V
†
Full range is –40°C to 85°C.
‡
Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C, extrapolated to TA = 25°C using the Arrhenius equation, and assuming an activation energy of 0.96 eV .
§
For V
Temperature coefficient of input offset voltage
Input offset voltage long-term drift
p
p
Common-mode input voltage range
Maximum positive peak output voltage swing
Maximum negative peak output voltage swing
arge-signal
Input resistance 25°C Input capacitance 25°C 10 12 pF
ommon-mode
upply-voltage rejection
upply curren
Crosstalk attenuation AVD = 100 25°C 120 120 dB
O2
= ±5 V, VO = ±2.3 V, at V
CC±
‡
erentia
p
p
VIC = 0,
= 50 Ω
50
R
VO = 0, VIC = 0, See Figure 5
VO = 0, VIC = 0, See Figure 5
=
L
=
L
=
L
=
L
RL = 2 kΩ –40°C 30 101 60 212 V/mV
=
IC
= 0,
CC±
= 0,
VO = 0, No load –40°C 7.9 12.8 8.2 12.8 mA
= ±15 V, VO = ±10 V.
CC±
=
ICR
TL054I
TL054AI
n,
m
= 50
= 50
T
A
25°C
Full range 8.8 7.3
25°C 0.57 3.5 0.5 1.5
Full range 6.8 4.8
25°C to
85°C
25°C to
85°C 25°C 0.04 0.04 µV/mo 25°C 4 100 5 100 pA
85°C 0.06 10 0.07 10 nA 25°C 20 200 30 200 pA 85°C 0.6 20 0.7 20 nA
25°C
Full range
25°C 3 4.2 13 13.9
Full range 3 13
25°C 2.5 3.8 11.5 12.7
Full range 2.5 11.5
25°C –2.5 –3.5 –12 –13.2
Full range –2.5 –12
25°C –2.3 –3.2 –11 –12
Full range –2.3 –11
25°C 25 72 50 133
85°C 20 50 30 70
25°C 65 84 75 92
–40°C 65 83 75 92 dB
85°C 65 84 75 93 25°C 75 99 75 99
,
–40°C 75 98 75 99 dB
85°C 75 99 75 99 25°C 8.1 11.2 8.4 11.2
85°C 7.6 11.2 7.9 11.2
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
0.64 5.5 0.56 4
25 24
25 23
–1
–2.3
to
–1
to
to
4
5.6
4
12
10
= ±15 V UNIT
CC±
–11
–12.3
to
to
11
15.6
–11
to
11
12
10
µ
°
Ω
15
Page 16
TL05x, TL05xA
†
A
SR
L L
V/µs
SR
g
,
ns
V
I(PP)
±10 mV, R
L
kΩ,
V
q
nV/√Hz
V
10 mV,R
2 kΩ
C
L
See Figure 4
Phase margin at
V
10 mV,R
2 kΩ
unity gain
C
L
See Figure 4
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TL054I and TL054AI operating characteristics at specified free-air temperature
TL054I, TL054AI
PARAMETER TEST CONDITIONS
Positive slew rate
+
at unity gain
RL = 2 kΩ,CL = 100 pF,
Negative slew rate at
–
unity gain
t
r
t
f
n
V
N(PP)
I
n
THD
B
1
φ
m
†
Full range is –40°C to 85°C.
‡
For V
§
This parameter is tested on a sample basis. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters.
For V
Rise time –40°C 52 53
Fall time
Overshoot factor –40°C 24 19
Equivalent input noise voltage
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
Total harmonic distortion
Unity-gain bandwidth
= ±5 V, V
CC±
= ±5 V, V
CC±
‡
§
= ±1 V; for V
I(PP)
O(RMS)
= 1 V; for V
See Figure 1
= ±10 mV, R
V CL = 100 pF, See Figures 1 and 2
RS = 20 Ω, See Figure 3
f = 1 kHz 25°C 0.01 0.01 pA/√Hz RS = 1 kΩ,
f = 1 kHz
=
I
= 25 F,
p
=
I
=
p
= 25 F,
= ±15 V, V
CC±
= ±15 V, V
CC±
= 2 kΩ
2
f = 10 Hz 25°C 75 75 f = 1 kHz 25°C 21 21 45 f = 10 Hz to
10 kHz
RL = 2 kΩ,
=
L
=
L
= ±5 V.
I(PP)
O(RMS)
T
A
25°C 15.4 10 17.8
–40°C 16.4 8 18
85°C 14 8 17.3 25°C 13.9 10 15.9
–40°C 14.7 8 16.1
85°C 13 8 15.3 25°C 55 56
85°C 64 65 25°C 55 57
–40°C 51 53
85°C 64 65 25°C 24 19
85°C 24 19
25°C 4 4 µV
25°C 0.003% 0.003% % 25°C 2.7 2.7
,
–40°C 3.3 3.3 MHz
85°C 2.3 2.4 25°C 61 64
,
–40°C 59 62 deg
85°C 61 64
= 6 V.
V
= ±5 V V
CC±
MIN TYP MAX MIN TYP MAX
= ±15 V UNIT
CC±
%
16
Page 17
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
PARAMETER MEASUREMENT INFORMATION
V
CC+
–
V
NOTE A: CL includes fixture capacitance.
+
I
V
CC–
(see Note A)
C
L
V
O
R
L
Figure 1. Slew Rate, Rise/Fall Time,
and Overshoot Test Circuit
Overshoot
90%
10%
t
r
Figure 2. Rise-Time and Overshoot
Waveform
2 kΩ
V
CC+
–
+
V
CC–
R
S
R
S
V
O
V
I
100 Ω
NOTE A: CL includes fixture capacitance.
10 kΩ
V
CC+
–
+
V
CC–
(see Note A)
C
V
L
R
L
Figure 4. Unity-Gain Bandwidth and
Figure 3. Noise-Voltage Test Circuit
typical values
Typical values, as presented in this data sheet
Phase-Margin Test Circuit
Ground Shield
V
–
+
CC+
represent the median (50% point) of device parametric performance.
pA pA
V
CC–
input bias and offset current
At the picoamp-bias-current level typical of the TL05x and TL05xA, accurate measurement of the bias current becomes difficult. Not only does this
Figure 5. Input-Bias and Offset-Current Test Circuit
measurement require a picoammeter, but test-socket leakages easily can exceed the actual device bias currents. To accurately measure these small currents, Texas Instruments uses a two-step process. The socket leakage is measured using picoammeters with bias voltages applied, but with no device in the socket. The device then is inserted in the socket, and a second test that measures both the socket leakage and the device input bias current is performed. The two measurements then are subtracted algebraically to determine the bias current of the device.
noise
Because of the increasing emphasis on low noise levels in many of today’s applications, the input noise voltage density is sample tested at f = 1 kHz. Texas Instruments also has additional noise-testing capability to meet specific application requirements. Please contact the factory for details.
O
17
Page 18
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
V
IO
a
I
IB
I
IO
V
IC
V
O
V
OM
V
O(PP)
A
VD
CMRR Common-mode rejection ratio z
o
k
SVR
I
OS
I
CC
SR Slew rate
V
n
THD Total harmonic distortion vs Frequency 63 B
1
φ
m
Input offset voltage Distribution 6–11 Temperature coefficient of input offset voltage Distribution 12, 13, 14
V
IO
Input bias current Input offset current vs Free-air temperature 16 Common-mode input voltage range limits Output voltage vs Differential input voltage 19, 20
Maximum peak output voltage
Maximum peak-to-peak output voltage vs Frequency 22, 23, 24
Large-signal differential voltage amplification
Output impedance vs Frequency 37 Supply-voltage rejection ratio vs Free-air temperature 38
Short-circuit output current
Supply current
Overshoot factor vs Load capacitance 60 Equivalent input noise voltage vs Frequency 61, 62
Unity-gain bandwidth
Phase margin
Phase shift vs Frequency 30 Voltage-follower small-signal pulse response vs Time 79 Voltage-follower large-signal pulse response vs Time 80
Table of Graphs
vs Common-mode input voltage vs Free-air temperature
vs Supply voltage vs Free-air temperature
vs Supply voltage vs Output current vs Free-air temperature
vs Load resistance vs Frequency vs Free-air temperature
vs Frequency vs Free-air temperature
vs Supply voltage vs Time vs Free-air temperature
vs Supply voltage vs Free-air temperature
vs Load resistance vs Free-air temperature
vs Supply voltage vs Free-air temperature
vs Supply voltage vs Load capacitance vs Free-air temperature
FIGURE
15 16
17 18
21 25, 26 27, 28
29
30
31, 32, 33
34, 35
36
39
40
41
42, 43, 44 45, 46, 47
48–53 54–59
64, 65, 66 67, 68, 69
70, 71, 72 73, 74, 75 76, 77, 78
18
Page 19
P
t
f
A
lifi
%
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
Percentage of Units – %
DISTRIBUTION OF TL051
INPUT OFFSET VOLTAGE
16
433 Units Tested From 1 Wafer Lot V
= ±15 V
CC±
TA = 25°C P Package
12
8
4
0
–1.5
–0.9 –0.3 0 0.3 0.9 1.5
–1.1 –0.6 0.6 1.1
VIO – Input Offset Voltage – mV
Figure 6
DISTRIBUTION OF TL052
INPUT OFFSET VOLTAGE
15
476 Amplifiers Tested From 1 Wafer Lot V
= ±15 V
CC±
TA = 25°C
12
P Package
Percentage of Units – %
DISTRIBUTION OF TL051A
INPUT OFFSET VOLTAGE
20
393 Units Tested From 1 Wafer Lot V
= ±15 V
CC±
TA = 25°C
16
P Package
12
8
4
0
–900
VIO – Input Offset Voltage – µV
Figure 7
DISTRIBUTION OF TL052A
INPUT OFFSET VOLTAGE
20
403 Amplifiers Tested From 1 Wafer Lot V
= ±15 V
CC±
TA = 25°C P Package
15
9006003000–300–600
ers –
mp
age o
ercen
9
6
3
0
–1.5
–0.9 –0.3 0 0.3 0.9 1.5
–1.2 –0.6 0.6 1.2
VIO – Input Offset Voltage – mV
Figure 8
10
5
Percentage of Amplifiers – %
0
–900 –600 –300 0 300 600 900
VIO – Input Offset Voltage – µV
Figure 9
19
Page 20
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
Percentage of Amplifiers – %
DISTRIBUTION OF TL054
INPUT OFFSET VOLTAGE
30
1140 Amplifiers Tested From 3 Wafer Lots
V
= ±15 V
CC±
25
TA = 25°C N Package
20
15
10
5
0
–4
–2013–3 –124
VIO – Input Offset Voltage – mV
Figure 10
DISTRIBUTION OF TL051
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
20
120 Units Tested From 2 Wafer Lots V
= ±15 V
CC±
TA = 25°C to 125°C
16
P Package
Percentage of Amplifiers – %
DISTRIBUTION OF TL054A
INPUT OFFSET VOLTAGE
15
1048 Amplifiers Tested From 3 Wafer Lots V
= ±15 V
CC±
TA = 25°C
12
N Package
9
6
3
0
–1.8
VIO – Input Offset Voltage – mV
Figure 11
DISTRIBUTION OF TL052
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
20
172 Amplifiers Tested From 2 Wafer Lots V
= ±15 V
CC±
TA = 25°C to 125°C P Package
15
Outlier: One Unit at –34.6 µV/°C
1.81.20.60–0.6–1.2
20
Percentage of Units – %
12
8
4
0
–20 –15 –10 –5 0 510152025
–25
a
– Temperature Coefficient – µV/°C
V
IO
Figure 12
Percentage of Amplifiers – %
10
5
0
a
– Temperature Coefficient – µV/°C
V
IO
20100–10–20–30
30
Figure 13
Page 21
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
Percentage of Amplifiers – %
50
40
30
20
10
0
–60
100
10
DISTRIBUTION OF TL054
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
324 Amplifiers Tested From 3 Wafer Lots
TA = 25°C to 125°C
–40 –20 0 20 40 60
– Temperature Coefficient – µV/°C
a
V
IO
Figure 14
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
V
= ±15 V
CC±
VO = 0 VIC = 0
I
1
IB
V
= ±15 V
CC±
N Package
†
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
10
V
= ±15 V
CC±
TA = 25°C
5
0
– Input Bias Current – nA
IB
–5
I
–10
–15
–10 –5051015
VIC – Common-Mode Input Voltage – V
Figure 15
COMMON-MODE
INPUT VOLTAGE RANGE LIMITS
vs
16
TA = 25°C
12
8
4
SUPPLY VOLTAGE
Positive Limit
I
IO
I
I
– Input Bias and Offset Currents – nA
IO
and
IB
0.1
0.01
0.001 25
45 65 85 105 125
TA – Free-Air Temperature – °C
Figure 16
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
0
Negative Limit
–4
–8
– Common-Mode Input Voltage – V
IC
–12
V
–16
2 4 6 8 10 12 14 16
0
|V
| – Supply Voltage – V
CC±
Figure 17
21
Page 22
TL05x, TL05xA
ООООО
ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
COMMON-MODE
INPUT VOLTAGE RANGE LIMITS
†
vs
20
FREE-AIR TEMPERATURE
V
= ±15 V
CC±
15
Positive Limit
10
5
0
–5
–10
– Common-Mode Input Voltage – V
IC
–15
V
–20
–50 –25 0 25 50 75 100 125
–75
TA – Free-Air Temperature – °C
Negative Limit
5
V
CC±
4
TA = 25°C
3 2
1 0
–1
RL = 600 Ω
– Output Voltage – V
O
V
RL = 1 kΩ
–2 –3 –4
–5
–200
Figure 18
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
= ±5 V
RL = 2 kΩ RL = 10 kΩ
–100 0 100 200
VID – Differential Input Voltage – µV
Figure 19
OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
15
V
= ±15 V
CC±
TA = 25°C
10
5
0
–5
– Output Voltage – V
O
V
–10
–15
–400
–200 0 200 400
VID – Differential Input Voltage – µV
RL = 600 Ω RL = 1 kΩ RL = 2 kΩ RL = 10 kΩ
– Maximum Peak Output Voltage – V
V
OM
–12
–16
Figure 20
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
16
TA = 25°C
12
RL = 10 kΩ
8
4
0
–4
–8
2 4 6 8 10 12 14 16
0
|V
CC±
RL = 10 kΩ
| – Supply Voltage – V
Figure 21
V
OM+
RL = 2 kΩ
RL = 2 kΩ
V
OM–
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
22
Page 23
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
30
RL = 2 kΩ
TA = –55°C
– Maximum Peak-to-Peak Output Voltage – V
O(PP)
V
25
20
15
10
5
0
V
10 k
= ±15 V
CC±
TA = 125°C
V
= ±5 V
CC±
100 k 1 M 10 M
f – Frequency – Hz
Figure 22
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
30
25
20
15
FREQUENCY
V
= ±15 V
CC±
RL = 10 kΩ
TA = 25°C
†
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
30
RL = 2 kΩ TA = 25°C
– Maximum Peak-to-Peak Output Voltage – V
O(PP)
V
25
20
15
10
5
0
10 k
V
CC±
V
= ±15 V
CC±
= ±5 V
100 k 1 M 10 M
f – Frequency – Hz
Figure 23
MAXIMUM PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5
4
3
V
OM+
V
= ±5 V
CC±
RL = 10 kΩ
TA = 25°C
– Maximum Peak Output Voltage – V
|
|V
OM
2
1
0
0
2 6 10 14 18
V
OM–
41216208
|IO| – Output Current – mA
Figure 25
10
V
= ±5 V
5
– Maximum Peak-to-Peak Output Voltage – V
O(PP)
0
V
10 k 100 k
CC±
1 M 10 M
f – Frequency – Hz
Figure 24
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
23
Page 24
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
– Maximum Peak Output Voltage – V
|
|V
OM
MAXIMUM PEAK OUTPUT VOLTAGE
vs
OUTPUT CURRENT
16
14
12
V
10
8
6
4
2
0
0
V
OM–
515253545
10 20 30 40 50
|IO| – Output Current – mA
OM+
Figure 26
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
16
12
8
RL = 10 kΩ
V
OM+
RL = 2 kΩ
V
= ±15 V
CC±
RL = 10 kΩ TA = 25°C
MAXIMUM PEAK OUTPUT VOLTAGE
†
vs
FREE-AIR TEMPERATURE
– Maximum Peak Output Voltage – V
V
OM
–1
–2 –3
–4 –5
5
V
OM+
4
3 2
1
0
V
OM–
–75
–50 –25 0 25 50 75 100 125
RL = 10 kΩ
RL = 2 kΩ
V
CC±
RL = 2 kΩ
RL = 10 kΩ
TA – Free-Air Temperature – °C
= ±5 V
Figure 27
†
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION
vs
LOAD RESISTANCE
250
VO = ±1 V TA = 25°C
200
V
CC±
= ±15 V
4
V
= ±15 V
CC±
0
–4
– Maximum Peak Output Voltage – V
V
OM
–8
–12
–16
V
OM–
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
RL = 2 kΩ
RL = 10 kΩ
125
Figure 28
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
24
150
100
50
– Differential Voltage Amplification – V/mV
VD
A
0
0.4
V
= ±5 V
CC±
1 4 10 40 100
RL – Load Resistance – kΩ
Figure 29
Page 25
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
10
10
10
10
6
5
4
3
FREQUENCY
A
VD
V
= ±15 V
CC±
RL = 2 kΩ CL = 25 pF
TA = 25°C
0°
30°
60°
1000
400
100
2
10
1
10
1
– Differential Voltage Amplification – V/mVA
VD
0.1 10
TL051 AND TL052
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
†
vs
FREE-AIR TEMPERATURE
V
= ±5 V
CC±
VO = ±2.3 V
RL = 10 kΩ
Phase Shift
f – Frequency – Hz
Figure 30
1000
400
100
90°
mφ – Phase Shift
120°
150°
180°
10 M100 1 k 10 k 100 k 1 M
TL054
LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
†
vs
FREE-AIR TEMPERATURE
V
= ±5 V
CC±
VO = ±2.3 V
RL = 10 kΩ
RL = 2 kΩ
40
– Differential Voltage Amplification – V/mVA
VD
10
–75
RL = 2 kΩ
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
125
Figure 31
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
40
– Differential Voltage Amplification – V/mVA
VD
10
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 32
125
25
Page 26
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
– Differential Voltage Amplification – V/mVA
VD
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION
vs
FREE-AIR TEMPERATURE
1000
400
100
40
10
–75
–50 –25 0 25 50 75 100
RL = 10 kΩ
RL = 2 kΩ
TA – Free-Air Temperature – °C
Figure 33
†
V
= ±15 V
CC±
VO = 10 V
125
CMRR – Common-Mode Rejection Ratio – dB
100
90
80
70
60
50
40
30
20 10
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
0
10
100 1 k 10 k 100 k 1 M
f – Frequency – Hz
Figure 34
V
= ±5 V
CC±
TA = 25°C
10 M
CMRR – Common-Mode Rejection Ratio – dB
100
90
80
70
60
50
40
30
20
10
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
0
10
f – Frequency – Hz
Figure 35
V
= ±15 V
CC±
TA = 25°C
1 M100 k10 k1 k100
10 M
CMRR – Common-Mode Rejection Ratio – dB
100
95
90
85
80
75
70
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
V
= ±15 V
CC±
V
= ±5 V
CC±
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 36
VIC = V
ICR
†
Min
125
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
26
Page 27
†
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
FREQUENCY
SVR
kSVR – Supply-Voltage Rejection Ratio – dB
k
110
106
102
100
40
Ω
10
4
1
– Output Impedance –
o
z
0.4
0.1 1 k
AVD = 100
AVD = 10
AVD = 1
VCC± = ±15 V TA = 25°C
ro (open loop) ≈ 250 Ω
10 k 100 k
f – Frequency – Hz
1 M
Figure 37
SHORT-CIRCUIT OUTPUT CURRENT
vs
SUPPLY VOLTAGE
60
VO = 0
TA = 25°C
40
VID = 100 mV
20
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
V
= ±5 V to ±15 V
CC±
98
94
90
–75
TA – Free-Air Temperature – °C
Figure 38
SHORT-CIRCUIT OUTPUT CURRENT
vs
TIME
60
VID = 100 mV
40
20
125–50 –25 02550 75 100
OS
IOS – Short-Circuit Output Current – mA
I
–20
–40
–60
0
VID = –100 mV
0
246 8 10 12 14
|V
| – Supply Voltage – V
CC±
16
Figure 39
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
OS
IOS – Short-Circuit Output Current – mA
I
–20
–40
–60
VID = –100 mV
V
= ±15 V
CC±
TA = 25°C
0
t – Time – s
5040302010 600
Figure 40
27
Page 28
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
OS
IOS – Short-Circuit Output Current – mA
I
60
40
20
–20
–40
–60
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
VID = 100 m V
0
VID = –100 m V
VO = 0
TA – Free-Air Temperature – °C
Figure 41
V
V
V
V
CC±
CC±
CC±
CC±
= ±15 V
= ±5 V
= ±5 V
= ±15 V
1007550250–25–50 125–75
†
SUPPLY CURRENT
TL051
†
vs
SUPPLY VOLTAGE
3
2.5 TA = 25°C
TA = –55°C TA = 125°C
VO = 0 No Load
16
CC
ICC – Supply Current – mA
I
1.5
0.5
2
1
0
0
2 4 6 8 10 12 14
|V
| – Supply Voltage – V
CC±
Figure 42
CC
ICC – Supply Current – mA
I
TL052
SUPPLY CURRENT
vs
†
SUPPLY CURRENT
SUPPLY VOLTAGE
5
4
3
2
1
0
0
2 4 6 8 10 12 14
|V
| – Supply Voltage – V
CC±
TA = 25°C
TA = –55°C
TA = 125°C
VO = 0 No Load
16
CC
ICC – Supply Current – mA
I
10
8
6
4
2
0
0
246 8 10 12 14
|V
CC±
Figure 43
TL054
†
vs
SUPPLY VOLTAGE
TA = 25°C
TA = –55°C
TA = 125°C
VO = 0 No Load
16
| – Supply Voltage – V
Figure 44
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
28
Page 29
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
CC
ICC – Supply Current – mA
I
2.5
1.5
0.5
TL051
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
3
2
1
0
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 45
†
V
V
CC± CC±
= ±15 V = ±5 V
VO = 0 No Load
125
CC
ICC – Supply Current – mA
I
TL052
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
5
4
3
2
1
0
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 46
V V
CC± CC±
†
= ±15 V = ±5 V
VO = 0 No Load
125
CC
ICC – Supply Current – mA
I
10
TL054
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
V
= ±15 V
CC±
8
6
4
2
0
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
V
CC±
= ±5 V
Figure 47
†
VO = 0 No Load
125
µs
SR – Slew Rate – V/
25
20
15
10
TL051
SLEW RATE
vs
LOAD RESISTANCE
SR+
SR–
V
= ±5 V
5
0
0.4 RL – Load Resistance – kΩ
CC±
CL = 100 pF TA = 25°C See Figure 1
100401041
Figure 48
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
29
Page 30
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL052
SLEW RATE
vs
LOAD RESISTANCE
25
SR+
20
15
10
SR – Slew Rate – V/µs
5
0
RL – Load Resistance – kΩ
SR–
10410.4
V
= ±5 V
CC±
CL = 100 pF TA = 25°C See Figure 1
40
100
µs
SR – Slew Rate – V/
25
20
15
10
5
0
0.4
LOAD RESISTANCE
RL – Load Resistance – kΩ
Figure 49
TL054
SLEW RATE
vs
Figure 50
SR+
SR–
V
CC±
CL = 100 pF TA = 25°C See Figure 1
= ±5 V
100401041
TL051
SLEW RATE
vs
LOAD RESISTANCE
30
SR+
25
SR–
20
15
10
SR – Slew Rate – V/µs
5
0
0.4
1 4 10 40 100
RL – Load Resistance – kΩ
V
= ±15 V
CC±
CL = 100 pF TA = 25°C See Figure 1
25
20
15
10
SR – Slew Rate – V/µs
5
0
LOAD RESISTANCE
1 4 10 40 1000.4
RL – Load Resistance – kΩ
Figure 51
TL052
SLEW RATE
vs
Figure 52
SR+
SR–
V
CC±
CL = 100 pF TA = 25°C
See Figure 1
= ±15 V
30
Page 31
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL054
SLEW RATE
vs
LOAD RESISTANCE
25
SR+
20
SR–
15
10
SR – Slew Rate – V/µs
5
0
0.4
1 4 10 40 100
RL – Load Resistance – kΩ
V
= ±5 V
CC±
CL = 100 pF TA = 25°C See Figure 1
30
25
20
15
10
SR – Slew Rate – V/µs
5
0
–75
FREE-AIR TEMPERATURE
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 53
TL051
SLEW RATE
vs
SR+
SR–
Figure 54
†
V
CC±
RL = 2 kΩ
= ±5 V
125
TL052
SLEW RATE
†
vs
FREE-AIR TEMPERATURE
25
20
15
10
SR – Slew Rate – V/µs
5
0
–75
TA – Free-Air Temperature – °C
SR+
SR–
V
= ±5 V
CC±
RL = 2 kΩ CL = 100 pF See Figure 1
125–50 –25 0 25 50 75 100
20
15
10
SR – Slew Rate – V/µs
5
0 –75
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Figure 55
TL054
SLEW RATE
vs
SR+
SR–
Figure 56
†
V
= ±5 V
CC±
RL = 2 kΩ CL = 100 pF See Figure 1
125–50 –25 0 25 50 75 100
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
31
Page 32
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL051
SLEW RATE
†
vs
FREE-AIR TEMPERATURE
30
25
20
15
10
SR – Slew Rate – V/µs
5
0
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
SR+
SR–
V
= ±15 V
CC±
RL = 2 kΩ CL = 100 pF See Figure 1
125
25
20
15
10
SR – Slew Rate – V/µs
5
0
–75
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Figure 57
TL052
SLEW RATE
vs
SR+
SR–
Figure 58
†
V
= ±15 V
CC±
RL = 2 kΩ CL = 100 pF See Figure 1
125–50 –25 0 25 50 75 100
TL054
SLEW RATE
†
vs
FREE-AIR TEMPERATURE
Overshoot Factor – %
50
40
30
20
10
0
0
20
SR+
SR–
15
10
SR – Slew Rate – V/µs
5
0
–75
TA – Free-Air Temperature – °C
V
= ±15 V
CC±
RL = 2 kΩ CL = 100 pF See Figure 1
125–50 –25 0 25 50 75 100
Figure 59
OVERSHOOT FACTOR
vs
LOAD CAPACITANCE
V
= ±5 V
CC±
V
= ±15 V
CC±
V
= ±10 mV
I(PP)
RL = 2 kΩ TA = 25°C See Figure 1
50 100 150 200 250
CL – Load Capacitance – pF
Figure 60
300
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
32
Page 33
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
nV/ Hz
Vn – Equivalent Input Noise Voltage –
100
70
50 40
30
20
10
TL051
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
V
CC±
RS = 20 Ω TA = 25°C See Figure 3
10
100 1 k 10 k
f – Frequency – Hz
Figure 61
= ±15 V
100 k
nV/ Hz
Vn – Equivalent Input Noise Voltage –
100
70
50 40
30
20
10
TL052 AND TL054
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
V
CC±
RS = 20 Ω TA = 25°C See Figure 3
10
100 1 k 10 k
f – Frequency – Hz
Figure 62
= ±15 V
100 k
0.004
THD – Total Harmonic Distortion – %
0.001
0.4
0.1
0.04
0.01
1
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
V
= ±15 V
CC±
AVD = 1
V TA = 25°C
100
O(RMS)
= 6 V
1 k 10 k 100 k
f – Frequency – Hz
Figure 63
3.2
3.1
2.9
– Unity-Gain Bandwidth – MHz
2.8
1
B
2.7
TL051
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
3
VI = 10 mV RL = 2 kΩ CL = 25 pF TA = 25°C See Figure 4
0
2 4 6 8 10 12 14
|V
| – Supply Voltage – V
CC±
16
Figure 64
33
Page 34
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL052
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
3.2
3.1
3
2.9
– Unity-Gain Bandwidth – MHz
2.8
1
B
2.7 4 6 8 10 12 14
|V
| – Supply Voltage – V
CC±
Figure 65
VI = 10 mV RL = 2 kΩ CL = 25 pF
TA = 25°C
See Figure 4
16
TL054
UNITY-GAIN BANDWIDTH
vs
SUPPLY VOLTAGE
2.9
2.8
2.7
2.6
– Unity-Gain Bandwidth – MHz
2.5
1
B
2.4 0 2 6 8 10 14
412
|V
| – Supply Voltage – V
CC±
Figure 66
VI = 10 mV RL = 2 kΩ CL = 25 pF
TA = 25°C
See Figure 4
16
TL051
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
4
V
= ±15 V
CC±
3
V
= ±5 V
CC±
2
VI = 10 mV
1
– Unity-Gain Bandwidth – MHzB
1
RL = 2 kΩ CL = 25 pF
See Figure 4
0
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
†
UNITY-GAIN BANDWIDTH
FREE-AIR TEMPERATURE
4
3
2
V
= ±5 V to ±15 V
CC±
VI = 10 mV RL = 2 kΩ
1
– Unity-Gain Bandwidth – MHzB
1
125
CL = 25 pF TA = 25°C See Figure 4
0
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 67
TL052
†
vs
125
Figure 68
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
34
Page 35
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
TL054
UNITY-GAIN BANDWIDTH
†
vs
FREE-AIR TEMPERATURE
4
3
2
V
= ±5 V to ±15 V
CC±
VI = 10 mV RL = 2 kΩ
1
– Unity-Gain Bandwidth – MHzB
1
CL = 25 pF TA = 25°C See Figure 4
0
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
125
65°
63°
61°
59°
m
φ – Phase Margin
57°
55°
0
2 4 6 8 10 12 14
|V
CC±
Figure 69
TL051
PHASE MARGIN
vs
SUPPLY VOLTAGE
VI = 10 mV RL = 2 kΩ CL = 25 pF
TA = 25°C See Figure 4
16
| – Supply Voltage – V
Figure 70
TL052
PHASE MARGIN
vs
SUPPLY VOLTAGE
65°
63°
61°
59°
m
φ – Phase Margin
57°
55°
46 8101214
|V
| – Supply Voltage – V
CC±
VI = 10 mV RL = 2 kΩ CL = 25 pF
TA = 25°C See Figure 4
Figure 71
16
TL054
PHASE MARGIN
vs
SUPPLY VOLTAGE
65°
63°
61°
59°
m
φ – Phase Margin
57°
55°
048101214
62
|V
| – Supply Voltage – V
CC±
VI = 10 mV RL = 2 kΩ CL = 25 pF
TA = 25°C See Figure 4
Figure 72
16
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
35
Page 36
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
70°
65°
60°
See Note A
55°
50°
m
φ – Phase Margin
45°
TL051
PHASE MARGIN
vs
LOAD CAPACITANCE
V
= ±5 V
CC±
†
VI = 10 mV RL = 2 kΩ TA = 25°C
See Figure 4
V
= ±15 V
CC±
70°
65°
60°
See Note A
55°
m
φ – Phase Margin
50°
TL052
PHASE MARGIN
vs
LOAD CAPACITANCE
V
CC±
V
= ±5 V
CC±
†
VI = 10 mV RL = 2 kΩ TA = 25°C
See Figure 4
= ±15 V
40°
0
10 20 30 40 50 60 70 80 90
CL – Load Capacitance – pF
Figure 73
70°
65°
60°
See Note A
55°
m
φ – Phase Margin
50°
45°
0
45°
0
100
10 20 30 40 50 60 70 80 90
TL054
PHASE MARGIN
†
vs
LOAD CAPACITANCE
VI = 10 mV RL = 2 kΩ TA = 25°C
See Figure 4
V
= ±15 V
CC±
V
= ±5 V
CC±
10 20 30 40 50 60 70 80 90
CL – Load Capacitance – pF
100
CL – Load Capacitance – pF
Figure 74
100
Figure 75
†
Values of phase margin below a load capacitance of 25 pF were estimated.
36
Page 37
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
65°
VI = 10 mV RL = 2 kΩ
CL = 25 pF See Figure 4
63°
61°
59°
m
φ – Phase Margin
57°
55°
–75
TL051
PHASE MARGIN
†
vs
FREE-AIR TEMPERATURE
V
= ±15 V
CC±
V
= ±5 V
CC±
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
Figure 76
65°
65°
VI = 10 mV RL = 2 kΩ
CL = 25 pF See Figure 4
–75
–50 –25 0 25 50 75 100
125
63°
61°
59°
m
φ – Phase Margin
57°
55°
TL054
PHASE MARGIN
†
vs
FREE-AIR TEMPERATURE
TL052
PHASE MARGIN
†
vs
FREE-AIR TEMPERATURE
V
= ±15 V
CC±
V
= ±5 V
CC±
TA – Free-Air Temperature – °C
Figure 77
125
63°
61°
59°
m
φ – Phase Margin
57°
55°
–75
–50 –25 0 25 50 75 100
TA – Free-Air Temperature – °C
V
CC±
V
CC±
= ±5 V
= ±15 V
VI = 10 mV RL = 2 kΩ
CL = 25 pF See Figure 4
125
Figure 78
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
37
Page 38
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
TYPICAL CHARACTERISTICS
– Output Voltage – mV
O
V
16
12
–4
–8
–12
–16
VOLTAGE-FOLLOWER
SMALL-SIGNAL
PULSE RESPONSE
8
6
8
4
0
0 0.2 0.4 0.6 0.8 1.0
V
= ±15 V
CC±
RL = 2 kΩ CL = 100 pF TA = 25°C
See Figure 1
t – Time – µs
1.2
4
2
0
–2
– Output Voltage – VV
O
–4
–6
–8
Figure 79
VOLTAGE-FOLLOWER
LARGE-SIGNAL
PULSE RESPONSE
V
= ±15 V
CC±
RL = 2 kΩ CL = 100 pF TA = 25°C
See Figure 1
0 1 2 3 4 5
t – Time – µs
Figure 80
6
38
Page 39
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
output characteristics
All operating characteristics (except bandwidth and phase margin) are specified with 100-pF load capacitance. The TL05x and TL05xA drive higher capacitive loads; however, as the load capacitance increases, the resulting response pole occurs at lower frequencies, causing ringing, peaking, or even oscillation. The value of the load capacitance at which oscillation occurs varies with production lots. If an application appears to be sensitive to oscillation due to load capacitance, adding a small resistance in series with the load should alleviate the problem. Capacitive loads of 1000 pF, and larger, may be driven if enough resistance is added in series with the output (see Figure 81 and Figure 82).
(a) CL = 100 pF, R = 0 (b) CL = 300 pF, R = 0 (c) CL = 350 pF, R = 0
(d) CL = 1000 pF, R = 0
(e) CL = 1000 pF, R = 50 Ω
(f) CL = 1000 pF, R = 2 kΩ
Figure 81. Effect of Capacitive Loads
15 V
5 V
–5 V
–
+
–15 V
(see Note A)
R
C
L
2 kΩ
V
O
NOTE A: CL includes fixture capacitance.
Figure 82. Test Circuit for Output Characteristics
39
Page 40
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
input characteristics
The TL05x and TL05xA are specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction.
Because of the extremely high input impedance and resulting low-bias current requirements, the TL05x and TL05xA are well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets easily can exceed bias current requirements and cause degradation in system performance. It is good practice to include guard rings around inputs (see Figure 83). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input.
Unused amplifiers should be connected as grounded unity-gain followers to avoid possible oscillation.
V
I
(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER (c) UNITY-GAIN AMPLIFIER
+
–
V
O
V
I
–
V
+
O
V
I
–
+
Figure 83. Use of Guard Rings
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier. The low input-bias current requirements of the TL05x and TL05xA result in a very low current noise. This feature makes the devices especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ.
V
O
40
Page 41
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
phase meter
The phase meter in Figure 84 produces an output voltage of 10 mV per degree of phase delay between the two input signals V (U1) convert these two input sine waves into ±5-V square waves. Then, R1 and R4 provide level shifting prior to the SN74HC109 dual J-K flip flops.
and VB. The reference signal VA must be the same frequency as VB. The TLC3702 comparators
A
Flip-flop U2B is connected as a toggle flip-flop and generates a square wave at one-half the frequency of V Flip-flop U2A also produces a square wave at one-half the input frequency . The pulse duration of U2A varies from zero to one-half the period, where zero corresponds to zero phase delay between V the period corresponds to V
lagging VA by 360 degrees.
B
and VB and one-half
A
The output pulse from U2A causes the TLC4066 (U3) switch to charge the TL05x (U4) integrator capacitors C1 and C2. As the phase delay approaches 360 degrees, the output of U4A approximates a square wave, and U2A has an output of almost 2.5 V. U4B acts as a noninverting amplifier with a gain of 1.44 in order to scale the 0- to 2.5-V integrator output to a 0- to 3.6-V output range.
R8 and R10 provide output gain and zero-level calibration. This circuit operates over a 100-Hz to 10-kHz frequency range.
+5 V
R2
100 kΩ
V
A
U1A
R1
100 kΩ
1J
1K
S
U2A
C1
R
U3
NC
+5 V
10 kΩ
R5
R6
10 kΩ
10 kΩ
0.016 µF
R7
C1
C2
0.016 µF
+
U4A
–
+
U4B V
–
R9
20 kΩ
.
B
O
R3
100 kΩ
R4
100 kΩ
V
B
U1B
NOTE A: U1 = TLC3702; V
U2 = SN74HC109 U3 = TLC4066 U4, U5 = TL05x; V
CC±
CC±
S
2J
C1
2K
R
= ±5 V
= ±5 V
U2B
NC
Figure 84. Phase Meter
Gain
R8 50 kΩ
+5 V
R10 10 kΩ
Zero
–5 V
41
Page 42
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
precision constant-current source over temperature
A precision current source (see Figure 85) benefits from the high input impedance and stability of Texas Instruments enhanced-JFET process. A low-current shunt regulator maintains 2.5 V between the inverting input and the output of the TL05x. The negative feedback then forces 2.5 V across the current-setting resistor R; therefore, the current to the load simply is 2.5 V divided by R.
Possible choices for the shunt regulator include the LT1004, LT1009, and LM385. If the regulator’s cathode connects to the operational amplifier output, this circuit sources load current. Similarly , if the cathode connects to the inverting input, the circuit sinks current from the load. T o minimize output current change with temperature, R should be a metal film resistor with a low temperature coefficient. Also, this circuit must be operated with split-voltage supplies.
150 pF
150 pF
100 kΩ
I
O
Load
V = 0 to 10 V
(a) SOURCE CURRENT LOAD (b) SINK CURRENT LOAD
NOTE A: U1 = 1/2 TL05x
U2 = LM385, LT1004, or LT1009 voltage reference
2.5 V
I =
, R = Low-temperature-coefficient metal-film resistor
R
U2
+15 V
Load
100 kΩ
I
I
–
U1
+
–15 V
R
V = 0 to –10 V
Figure 85. Precision Constant-Current Source
U2
+15 V
–
U1 +
–15 V
R
42
Page 43
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
instrumentation amplifier with adjustable gain/null
The instrumentation amplifier in Figure 86 benefits greatly from the high input impedance and stable input offset voltage of the TL05xA. Amplifiers U1A, U1B, and U2A form the actual instrumentation amplifier, while U2B provides offset null. Potentiometer R1 provides gain adjustment. With R1 = 2 kΩ, the circuit gain equals 100, while with R1 = 200 kΩ, the circuit gain equals two. The following equation shows the instrumentation amplifier gain as a function of R1:
R2)R3
+1)
A
V
Readjusting the offset null is necessary when the circuit gain is changed. If U2B is needed for another application, R7 can be terminated at ground. The low input offset voltage of the TL05xA minimizes the dc error of the circuit. For best matching, all resistors should be one-percent tolerance. The matching between R4, R5, R6, and R7 controls the CMRR of this application.
The following equation shows the output voltages when the input voltage equals zero. This dc error can be nulled by adjusting the offset null potentiometer; however , any change in offset voltage over time or temperature also creates an error. To calculate the error from changes in offset, consider the three offset components in the equation as delta offsets, rather than initial offsets. The improved stability of T exas Instruments enhanced JFET s minimizes the error resulting from change in input offset voltage with time. Assuming V be shown as a function of the offset voltage:
ǒ
R1
Ǔ
equals zero, VO can
I
VO+
200 kΩ
10 turn
AV = 2 to 100
V
–V
IO2
IO1
V
2 kΩ
V
R3
ǒ
ƪ
1
R3
ƪ
R1
I–
R1
I+
)
R1
ǒ
+
U1A
–
–
U1B
+
Ǔ
R5)R7
ǒ
R5)R7
R7
100 kΩ
R2
10 MΩ
10 MΩ
R3
100 kΩ
R7
Ǔ
Ǔ
ǒ
1
)
10 kΩ
10 kΩ
ǒ
R6 R4
R4
R5
R6
)
Ǔ
)
R4
Ǔ
R6 R4
10 kΩ
)
ǒ
–
U2A
+
R7
1
R2 R1
1
)
R6
10 kΩ
ǒ
R2 R1
R6 R4
Ǔ
ƫ
Ǔ
ƫ
)
V
IO3
–
U2B
+
0.1 µF
R6
ǒ
1
)
R4
V
O
Offset Null
Ǔ
V
CC+
82 kΩ
1 kΩ 82 kΩ
NOTE A: U1 and U2 = TL05xA; V
= ±15 V.
CC±
Figure 86. Instrumentation Amplifier
V
CC–
43
Page 44
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
high input impedance log amplifier
The low input offset voltage and high input impedance of the TL05xA creates a precision log amplifier (see Figure 87). IC1 is a 2.5-V, low-current precision, shunt regulator. Transistors Q1 and Q2 must be a closely matched npn pair. For best performance over temperature, R4 should be a metal-film resistor with a low temperature coefficient.
In this circuit, U1A serves as a high-impedance unity-gain buffer. Amplifier U1B converts the input voltage to a current through R1 and Q1. Amplifier U1C, IC1, and R4 form a 1-µA temperature-stable current source that sets the base-emitter voltage of Q2. U1D amplifies the difference between the base-emitter voltage of Q1 and Q2 (see Figure 88). The output voltage is given by the following equation:
kT
ƫ
R1
10 kΩ
ȱ
In
ȧ
q
ǒ
R1 1 10
Ȳ
R6
VO+
ƪ
–
1
)
R5
+ U1A
_
V
I
NOTE A: U1A through U1D = TL05xA. IC1 = LM385, LT1004, or LT1009 voltage reference
V
I
Q1 Q2
2N2484
R2
15 V
+
U1B
_
–15V
10 kΩ
R3
270 kΩ
ȳ
where k+1.38 10
ȧ
–6
Ǔ
and T is Kelvin temperature
ȴ
R4
2.5 MΩ
+
U1C
_
C1
150 pF
IC1
R5
10 kΩ
Figure 87. Log Amplifier
–0.1
–0.15
–23
,q+1.602 10
+ U1D
_
R6
10 kΩ
–19
V
O
(see equation above)
,
44
–0.2
–0.25
–0.3
–0.35
– Differential Voltage Amplification – dB
VD
A
–0.4
0123456
f – Frequency – Hz
78910
Figure 88. Output Voltage vs Input Voltage for Log Amplifier
Page 45
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
analog thermometer
By combining a current source that does not vary over temperature with an instrumentation amplifier, a precise analog thermometer can be built (see Figure 89). Amplifier U1A and IC1 establish a constant current through the temperature-sensing diode D1. For this section of the circuit to operate correctly , the TL05x must use split supplies, and R3 must be a metal-film resistor with a low temperature coefficient.
The temperature-sensitive voltage from the diode is compared to a temperature-stable voltage reference set by IC2. R4 should be adjusted to provide the correct output voltage when the diode is at a known temperature. Although this potentiometer resistance varies with temperature, the divider ratio of the potentiometer remains constant.
Amplifiers U1B, U2A, and U2B form the instrumentation amplifier that converts the difference between the diode and reference voltage to a voltage proportional to the temperature. With switch S1 closed, the amplifier gain equals 5 and the output voltage is proportional to temperature in degrees Celsius. With S1 open, the amplifier gain is 9 and the output is proportional to temperature in degrees Fahrenheit. Every time S1 is changed, R4 must be recalibrated. By setting S1 correctly, the output voltage equals 10 mV per degree (C or F).
IC1
R1
100 kΩ
D1
(see Note A)
C1
150 pF
–
U1A
+
R3
+15 V
10 kΩ (see Note B)
+
U1B
–
R6
10 kΩ
R5
5 kΩ
S1
(see Note C)
R9 R12
10 kΩ 10 kΩ
R7 5 kΩ
+15 V
–
U2B
+
–15 V
V
O
(see Note D)
100 kΩ
R2
IC2
NOTES: A. Temperature-sensing diode ≈ (–2 mV/°C)
B. Metal-film resistor (low temperature coefficient) C. Switch open for °F and closed for °C D. VO α temperature; 10 mV/°C or 10 mV/°F E. U1, U2 = TL05x. IC1, IC2 = LM385, LT1004, or LT1009 voltage reference
R4 50 kΩ
Figure 89. Analog Thermometer
R8
10 kΩ
–
U2A
+
R10
10 kΩ
R11 10 kΩ
45
Page 46
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
voltage-ratio-to-dB converter
The application in Figure 90 measures the amplitude ratio of two signals, then converts the ratio to decibels (see Figure 91). The output voltage provides a resolution of 100 mV/dB. The two inputs can be either dc or sinusoidal ac signals. When using ac signals, both signals should be the same frequency or output glitches will occur. For measuring two input signals of different frequencies, extra filtering should be added after the rectifiers.
The circuit contains three low-offset TL05xA devices. Two of these devices provide the rectification and logarithmic conversion of the inputs. The third TL05xA forms an instrumentation amplifier. The stage performing the logarithmic conversion also requires two well-matched npn transistors.
The input signal first passes through a high-impedance unity-gain buffer U1A (U2A). Then U1B (U2B) rectifies the input signal at a gain of 0.5, and U1C (U2C) provides a noninverting gain of 2, so that the system gain is still one. U1D (U2D), R6 (R13), and Q1 (Q2) perform the logarithmic conversion of the rectified input signal. The instrumentation amplifier formed by U3A, U3B, U3D scales the difference of the two logarithmic voltages by a gain of 33.6. As a result, the output voltage equals 100 mV/dB. The 1-kΩ potentiometer on the input of U3C calibrates the zero-dB reference level. The following equations are used to derive the relationship between the input voltage ratio, expressed in decibels, and the output voltage.
In (10)
Ǔ
B
V
BE(Q2)
kT
q
–19
Ǔ–ǒ
A
ƫ
ƪ
ƫ
, and T is Kelvin temperature
InǒV
A
+
Ǔ
ƫ
S
ȱ
20
ȧ Ȳ
– InǒV
+
V
A
ƪ
XdB+20 log
XdB+8.686ƪInǒV
V
BE(Q1)
D
VBE+
XdB
where
k+1.38 10
This gives a resolution of 1 V/dB. Therefore, the gain of the instrumentation amplifier is set at 33.6 to obtain 100 mV/dB.
kT
+
In
q
V
BE(Q1)–VBE(Q2)
8.686
+
kTńq
–23
ƫ
V
B
V
A
ƪ
R I
ƪ
V
BE(Q1)–VBE(Q2)
,q+1.602 10
V
+
InǒV
+
336ƪV
Ǔ
ȳ
B
ȧ ȴ
kT
q
Ǔ
A
V
In
ƪ
R I
– InǒV
BE(Q1)–VBE(Q2)
B
ƫ
S
Ǔ
ƫ
B
ƫ
at 25°C
46
Page 47
TL05x, TL05xA
ENHANCED-JFET LOW-OFFSET
OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
R2
V
V
+
A
U1A
_
+
B
U2A
_
R1
20 kΩ
R8
20 kΩ
10 kΩ
+ U1B
_
10 kΩ
+ U2B
_
R9
D1
R3
30 kΩ
D2
R10
30 kΩ
+ U1C
_
R5
10 kΩ
R4 10 kΩ
+ U2C
_
10 kΩ
R11 10 kΩ
R6
10 kΩ
R13
10 kΩ
R12
+
U1D
_
+
U2D
_
2N2484
2N2484
10 kΩ
R7
10 kΩ
R14
82 kΩ
82 kΩ
1 kΩ
Q2
15 V
–15 V
Q1
16.3 kΩ
+ U3A
_
R16
16.3 kΩ
R76
+
U3B
_
C1
+
U3C
_
R18
10 kΩ
R19
10 kΩ
R20
10 kΩ
+ U3D
_
R21 10 kΩ
V
O
NOTE A: U1A through U3D = TL05xA, V
– Output Voltage – V
O
V
Figure 91. Output Voltage vs the Ratio of the Input Voltages for Voltage-to-dB Converter
= ±15 V. D1 and D2 = 1N914.
CC±
Figure 90. Voltage Ratio-to-dB Converter
2
1
0
–1
–2
0123456
Ratio – VA/V
78910
B
47
Page 48
TL05x, TL05xA ENHANCED-JFET LOW-OFFSET OPERATIONAL AMPLIFIERS
SLOS178A – FEBRUARY 1997 - REVISED FEBRUARY 2003
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts, the model-generation software used with Microsim PSpice. The Boyle macromodel (see Note 6 and subcircuit Figure 92) are generated using the TL05x typical electrical and operating characteristics at T of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
Maximum positive output voltage swing
D
Maximum negative output voltage swing
D
Slew rate
D
Quiescent power dissipation
D
Input bias current
D
Open-loop voltage amplification
= 25°C. Using this information, output simulations
A
D
Unity-gain frequency
D
Common-mode rejection ratio
D
Phase margin
D
DC output resistance
D
AC output resistance
D
Short-circuit output current limit
NOTE 6: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
V
CC+
RSS ISS
RP
2
IN–
DP
IN+
3
V
CC–
.SUBCKT TL05x 1 2 3 4 5
C1 11 12 3.988E–12 C2 6 7 15.00E–12 DC 5 53 DX DE 54 5 DX DLP 90 91 DX DLN 92 90 DX DP43DX EGND99 0 POLY (2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY (5) VB VC VE VLP + VLN 0 2.875E6 –3E6 3E6 3E6 –3E6 GA 6 0 11 12 292.2E–6 GCM 0 6 10 99 6.542E–9 ISS 3 10 DC 300.0E–6 HLIM 90 0 VLIM 1K J1 11 2 10 JX J2 12 1 10 JX R2 6 9 100.0E3
J1 J2
11
RD1
VAD
3
10
C1
+
–
4
12
RD2
60
VE
99
EGND
9
+
+
VC
DC
54
+–
R2
–
53
DE
–
6
GCM
+
FB
–
VB
C2
GA
RD1 4 11 3.422E3 RD2 4 12 3.422E3 R01 8 5 125 R02 7 99 125 RP 3 4 11.11E3 RSS 10 99 666.7E6 VB 9 0 DC 0 VC 3 53 DC 3 VE 54 4 DC 3.7 VLIM 7 8 DC 0 VLP 91 0 DC 28 VLN 0 92 DC 28 .MODEL DX D (IS=800.0E–18) .MODEL JX PJF (IS=15.00E–12 BETA=185.2E–6 + VTO=–.1) .ENDS
7
VLIM
RO2
HLIM
8
5
OUT
+
–
RO1
90
+
DLP
–
+
–
91
DLN
92
–
VLNVLP
+
Figure 92. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
Macromodels, simulation models, or other models provided by TI, directly or indirectly, are not warranted by TI as fully representing all of the specification and operating characteristics of the semiconductor product to which the model relates.
48
Page 49
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
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Wireless
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
Page 50
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
TL051ACD ACTIVE SOIC D 8 75 Green (RoHS &
TL051ACDE4 ACTIVE SOIC D 8 75 Green (RoHS &
TL051ACDG4 ACTIVE SOIC D 8 75 Green (RoHS &
TL051ACP ACTIVE PDIP P 8 50 Pb-Free
TL051ACPE4 ACTIVE PDIP P 8 50 Pb-Free
TL051AID OBSOLETE SOIC D 8 TBD Call TI Call TI TL051AIP OBSOLETE PDIP P 8 TBD Call TI Call TI TL051CD ACTIVE SOIC D 8 75 Green (RoHS &
TL051CDE4 ACTIVE SOIC D 8 75 Green (RoHS &
TL051CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
TL051CDR ACTIVE SOIC D 8 2500 Green (RoHS &
TL051CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
TL051CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
TL051CP ACTIVE PDIP P 8 50 Pb-Free
TL051CPE4 ACTIVE PDIP P 8 50 Pb-Free
TL051ID OBSOLETE SOIC D 8 TBD Call TI Call TI
TL051IDR OBSOLETE SOIC D 8 TBD Call TI Call TI
TL051IP OBSOLETE PDIP P 8 TBD Call TI Call TI
TL052ACD ACTIVE SOIC D 8 75 Green (RoHS &
TL052ACDE4 ACTIVE SOIC D 8 75 Green (RoHS &
TL052ACDG4 ACTIVE SOIC D 8 75 Green (RoHS &
TL052ACDR ACTIVE SOIC D 8 2500 Green (RoHS &
TL052ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
TL052ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
TL052ACP ACTIVE PDIP P 8 50 Pb-Free
TL052ACPE4 ACTIVE PDIP P 8 50 Pb-Free
TL052AID ACTIVE SOIC D 8 75 Green (RoHS &
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
23-Apr-2007
(3)
Addendum-Page 1
Page 51
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
TL052AIDE4 ACTIVE SOIC D 8 75 Green (RoHS &
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052AIDG4 ACTIVE SOIC D 8 75 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052AIDR ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052AIDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052AIP ACTIVE PDIP P 8 50 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL052AIPE4 ACTIVE PDIP P 8 50 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS) TL052AMFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI TL052AMJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI
TL052CD ACTIVE SOIC D 8 75 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052CDE4 ACTIVE SOIC D 8 75 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052CDG4 ACTIVE SOIC D 8 75 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052CDR ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052CP ACTIVE PDIP P 8 50 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL052CPE4 ACTIVE PDIP P 8 50 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL052CPSR ACTIVE SO PS 8 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052CPSRE4 ACTIVE SO PS 8 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052ID ACTIVE SOIC D 8 75 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052IDE4 ACTIVE SOIC D 8 75 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052IDG4 ACTIVE SOIC D 8 75 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052IDR ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052IDRE4 ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL052IP ACTIVE PDIP P 8 50 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL052IPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type
23-Apr-2007
(3)
Addendum-Page 2
Page 52
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(RoHS)
TL052MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TL052MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI
TL052MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI
TL054ACD ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054ACDE4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054ACDG4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054ACDR ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054ACN ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS) TL054ACNE4 ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL054AID ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054AIDE4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054AIDG4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054AIDR ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054AIDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054AIN ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL054AINE4 ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS) TL054AMFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TL054AMJB OBSOLETE CDIP J 14 TBD Call TI Call TI
TL054CD ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054CDBR ACTIVE SSOP DB 14 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054CDBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054CDE4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054CDG4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054CDR ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
23-Apr-2007
(3)
Addendum-Page 3
Page 53
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
TL054CDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
23-Apr-2007
(3)
no Sb/Br)
TL054CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054CN ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL054CNE4 ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL054CNSR ACTIVE SO NS 14 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054CNSRE4 ACTIVE SO NS 14 2000 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054ID ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054IDE4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054IDG4 ACTIVE SOIC D 14 50 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054IDR ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TL054IN ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL054INE4 ACTIVE PDIP N 14 25 Pb-Free
CU NIPDAU N / A for Pkg Type
(RoHS)
TL054MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TL054MJ OBSOLETE CDIP J 14 TBD Call TI Call TI
TL054MJB OBSOLETE CDIP J 14 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 4
Page 54
PACKAGE OPTION ADDENDUM
www.ti.com
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
23-Apr-2007
Addendum-Page 5
Page 55
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
Page 56
PACKAGE MATERIALS INFORMATION
www.ti.com
Device Package Pins Site Reel
Diameter
(mm)
TL051CDR D 8 FMX 330 12 6.4 5.2 2.1 8 12 Q1
TL052ACDR D 8 FMX 330 12 6.4 5.2 2.1 8 12 Q1
TL052AIDR D 8 FMX 330 12 6.4 5.2 2.1 8 12 Q1
TL052CDR D 8 FMX 330 12 6.4 5.2 2.1 8 12 Q1
TL052CPSR PS 8 MLA 330 16 8.2 6.6 2.5 12 16 Q1
TL052IDR D 8 FMX 330 12 6.4 5.2 2.1 8 12 Q1
TL054ACDR D 14 FMX 330 0 6.5 9.0 2.1 8 16 Q1
TL054AIDR D 14 FMX 330 0 6.5 9.0 2.1 8 16 Q1
TL054CDBR DB 14 MLA 330 16 8.2 6.6 2.5 12 16 Q1
TL054CDR D 14 FMX 330 0 6.5 9.0 2.1 8 16 Q1
TL054CNSR NS 14 MLA 330 16 8.2 10.5 2.5 12 16 Q1
TL054IDR D 14 FMX 330 0 6.5 9.0 2.1 8 16 Q1
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
3-May-2007
Pin1
Quadrant
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TL051CDR D 8 FMX 338.1 340.5 20.64
TL052ACDR D 8 FMX 338.1 340.5 20.64
TL052AIDR D 8 FMX 338.1 340.5 20.64
TL052CDR D 8 FMX 338.1 340.5 20.64
TL052CPSR PS 8 MLA 333.2 333.2 28.58
TL052IDR D 8 FMX 338.1 340.5 20.64
TL054ACDR D 14 FMX 333.2 333.2 28.58
TL054AIDR D 14 FMX 333.2 333.2 28.58
TL054CDBR DB 14 MLA 333.2 333.2 28.58
Pack Materials-Page 2
Page 57
PACKAGE MATERIALS INFORMATION
www.ti.com
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TL054CDR D 14 FMX 333.2 333.2 28.58
TL054CNSR NS 14 MLA 333.2 333.2 28.58
TL054IDR D 14 FMX 333.2 333.2 28.58
3-May-2007
Pack Materials-Page 3
Page 58
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
0.063 (1,60)
0.015 (0,38)
0.100 (2,54)
8
1
5
4
0.065 (1,65)
0.045 (1,14)
0.020 (0,51) MIN
0.023 (0,58)
0.015 (0,38)
0.280 (7,11)
0.245 (6,22)
0.310 (7,87)
0.290 (7,37)
0.200 (5,08) MAX Seating Plane
0.130 (3,30) MIN
0°–15°
0.014 (0,36)
0.008 (0,20)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8
4040107/C 08/96
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 59
Page 60
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A SQ
B SQ
20
22
23
24
25
19
21
12826 27
12
1314151618 17
0.020 (0,51)
0.010 (0,25)
MIN
0.342 (8,69)
0.442
0.640
0.739
0.938
1.141
A
0.358 (9,09)
0.458
(11,63)
0.660
(16,76)
0.761
(19,32)(18,78)
0.962
(24,43)
1.165
(29,59)
(10,31)
(12,58)
(12,58)
NO. OF
TERMINALS
**
11
10
9
8
7
6
5
432
20
28
44
52
68
84
0.020 (0,51)
0.010 (0,25)
(11,23)
(16,26)
(23,83)
(28,99)
MINMAX
0.307
(7,80)
0.406
0.495
0.495
0.850
(21,6)
1.047
(26,6)
0.080 (2,03)
0.064 (1,63)
B
MAX
0.358 (9,09)
0.458
(11,63)
0.560
(14,22)
0.560
(14,22)
0.858 (21,8)
1.063 (27,0)
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
Page 61
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8) PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
0.021 (0,53)
0.015 (0,38)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
4
0.070 (1,78) MAX
0.020 (0,51) MIN
0.200 (5,08) MAX
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
Seating Plane
M
0.325 (8,26)
0.300 (7,62)
0.015 (0,38) Gage Plane
0.010 (0,25) NOM
0.430 (10,92) MAX
4040082/D 05/98
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 62
Page 63
Page 64
Page 65
Page 66
Page 67
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38 0,22
15
14
A
0,05 MIN
0,15
5,60 5,00
M
8,20 7,40
Seating Plane
0,10
0,25 0,09
0°–ā8°
Gage Plane
0,25
0,95 0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
Page 68
IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.
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