Datasheet TIP 3055G ONS Datasheet

TIP3055 (NPN),
TIP2955 (PNP)

Complementary Silicon
Power Transistors

Designed for general−purpose switching and amplifier applications.

Features

• DC Current Gain −

h

= 20−70 @ IC

FE

= 4.0 Adc

• Collector−Emitter Saturation Voltage −

V

• Excellent Safe Operating Area

• These are Pb−Free Devices*

MAXIMUM RATINGS

Collector − Emitter Voltage V

Collector − Emitter Voltage V

Collector − Base Voltage V

Emitter − Base Voltage V

Collector Current − Continuous I

Base Current I

Total Power Dissipation @ TC = 25°C
Derate above 25°C

Operating and Storage Junction
Temperature Range

= 1.1 Vdc (Max) @ IC

CE(sat)

= 4.0 Adc

Rating Symbol Value Unit

CEO

CER

P

TJ, T

CB

EB

C

B

D

stg

60 Vdc

70 Vdc

100 Vdc

7.0 Vdc

1 5 Adc

7.0 Adc

90

0.72

–65 to

+150

W/°C

W

°C

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15 AMPERE

POWER TRANSISTORS

COMPLEMENTARY SILICON

60 VOLTS, 90 WATTS

SOT−93 (TO−218)

CASE 340D

STYLE 1

TO−247

CASE 340L

STYLE 3

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Thermal Resistance, Junction−to−Case

Thermal Resistance, Junction−to−Ambient

Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2012

May, 2012 − Rev. 7

R

q

JC

R

q

JA

1.39 °C/W

35.7 °C/W

1 Publication Order Number:

NOTE: Effective June 2012 this device will

be available only in the TO−247
package. Reference FPCN# 16827.

ORDERING INFORMATION

See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.

TIP3055/D

TIP3055 (NPN), TIP2955 (PNP)

MARKING DIAGRAMS

TO−247

TIPxx55

AYWWG

1 BASE

2 COLLECTOR

3 EMITTER

TIPxx55 = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G=Pb−Free Package

ORDERING INFORMATION

Device Package Shipping

TIP3055G SOT−93 (TO−218)

TIP2955G SOT−93 (TO−218)

TIP3055G TO−247

TIP2955G TO−247

(Pb−Free)

(Pb−Free)

(Pb−Free)

(Pb−Free)

1 BASE

TO−218

AYWWG

TIPxx55

3 EMITTER

2 COLLECTOR

30 Units / Rail

30 Units / Rail

30 Units / Rail

30 Units / Rail

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2

TIP3055 (NPN), TIP2955 (PNP)

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

C

Characteristic

OFF CHARACTERISTICS

Collector−Emitter Sustaining Voltage (Note 1)

(I

= 30 mAdc, IB = 0)

C

Collector Cutoff Current

= 70 Vdc, RBE = 100 Ohms)

(V

CE

Collector Cutoff Current

(V

= 30 Vdc, IB = 0)

CE

Collector Cutoff Current

(V

= 100 Vdc, V

CE

BE(off)

= 1.5 Vdc)

Emitter Cutoff Current

(V

= 7.0 Vdc, IC = 0)

BE

ON CHARACTERISTICS (Note 1)

DC Current Gain

(I

= 4.0 Adc, VCE = 4.0 Vdc)

C

= 10 Adc, VCE = 4.0 Vdc)

(I

C

Collector−Emitter Saturation Voltage

(I

= 4.0 Adc, IB = 400 mAdc)

C

= 10 Adc, IB = 3.3 Adc)

(I

C

Base−Emitter On Voltage

(I

= 4.0 Adc, VCE = 4.0 Vdc)

C

SECOND BREAKDOWN

Second Breakdown Collector Current with Base Forward Biased

(V

= 30 Vdc, t = 1.0 s; Nonrepetitive)

CE

DYNAMIC CHARACTERISTICS

Current Gain — Bandwidth Product

(I

= 0.5 Adc, VCE = 10 Vdc, f = 1.0 MHz)

C

Small−Signal Current Gain

(V

= 4.0 Vdc, IC = 1.0 Adc, f = 1.0 kHz)

CE

NOTE: For additional design curves, refer to electrical characteristics curves of 2N3055.

1. Pulse Test: Pulse Width = 300 ms, Duty Cycle v 2.0%.

Symbol

V

CEO(sus)

I

CER

I

CEO

I

CEV

I

EBO

h

FE

V

CE(sat)

V

BE(on)

I

s/b

f

T

h

fe

Min

60

−

−

−

−

20

5.0

−

−

−

3.0

2.5

15

Max

−

1.0

0.7

5.0

5.0

70

−

1.1

3.0

1.8

−

−

−

Unit

Vdc

mAdc

mAdc

mAdc

mAdc

−

Vdc

Vdc

Adc

MHz

kHz

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3

1000

TIP3055 (NPN), TIP2955 (PNP)

VCE = 4.0 V
T

= 25°C

J

100

50
30

20

10

5.0

3.0

2.0

1.0

0.5

, COLLECTOR CURRENT (AMPS)

C

0.3

I

0.2

0.1

1.0 2.0 4.0 6.0 10 20

SECONDARY BREAKDOWN LIMIT
BONDING WIRE LIMIT
THERMAL LIMIT @ T

TJ = 150°C

VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)

dc

= 25°C

C

100

, DC CURRENT GAIN

FE

h

10

0.2 0.5 0.7 3.0 5.0

0.1
IC, COLLECTOR CURRENT (AMP)

1.0 2.00.3 7.0 10

Figure 1. DC Current Gain

a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate I

1.0ms

300 ms

10ms

limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.

variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be
derated for temperature.

40 60

TIP3055
TIP2955

There are two limitations on the power handling ability of

− V

C

CE

The data of Figure 2 is based on T

= 25°C; T

C

J(pk)

is

Figure 2. Maximum Rated Forward Bias

Safe Operating Area

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4

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

SOT−93 (TO−218)

CASE 340D−02

ISSUE E DATE 01/03/2002

SCALE 1:1

C

B

U

L

S

K

4

123

Q

E

A

D

J

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

DIM MIN MAX MIN MAX

A --- 20.35 --- 0.801
B 14.70 15.20 0.579 0.598
C 4.70 4.90 0.185 0.193
D 1.10 1.30 0.043 0.051
E 1.17 1.37 0.046 0.054
G 5.40 5.55 0.213 0.219
H 2.00 3.00 0.079 0.118
J 0.50 0.78 0.020 0.031
K 31.00 REF 1.220 REF
L --- 16.20 --- 0.638
Q 4.00 4.10 0.158 0.161
S 17.80 18.20 0.701 0.717
U 4.00 REF 0.157 REF
V 1.75 REF 0.069

INCHESMILLIMETERS

MARKING DIAGRAM

V

G

STYLE 1:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 2:

PIN 1. ANODE

2. CATHODE

3. ANODE

4. CATHODE

AYWW
xxxxx

A = Assembly Location
Y = Year
WW = Work Week
xxxxx = Device Code

DOCUMENT NUMBER:

DESCRIPTION:

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019

98ASB42643B

SOT−93

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1

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MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

TO−247

CASE 340L−02

ISSUE F

DATE 26 OCT 2011

N

A

K

F

2 PL

STYLE 1:

PIN 1. GATE

2. DRAIN

3. SOURCE

4. DRAIN

STYLE 5:

PIN 1. CATHODE

2. ANODE

3. GATE

4. ANODE

SCALE 1:1

−B−

123

G

D

3 PL

0.25 (0.010)MYQ

STYLE 2:

STYLE 6:

U

P

−Y−

W

PIN 1. ANODE

2. CATHODE (S)

3. ANODE 2

4. CATHODES (S)

PIN 1. MAIN TERMINAL 1

2. MAIN TERMINAL 2

3. GATE

4. MAIN TERMINAL 2

−T−

C

E

L

4

−Q−

0.63 (0.025)MTB

J

H

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

DIM MIN MAX MIN MAX

A 20.32 21.08 0.800 8.30
B 15.75 16.26 0.620 0.640
C 4.70 5.30 0.185 0.209
D 1.00 1.40 0.040 0.055

M

E 1.90 2.60 0.075 0.102
F 1.65 2.13 0.065 0.084
G 5.45 BSC 0.215 BSC
H 1.50 2.49 0.059 0.098
J 0.40 0.80 0.016 0.031
K 19.81 20.83 0.780 0.820
L 5.40 6.20 0.212 0.244
N 4.32 5.49 0.170 0.216
P --- 4.50 --- 0.177
Q 3.55 3.65 0.140 0.144
U 6.15 BSC 0.242 BSC
W 2.87 3.12 0.113 0.123

GENERIC

INCHESMILLIMETERS

MARKING DIAGRAM*

S

STYLE 3:

PIN 1. BASE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

STYLE 4:

PIN 1. GATE

2. COLLECTOR

3. EMITTER

4. COLLECTOR

XXXXXXXXX

AYWWG

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

© Semiconductor Components Industries, LLC, 2002

October, 2002 − Rev. 0

DESCRIPTION:

98ASB15080C

ON SEMICONDUCTOR STANDARD

TO−247

http://onsemi.com

1

XXXXX = Specific Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.

Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.

Case Outline Number:

PAGE 1 OF 2

XXX

DOCUMENT NUMBER:
98ASB15080C

PAGE 2 OF 2

ISSUE REVISION DATE

D CHANGE OF OWNERSHIP FROM MOTOROLA TO ON SEMICONDUCTOR. DIM A

25 AUG 2000
WAS 20.80−21.46/0.819−0.845. DIM K WAS 19.81−20.32/0.780−0.800. UPDATED
STYLE 1, ADDED STYLES 2, 3, & 4. REQ. BY L. HAYES.

E DIM E MINIMUM WAS 2.20/0.087. DIM K MINIMUM WAS 20.06/0.790. ADDED

26 FEB 2010

GENERIC MARKING DIAGRAM. REQ. BY S. ALLEN.

F ADDED STYLES 5 AND 6. REQ. BY J. PEREZ. 26 OCT 2011

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© Semiconductor Components Industries, LLC, 2011

Case Outline Number:

October, 2011 − Rev. 02F

340L

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