Datasheet TICPAL22V10Z-25CFN, TICPAL22V10Z-25CNT Datasheet (Texas Instruments)

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Page 1

TICPAL22V10Z-25C, TICPAL22V10Z-30I

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

• 24-Pin Advanced CMOS PLD

• Virtually Zero Standby Power

• Propagation Delay Time:

I, I/O to I/O in the Turbo Mode

-25C . . . 25 ns Max

-30I . . . 30 ns Max

I, I/O to I/O in the Zero-Power Mode

-25C . . . 35 ns Max

-30I . . . 40 ns Max

CLK to Q

-25C . . . 15 ns Max

-30I . . . 20 ns Max

• Variable Product Term Distribution Allows

More Complex Functions to Be Implemented

• Each Output Is User-Programmable for

Registered or Combinatorial Operation, Polarity, and Output Enable Control

• Extra Terms Provide Logical Synchronous

Set and Asynchronous Reset Capability

• Preload Capability on All Registered

Outputs Allow for Improved Device Testing

• UV Light Erasable Cell Technology Allows

for:

Reconfigurable Logic Reprogrammable Cells Full Factory Testing for High

Programming Yield

• Programmable Design Security Bit

Prevents Copying of Logic Stored in Device

JTL AND NT PACKAGE

(TOP VIEW)

24 23 22 21 20 19 18 17 16 15 14 13

I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I

I/O/Q

25 24 23 22 21 20 19

I/O/Q

CLK/I

GND

I I I

11 12

FN PACKAGE

(TOP VIEW)

CLK/INCI/O/Q

3212827

426

5 6 7 8 9

12 13

14 15 16 1718

GND

– No internal connection

NC Pin assignments in operating mode

I/O/Q I/O/Q I/O/Q NC I/O/Q I/O/Q I/O/Q

• Package Options Include Plastic

Dual-In-Line and Clip Carrier [for One-Time-Programmable (OTP) Devices] and Ceramic Dual-In-Line Windowed Package

RANGE

0°C to 75°C TICPAL22V10Z-25CJTL TICPAL22V10Z-25CNT TICPAL22V10Z-25CFN

–40°C to 85°C NA TICPAL22V10Z-30INT TICPAL22V10Z-30IFN

These devices are covered by U.S. Patent 4,410,987. EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

CERAMIC WINDOWED

DUAL-IN-LINE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

(JTL)

PACKAGE TYPE

PLASTIC

DUAL-IN-LINE

(NT)

PLASTIC

CHIP CARRIER

(FN)

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TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

description

The CMOS PLD devices feature variable product terms, flexible outputs, and virtually zero standby power. It combines TI’s EPIC (Enhanced Processed Implanted CMOS) process with ultraviolet-light-erasable EPROM technology. Each output has an output logic macrocell (OLM) configuration allowing for user definition of the output type. This device provides reliable, low-power substitutes for numerous high-performance TTL PLDs with gate complexities between 300 and 800 gates.

The TICPAL22V10Z has 12 dedicated inputs and 10 user-definable outputs. Individual outputs can be programmed as registered or combinational and inverting or noninverting as shown in the OLM diagram. These ten outputs are enabled through the use of individual product terms

The variable product-term distribution on this device removes rigid limitation to a maximum of eight product terms per output. This technique allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. The variable allocation of product terms allows for far more complex functions to be implemented in this device than in previously available devices.

With features such as the programmable OLMs and the variable product-term distribution, the TICP AL22V10Z offers quick design and development of custom LSI functions. Since each of the ten output pins may be individually configured as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and 10 outputs can be implemented with this device.

Design complexity is enhanced by the addition of synchronous set and asynchronous reset product terms. These functions are common to all registers. When the synchronous set product term is a logic 1, the output registers are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term is a logic 1, the output registers are loaded with a logic 0 independently of the clock. The output logic level after set or reset will depend on the polarity selected during programming.

Output registers of this device can be preloaded to any desired state during testing, thus allowing for full logical verification during product testing.

The TICP AL22V10Z has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V ESD rating tested under MIL-STD-883C, Method 3015.6. However, care should be exercised in handling these devices, as exposure to ESD may result in a degradation of the device parametric performance.

The floating-gate programmable cells allow the devices to be fully programmed and tested before assembly to assure high field programming yield and functionality . They are then erased by ultraviolet light before packaging.

The TICPAL22V10Z-25C is characterized for operation from 0°C to 75°C. The TICPAL22V10Z-30I is characterized for operation from –40°C to 85°C.

design security

The ’PAL22V10Z contains a programmable design security cell. Programming this cell will disable the read verify and programming circuitry protecting the design from being copied. The security cell is usually programmed after the design is finalized and released to production. A secured device will verify as if every location in the device is programmed. Because programming is accomplished by storing an invisible charge instead of opening a metal link, the ’22V10Z cannot be copied by visual inspection. Once a secured device is fully erased, it can be reprogrammed to any desired configuration.

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EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

functional block diagram (positive logic)

TICPAL22V10Z-25C, TICPAL22V10Z-30I

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

CLK/I

C1 1S R

Output

Logic

Macrocell

I/O/Q

Set Reset

44 x 132

denotes programmable cell inputs

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logic diagram (positive logic)

CLK/I

First Cell Numbers

0 481216 20 24 28

396

440

880

924

1452

1496

Increment

32 36 40

MACRO CELL

P = 5808 R = 5809

MACRO CELL

P = 5810 R = 5811

MACRO CELL

P = 5812 R = 5813

MACRO CELL

Asynchronous Reset (to all registers)

I/O/Q

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

TICPAL22V10Z-25C, TICPAL22V10Z-30I

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

2112

2156

2860

P = 5814 R = 5815

MACRO CELL

P = 5816 R = 5817

I/O/Q

Page 5

2904

MACRO CELL

3608

3652

P = 5818 R = 5819

MACRO CELL

I/O/Q

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4268

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

4312

4840

4884

5324

5368

5720

5764

P = 5820 R = 5821

MACRO CELL

P = 5822 R = 5823

MACRO CELL

P = 5824 R = 5825

MACRO CELL

P = 5826 R = 5827

I/O/Q

Synchronous Set (to all registers)

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

TICPAL22V10Z-25C, TICPAL22V10Z-30I

Inside each MACROCELL the (P) cell is the polarity cell and the (R) cell is the register cell.

Programmable Cell Number = First Cell Number + Increment

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TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

output logic macrocell (OLM) description

A great amount of architectural flexibility is provided by the user-configurable macrocell output options. The macrocell consists of a D-type flip-flop and two select multiplexers. The D-type flip-flop operates like a standard TTL D-type flip-flop. The input data is latched on the low-to-high transition of the clock input. The Q and Q outputs are made available to the output select multiplexer. The asynchronous reset and synchronous set controls are available in all flip-flops.

The select multiplexers are controlled by programmable cells. The combination of these programmable cells will determine which macrocell functions are implemented. It is this user control of the architectural structure that provides the generic flexibility of this device.

output logic macrocell diagram

From Clock Buffer

Output Logic Macrocell

AR = asynchronous reset SS = synchronous set

R 1D

MUX

2 3 0

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EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

output logic macrocell options (see Figure 1)

TICPAL22V10Z-25C, TICPAL22V10Z-30I

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

R 1D

I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT

S1 = 0 S0 = 0

S1 = 1 S0 = 0

R 1D

S1 = 0 S0 = 1

S1 = 1 S0 = 1

MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE

CELL SELECT

S1 S0

0 0 Register feedback Registered Active low 0 1 Register feedback Registered Active high 1 0 I/O feedback Combinational Active low 1 1 I/O feedback Combinational Active high

0 = erased cell, 1 = programmed cell S1 and S0 are select-function cells as shown in the output logic macrocell diagram.

FEEDBACK AND OUTPUT CONFIGURATION

Figure 1. Resultant Macrocell Feedback and Output Logic After Programming

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TICP AL22V10Z-25C EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to VCC+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or V Output clamp current, I

(VO < 0 or V

> VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

> VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ± 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: FN or NT package 260°C. . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: JTL package 300°C. . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

MIN NOM MAX UNIT

V V V

t T

Supply voltage 4.75 5 5.25 V

High-level input voltage 2 V

Low-level input voltage 0.8 V

High-level output current

Low-level output current mA

Pulse duration Clock low 10 ns

Setup time, turbo mode Asynchronous reset inactive 20 ns

Setup time, zero-power mode Asynchronous reset inactive 30 ns

Hold time Input or feedback 0 ns Operating free-air temperature 0 75 °C

Driving TTL –3.2 Driving CMOS –4 Driving TTL 16 Driving CMOS 4 Clock high 10

Asynchronous reset 20 Input or feedback 17

Synchronous preset inactive 20 Input or feedback 25

Synchronous preset inactive 30

†

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TICPAL22V10Z-25C

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITION MIN TYP†MAX UNIT

OZH

OZL

‡

§ I 6

I/O 10

VCC = 4.75 V, IOH = –3.2 mA for TTL 4 4.8 VCC = 4.75 V, IOH = –4 mA for CMOS 3.86 4.7 VCC = 4.75 V, IOL = 16 mA for TTL 0.25 0.5 VCC = 4.75 V, IOL = 4 mA for CMOS 0.07 0.4 VCC = 5.25 V, VO = 2.7 V 0.01 10 µA VCC = 5.25 V, VO = 0.5 V –0.01 –10 µA VCC = 5.25 V, VI = 5.25 V 0.01 10 µA VCC = 5.25 V, VI = 0.5 V –0.01 –10 µA

VCC = 5.25 V, VO = 0.5 V –30 –45 –90 mA VCC = 5.25 V,

Outputs open,

VI = 2 V, f = 1 MHz

VI = 0 or VCC, Zero-power mode

10 100 µA

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3)

PARAMETER

max

dis

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.

Disabled outputs are tied to GND or VCC.

max

Without feedback 50 66 With feedback 31.2 55 Turbo mode 16 25 Zero-power mode 21 35 Turbo mode 18 30 Zero-power mode 23 40

Turbo mode 15 25 Zero-power mode 20 35 Turbo mode 15 25 Zero-power mode 17 35

(with feedback) =

tsu)

tpd(CLK to Q)

FROM

(INPUT)

I, I/O O, I/O

Asynchronous

RESET

CLK↑ Q 10 15 ns

I, I/O

; f

(without feedback) =

max

tw(high))tw(low)

(OUTPUT)

I, Q, I/O

MIN TYP†MAX UNIT

MHz

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Page 10

TICP AL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to VCC+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or V Output clamp current, I

(VO < 0 or V

> VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

> VCC) ± 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ± 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: FN or NT package 260°C. . . . . . . . . . . . . . . .

Operating free-air temperature range –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

MIN NOM MAX UNIT

V V V

t T

Supply voltage 4.5 5 5.5 V

High-level input voltage 2 V

Low-level input voltage 0.8 V

High-level output current

Low-level output current mA

Pulse duration Clock low 12 ns

Setup time, turbo mode Asynchronous reset inactive 25 ns

Setup time, zero-power mode Asynchronous reset inactive 35 ns

Hold time Input or feedback 0 ns Operating free-air temperature –40 85 °C

Driving TTL –3.2 Driving CMOS –4 Driving TTL 16 Driving CMOS 4 Clock high 12

Asynchronous reset 30 Input or feedback 22

Synchronous preset inactive 25 Input or feedback 30

Synchronous preset inactive 35

†

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Page 11

TICPAL22V10Z-30I

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITION MIN TYP†MAX UNIT

OZH

OZL

‡

§ I 6

I/O 10

VCC = 4.5 V, IOH = –3.2 mA for TTL 4 4.8 VCC = 4.5 V, IOH = –4 mA for CMOS 3.86 4.7 VCC = 4.5 V, IOL = 16 mA for TTL 0.25 0.5 VCC = 4.5 V, IOL = 4 mA for CMOS 0.07 0.4 VCC = 5.5 V, VO = 2.7 V 0.01 10 µA VCC = 5.5 V, VO = 0.5 V –0.01 –10 µA VCC = 5.5 V, VI = 5.5 V 0.01 10 µA VCC = 5.5 V, VI = 0.5 V –0.01 –10 µA

VCC = 5.5 V, VO = 0.5 V –30 –45 –90 mA VCC = 5.5 V,

Outputs open,

VI = 2 V, f = 1 MHz

VI = 0 or VCC, Zero-power mode

10 100 µA

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 3)

PARAMETER

max

dis

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Disabled outputs are tied to GND or VCC.

max

Without feedback 41.6 66 With feedback 23.8 55 Turbo mode 16 30 Zero-power mode 21 40 Turbo mode 18 35 Zero-power mode 23 45

Turbo mode 15 30 Zero-power mode 20 40 Turbo mode 15 30 Zero-power mode 17 40

(with feedback) =

tsu)

tpd(CLK to Q)

FROM

(INPUT)

I, I/O O, I/O

Asynchronous

RESET

CLK↑ Q 10 20 ns

I, I/O

; f

(without feedback) =

max

tw(high))tw(low)

(OUTPUT)

I, Q, I/O

MIN TYP†MAX UNIT

MHz

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Page 12

TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

preload procedure for registered outputs (see Notes 2 and 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to setup through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. The output level depends on the polarity selected during programming.

Step 1. With VCC at 5 V and pin 1 at VIL, raise pin 8 to V Step 2. Apply either V

or VIH to the output corresponding to the register to be preloaded.

IHH

Step 3. Pulse pin 1, clocking in preload data. Step 4. Remove output voltage, then lower pin 8 to V

. Preload can be verified by observing the voltage level

at the output pin.

IHH

Pin 8

CLK/I

Registered I/O Input Output

Figure 2. Preload Waveforms

NOTES: 2. Pin numbers shown are for the JTL and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed

accordingly.

= t

tw = 100 ns to 1000 ns. V

= 10.25 V to 10.75 V.

IHH

programming information

Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming T exas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.

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TICPAL22V10Z-25C, TICPAL22V10Z-30I

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

PARAMETER MEASUREMENT INFORMATION

5 V

(see Note D)

300 Ω

From Output

Under Test

Test

Point

CLK

Data

Input

In-Phase

Output

Out-of-Phase

Output

(see Note D)

PROPAGATION DELAY TIMES

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

(see Note A)

1.5 V

LOAD CIRCUIT FOR

3-STATE OUTPUTS

3 V

0 (see Note B)

3 V

390 Ω

High-Level

Pulse

Low-Level

Pulse

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note C)

Waveform 2

S1 Open

(see Note C)

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

1.5 V

dis

3 V

0 (see Note B)

3 V

0 (see Note B)

≈ 3.3 V

VOL + 0.5 V

VOH – 0.5 V

≈ 0 V

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t

B. All input pulses have the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr = tf = 2 ns, duty cycle = 50%. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing.

Figure 3. Load Circuit and Voltage Waveforms

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VOLTAGE WAVEFORMS

dis

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TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

special design features

True CMOS Outputs: Each TICPAL22V10Z output is designed with a P-channel pull-up transistor and an

N-channel pull-down transistor, a true CMOS output with rail-to-rail output switching. This provides direct interface to CMOS logic, memory, or ASIC devices without the need for a pull-up resistor. The CMOS output has 16-mA drive capability , which makes the TICPAL22V10Z an ideal substitute for bipolar PLDs. The electrical characteristics of this device show the output under both CMOS and TTL conditions.

Simultaneous Switching: High-performance CMOS devices often have output glitches on nonswitched outputs when a large number of outputs are switched simultaneously. This glitch is commonly referred to as

(low-level output voltage). Ground bounce is

”ground bounce” and is most noticeable on outputs held at V caused by the voltage drop across the inductance in the package lead when current is switched (dv α I x di/dt).

One solution is to restrict the number of outputs that can switch simultaneously . Another solution is to change the device pinout such that the ground is located on a low-inductance package pin. TI opted for a third option in order to maintain pinout compatibility and eliminate functional constraints. This option controls the output transistor turn-on characteristics and puts a limit on the instantaneous current available to the load, much like the I

resistor in a TTL circuit.

Wake-Up Features: The TICP AL22V10Z employs input signal transition detection techniques to power up the device from the standby-power mode. The transition detector monitors all inputs, I/Os, and feedback paths. Whenever a transition is sensed, the detector activates the power-up mode. The device will remain in the power-up mode until the detector senses that the inputs and outputs have been static for about 40 ns; thereafter, the device returns to the standby mode.

T urbo Mode or Zero-Power Mode: When the turbo cell is programmed, the device will be set to the power-up mode. Therefore, the delay associated with its transition detection and power up will be eliminated. This is how the faster propagation delays and shorter setup times are obtained in the turbo mode. The turbo mode and the associated speed increase can be effectively simulated with the turbo cell erased, if a series of adjacent input, I/O, or feedback edges occur with an interval of about 25 ns or less between these adjacent edges. Under these conditions, the TICPAL22V10Z will never have the opportunity to power down due to the frequency of the adjacent edges.

Power Up: The TICP AL22V10Z device configuration bits (power mode, and macrocell configuration) are read at the first input transition after a monotonic power up. When completed, the TICP AL22V10Z is in its designed configuration. The use of an initializing device reset is necessary in applications where registered feedback is used to ensure the TICPAL22V10Z is in a known state at the beginning of system operation.

Power Dissipation: Power dissipation of the TICP AL22V10Z is defined by three contributing factors, and the total power dissipation is the sum of all three.

Standby Power: The product of V

and the standby ICC. The standby current is the reverse current

through the diodes that are reversed biased. This current is very small, and for circuits that remain in static condition for a long time, this low amount of current can become a major performance advantage.

Dynamic Power: The product of VCC and the dynamic current. This dynamic current flows through the device only when the transistors are switching from one logic level to the other. The total dynamic current for the TICPAL22V10Z is dependent upon the users’ configuration of the device and the operating frequency. Output loading can be a source of additional power dissipation.

Interface Power: The product of I

(interface) and VCC. The total interface power is dependent on the

number of inputs at the TTL VOH level. The interface power can be eliminated by the addition of a pull-up resistor.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 15

TICPAL22V10Z-25C, TICPAL22V10Z-30I

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

Even though power dissipation is a function of the user’s device configuration and the operating frequency, the TICPAL22V10Z is a lower powered solution than either the quarter-powered or half-powered bipolar devices. The virtually zero standby power feature makes the TICPAL22V10Z the device of choice for low-duty-cycle applications.

programming and erasability

Programming of the TICPAL22V10Z is achieved through floating-gate avalanche injection techniques. The charge trapped on the floating gate remains after power has been removed, allowing for the nonvolatility of the programmed data. The charge can be removed by exposure to light with wavelengths of less than 400 nm (4000 Å). The recommended erasure wavelength is 253.7 nm (2537 Å), with erasure time of 60 to 90 minutes, using a light source with a power rating of 12000 µW/cm

The TICP AL22V10Z is designed for programming endurance of 1000 write/erase cycles with a data retention of ten years. T o guarantee maximum data retention, the window on the device should be covered by an opaque label. The fluorescent light in a room can erase a unit in three years or, in the case of a direct sunlight, erasure can be complete in one week.

placed within 2.5 cm (one inch) of the device.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 16

TICPAL22V10Z-25C, TICPAL22V10Z-30I EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

TYPICAL CHARACTERISTICS

OUTPUT CURRENT

OUTPUT VOLTAGE

400

VCC = 5 V TA = 25°C

200

100

70 40

–I

– Output Current – mA

0123 5

VO – Output Voltage – V

Figure 4

1.4

= 25 °C

1.3

1.2

= 5 V,V

1.1

0.9

0.8

CL = 50 pF f Duty Cycle = 50%

0.7

Normalized Supply Current at

–50 –25 0

NORMALIZED SUPPLY CURRENT

FREE-AIR TEMPERATURE

(10-BIT COUNTER)

= 23.8 MHz

clock

25 50 75

TA – Free-Air Temperature – °C

Figure 5

VCC = 4.5 V VCC = 4.75 V VCC = 5 V VCC = 5.25 V VCC = 5.5 V

100

CLOCK FREQUENCY

100

VCC = 5 V TA = 25°C CL = 50 pF Duty cycle = 50%

– Supply Current – mA

Turbo Bit off

100 1 k 10 k 100 k

clock

SUPPLY CURRENT

(10-BIT COUNTER)

Turbo Bit on

1 M 10 M

– Clock Frequency – Hz

Figure 6

100 M

NORMALIZED PROPAGATION DELAY TIME

1.15

= 5 V

1.05

0.95

Normalized Propagation Delay Time at

CLK to Q and Turbo Mode

1.1

TA = 25 °C CL = 50 pF R1 = 300 Ω R2 = 390 Ω

0.9

4.5 5

SUPPLY VOLTAGE

Zero-Power Mode

4.75 VCC – Supply Voltage – V

Figure 7

5.25

5.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Page 17

TICPAL22V10Z-25C, TICPAL22V10Z-30I

EPIC CMOS PROGRAMMABLE ARRAY LOGIC CIRCUITS

SRPS007C – D3323, SEPTEMBER 1989 – REVISED FEBRUARY 1992

TYPICAL CHARACTERISTICS

CHANGE IN

NORMALIZED PROPAGATION DELAY TIME

FREE-AIR TEMPERATURE

1.2 VCC = 5 V

CL = 50 pF

= 25 °C

R1 = 300 Ω R2 = 390 Ω

1.1

PROPAGATION DELAY TIME

LOAD CAPACITANCE

VCC = 5 V TA = 25 °C R1 = 300 Ω R2 = 390 Ω

0.9

Normalized Propagation Delay Time at

0.8

–50 –25 0

= CLK to Q = Zero-Power Mode = Turbo Mode

25 50 75

TA – Free-Air Temperature –°C

Figure 8

PROPAGATION DELAY TIME

NUMBER OF OUTOUTS SWITCHING

1.5 VCC = 5 V

TA = 25 °C CL = 50 pF R1 = 300 Ω R2 = 390 Ω Registered Macrocell

100

CHANGE IN

Change in Propagation Delay Time – ns

0 100 200 300 400 500

CL – Load Capacitance – pF

Figure 9

PHL

PLH

600 700 800

0.5

Change in Propagation Delay Time – ns

1234567

Number of Outputs Switching

Figure 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PHL

PLH

8910

Page 18

Page 19

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TI Authorized North American Distributors

Alliance Electronics, Inc. (military product only) Almac/Arrow Anthem Electronics Arrow/Schweber Future Electronics (Canada) GRS Electronics Co., Inc. * Hall-Mark Electronics Marshall Industries Newark Electronics * Wyle Laboratories Zeus Components Rochester Electronics, Inc. (obsolete product only)

*Not authorized for TI military products

1992 T exas Instruments Incorporated

B0892

Page 20

TI North American Sales Offices

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TI Distributors

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NEW MEXICO: Alliance (505) 292-3360. NEW YORK: Long Island: Anthem (516) 864-6600;

Arrow/Schweber (516) 231-1000; Hall-Mark (516) 737-0600; Marshall (516) 273-2424; Zeus (914) 937-7400.

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TEXAS: Austin: Arrow/Schweber (512) 835-4180; Hall-Mark (512) 258-8848; Marshall (512) 837-1991; Wyle (512) 345-8853;

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Houston: Arrow/Schweber (713) 530-4700; Hall-Mark (713) 781-6100; Marshall (713) 467-1666; Wyle (713) 879-9953.

UTAH: Anthem (801) 973-8555; Arrow/Schweber (801) 973-6913; Marshall (801) 973-2288; Wyle (801) 974-9953.

WASHINGTON: Almac/Arrow (206) 643-9992, Anthem (206) 483-1700; Marshall (206) 486-5747; Wyle (206) 881-1150.

WISCONSIN: Arrow/Schweber (414) 792-0150; Hall-Mark (414) 797-7844; Marshall (414) 797-8400.

CANADA: Calgary: Future (403) 235-5325; Edmonton: Future (403) 438-2858; Montreal: Arrow/Schweber (514) 421-7411; Future (514)

694-7710; Marshall (514) 694-8142 Ottawa: Arrow/Schweber (613) 226-6903; Future (613) 820-8313.

Quebec: Future (418) 897-6666. Toronto: Arrow/Schweber (416) 670-7769;

Future (416) 612-9200; Marshall (416) 458-8046. Vancouver: Arrow/Schweber (604) 421-2333;

Future (604) 294-1166.

TI Die Processors

Chip Supply (407) 298-7100 Elmo Semiconductor (818) 768-7400 Minco T echnology Labs (512) 834-2022

Customer Response Center

TOLL FREE: (800) 336-5236 OUTSIDE USA: (214) 995-6611

(8:00 a.m. – 5:00 p.m. CST)

1992 T exas Instruments Incorporated

D0892

SRPS007C

Page 21

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.