The TIBP AL22V10-15BC is a programmable array logic device featuring high speed and functional equivalency
when compared to presently available devices. They are implemented with the familiar sum-of-products
(AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”. These
IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titaniumtungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
This device is covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SRPS009A – D3356, OCTOBER 1989 – REVISED JUNE 1990
description (continued)
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBP AL22V10-15BC of fers quick design and development of custom LSI functions with complexities of 500 to
800 equivalent gates. Since each of the ten output pins may be individually configured as inputs on either a
temporary or permanent basis, functions requiring up to 21 inputs and a single output or down to 12 inputs and
10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10-15BC is characterized for operation from 0°C to 75°C.
00Register feedbackRegisteredActive low
01Register feedbackRegisteredActive high
10I/O feedbackCombinational Active low
11I/O feedbackCombinational Active high
0 = unblown fuse, 1 = blown fuse
S1 and S0 are select-function fuses as shown in the output logic macrocell
diagram.
FEEDBACK AND OUTPUT CONFIGURATION
Figure 1. Resultant Macrocell Feedback and Output Logic After Programming
SRPS009A – D3356, OCTOBER 1989 – REVISED JUNE 1990
electrical characteristics over recommended operating free-air temperature range
PARAMETERTEST CONDITIONSMIN TYP†MAXUNIT
V
IK
V
OH
V
OL
I
OZH
I
OZL
I
I
I
IH
I
I
I
C
C
C
IL
OS
CC
i
o
clk
CLK–0.15
All others–0.1
‡
switching characteristicsover recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
§
f
max
t
pd
t
pd
t
pd
t
pd
t
en
t
dis
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
SRPS009A – D3356, OCTOBER 1989 – REVISED JUNE 1990
preload procedure for registered outputs (see Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1. With VCC at 5 V and pin 1 at VIL, raise pin 13 to V
IHH
.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower pin 13 to V
. Preload can be verified by observing the voltage level
IL
at the output pin.
V
V
V
V
V
V
IHH
IL
IH
IL
OH
OL
Pin 13
t
t
d
Pin 1
Registered I/OInputOutput
su
t
w
t
d
V
IH
V
IL
Figure 2. Preload Waveforms
NOTES: 2. Pin numbers shown are for the NT package only. If chip-carrier socket adapter is not used, pin numbers must be changed accordingly .
SRPS009A – D3356, OCTOBER 1989 – REVISED JUNE 1990
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
V
CC
Active High
Registered Output
Active Low
Registered Output
CLK
4 V
†
tpd
(600 ns typ, 1000 ns MAX)
State Unknown
State Unknown
1.5 V
1.5 V
1.5 V
tsu
t
w
‡
1.5 V
5 V
V
V
V
V
V
V
OH
OL
OH
OL
IH
IL
†
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
‡
This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming T exas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
SRPS009A – D3356, OCTOBER 1989 – REVISED JUNE 1990
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
Timing
Input
t
Data
Input
Input
t
pd
In-Phase
Output
t
pd
Out-of-Phase
Output
(see Note D)
PROPAGATION DELAY TIMES
1.5 V
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V1.5 V
1.5 V
1.5 V1.5 V
VOLTAGE WAVEFORMS
(see Note A)
t
h
1.5 V
3.5 V
0.3 V
3.5 V
0.3 V
(see Note B)
3.5 V
0.3 V
t
pd
V
1.5 V
V
t
pd
V
V
C
L
LOAD CIRCUIT FOR
3-STATE OUTPUTS
OH
OL
OH
OL
R2
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
1.5 V1.5 V
t
w
1.5 V1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V1.5 V
t
en
t
en
t
1.5 V
t
1.5 V
dis
dis
3.5 V
0.3 V
3.5 V
0.3 V
(see Note B)
3.5 V
0.3 V
(see Note B)
≈ 3.3 V
VOL + 0.5 V
V
OL
V
OH
VOH – 0.5 V
≈ 0 V
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t
B. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
SRPS009A – D3356, OCTOBER 1989 – REVISED JUNE 1990
TYPICAL CHARACTERISTICS
POWER DISSIPATION
PROPAGATION DELAY TIME
vs
NUMBER OF OUTOUTS SWITCHING
t
(I, I/O to O, I/O)
PHL
t
(I, I/O to O, I/O)
PLH
t
(CLK to Q)
PHL
1000
950
10–BIT COUNTER MODE
VCC = 5 V
R1 = 300 Ω
R2 = 390 Ω,
CL = 50 pF
vs
FREQUENCY
12
10
8
900
850
800
10
TA = 0°C
TA = 25°C
TA = 50°C
3050
F – Frequency – MHz
70
100
Power Dissipation – mWP
–
D
Figure 9
6
4
Propagation Delay Time – ns
–
2
pd
t
0
1234567
Number of Outputs Switching
Figure 10
t
PLH
(CLK to Q)
VCC = 5 V
R1 = 300 Ω
R2 = 390 Ω
CL = 50 pF
TA = 25 °C
8910
14
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