Datasheet TIBPAL20R8-5CNT, TIBPAL20R8-5CFN, TIBPAL20R8-7MWB, TIBPAL20R8-7MJTB, TIBPAL20R4-5CNT Datasheet (Texas Instruments)

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992



CIRCUITS

• High-Performance Operation:

f

(no feedback)

max

TIBPAL20R’ -5C Series . . . 125 MHz Min TIBPAL20R’ -7M Series . . . 100 MHz Min

f

(internal feedback)

max

TIBPAL20R’ -5C Series . . . 125 MHz Min TIBPAL20R’ -7M Series . . . 100 MHz Min

f

(external feedback)

max

TIBPAL20R’ -5C Series . . . 117 MHz Min TIBPAL20R’ -7M Series . . . 74 MHz Min

Propagation Delay

TIBPAL20L8-5C Series . . . 5 ns Max TIBPAL20L8-7M Series . . . 7 ns Max TIBPAL20R’ -5C Series

(CLK-to-Q) . . . 4 ns Max

TIBPAL20R’ -7M Series

(CLK-to-Q) . . . 6.5 ns Max

• Functionally Equivalent, but Faster Than,

Existing 24-Pin PLDs

• Preload Capability on Output Registers

Simplifies Testing

• Power-Up Clear on Registered Devices (All

Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High)

TIBPAL20L8’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

NC

24 23 22 21 20 19 18 17 16 15 14 13

V

CC

V I O I/O I/O I/O I/O I/O I/O O I I

I

CC

O

I

1

I

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

11

GND

C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE

12

TIBPAL20L8’

(TOP VIEW)

I

• Package Options Include Both Plastic and

Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs

• Security Fuse Prevents Duplication

DEVICE

PAL20L8 14 2 0 6 PAL20R4 12 0 4 (3-state buffers) 4 PAL20R6 12 0 6 (3-state buffers) 2 PAL20R8 12 0 8 (3-state buffers) 0

I

INPUTS

description

3-STATE

O OUTPUTS

REGISTERED

Q OUTPUTS

I/O

PORT

S

I I I

NC

I I I

NC

– No internal connection

Pin assignments in operating mode

3212827

426

5 6 7 8 9

10

11

12 13

14 15 16 17 18

I

GND

NC

I

25 24 23 22 21 20 19

O

I/O I/O I/O NC I/O I/O I/O

These programmable array logic devices feature high speed and functional equivalency when compared with currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically results in a more compact circuit board.

The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for operation over the full military temperature range of –55°C to 125°C.

These devices are covered by U.S. Patent 4,410,987. IMPACT-X is a trademark of Texas Instruments Incorporated. PAL is a registered trademark of Advanced Micro Devices Inc.

This document contains information on products in more than one phase of development. The status of each device is indicated on the page(s) specifying its electrical characteristics.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1992, Texas Instruments Incorporated

1

TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992



CIRCUITS

TIBPAL20R4’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

24 23 22 21 20 19 18 17 16 15 14 13

V I I/O

I/O Q Q Q Q I/O I/O I OE

V I

I/O Q Q Q Q Q Q I/O I OE

CC

1

CLK

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

11

I

12

GND

TIBPAL20R6’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

1

CLK

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

11

I

12

GND

TIBPAL20R4’ C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE

(TOP VIEW)

CC

I

4

3 2 1 282726

5 I/O

I

6

I

7

I

8

NC

9

I

10

I

11

I

12 13 14 15 16 17 18

I

TIBPAL20R6’ C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE

(TOP VIEW)

I

4

3 2 1 282726

5Q

I

6

I

7

I

8

NC

9

I

10

I

11 19

I

12 13 14 15 16 17 18

I

V

CLKNCI

NC

OE

GND

CC

V

CLKNCI

OE

NC

GND

I/O

25

Q

24

Q

23

NC

22

Q

21

Q

20 19

I/O

I

I/O

25

Q

24

Q

23

NC

22

Q

21

Q

20

Q

I

I/O

TIBPAL20R8’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

1

CLK

2

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I

11

I

12

GND

Pin assignments in operating mode

2

24 23 22 21 20 19 18 17 16 15 14 13

V

CC I Q Q Q

Q Q Q Q Q I OE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL20R8’ C SUFFIX . . . FN PACKAGE M SUFFIX . . . FK PACKAGE

(TOP VIEW)

I

4

3 2 1 282726

5Q

I

6

I

7

I

8

NC

9

I

10

I

11 19

I

12 13 14 15 16 17 18

I

NC – No internal connection

CC

CLKNCI

V

OE

NC

GND

Q

25

Q

24

Q

23

NC

22

Q

21

Q

20

Q

I

Q

functional block diagrams (positive logic)

TIBPAL20L8-5C, TIBPAL20R4-5C

TIBPAL20L8-7M, TIBPAL20R4-7M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

TIBPAL20L8’



CIRCUITS

OE

CLK

14 20

I

20 x

&

40 X 64

206

TIBPAL20R4’

7

6

EN

≥1

O

I/O

EN 2

C1

denotes fused inputs

12 20

I

4

20 x

1D

I = 0

2

Q

I/O

&

40 X 64

204

8

7

4

≥1

EN

4

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3

TIBPAL20R6-5C, TIBPAL20R8-5C TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

functional block diagrams (positive logic)



CIRCUITS

TIBPAL20R6’

OE

CLK

12 20

I

6

20 x

EN 2

C1

1D

I = 0

2

Q

I/O

&

40 X 64

202

8

7

2

≥1

EN

6

CLK

denotes fused inputs

OE

12 20

I

20 x

TIBPAL20R8’

EN 2

C1

1D

I = 0

2

Q

&

40 X 64

208

8

≥1

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1

I

HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

Increment

TIBPAL20L8-5C

TIBPAL20L8-7M



CIRCUITS

2

I

First Fuse Numbers

120 160 200 240 280

3

I

320 360 400 440 480 520 560 600

4

I

640 680 720 760 800 840 880 920

5

I

960 1000 1040 1080 1120 1160 1200 1240

6

I

1280 1320 1360 1400 1440 1480 1520 1560

7

I

1600 1640 1680 1720 1760 1800 1840 1880

8

I

1920 1960 2000 2040 2080 2120 2160 2200

9

I

2240 2280 2320 2360 2400 2440 2480 2520

10

I

11

I

4 8 12 16 20 24 28 32

0 40 80

36 390

23

I

22

O

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O

16

I/O

15

O

14

I

13

I

Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.

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5

TIBPAL20R4-5C TIBPAL20R4-7M HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

logic diagram (positive logic)

1

CLK

Increment



CIRCUITS

2

I

First Fuse Numbers

0 40 80

120 160 200 240 280

3

I

320 360 400 440 480 520 560 600

4

I

640 680 720 760 800 840 880 920

5

I

960 1000 1040 1080 1120 1160 1200 1240

6

I

1280 1320 1360 1400 1440 1480 1520 1560

7

I

1600 1640 1680 1720 1760 1800 1840 1880

8

I

1920 1960 2000 2040 2080 2120 2160 2200

9

I

2240 2280 2320 2360 2400 2440 2480 2520

10

I

11

I

Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.

4 8 12 16 20 24 28 32

36 390

23

I

22

I/O

21

I/O

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

20

19

18

17

16

15

14

13

Q

I/O

I

OE

6

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logic diagram (positive logic)

1

CLK

HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

Increment

TIBPAL20R6-5C

TIBPAL20R6-7M



CIRCUITS

2

I

First Fuse Numbers

0 40 80

120 160 200 240 280

3

I

320 360 400 440 480 520 560 600

4

I

640 680 720 760 800 840 880 920

5

I

960 1000 1040 1080

1120

1160 1200 1240

6

I

1280 1320 1360 1400 1440 1480 1520 1560

7

I

1600 1640 1680 1720 1760 1800 1840 1880

8

I

1920 1960 2000 2040 2080 2120 2160 2200

9

I

2240 2280 2320 2360 2400 2440 2480 2520

10

I

11

I

Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.

4 8 12 16 20 24 28 32

36 390

23

I

22

I/O

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

21

20

19

18

17

16

15

14

13

Q

I/O

I

OE

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7

TIBPAL20R8-5C TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

logic diagram (positive logic)

1

CLK

Increment



CIRCUITS

2

I

First Fuse Numbers

0 40 80

120 160 200 240 280

3

I

320 360 400 440 480 520 560 600

4

I

640 680 720 760 800 840 880 920

5

I

960 1000 1040 1080

1120

1160 1200 1240

6

I

1280 1320 1360 1400 1440 1480 1520 1560

7

I

1600 1640 1680 1720 1760 1800 1840 1880

8

I

1920 1960 2000 2040 2080 2120 2160 2200

9

I

2240 2280 2320 2360 2400 2440 2480 2520

10

I

11

I

Fuse number = First fuse number + Increment Pin numbers shown are for JT and NT packages.

4 8 12 16 20 24 28 32

36 390

23

I

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

I = 0

1D

C1

22

21

20

19

18

17

16

15

14

13

Q

I

OE

8

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TIBPAL20L8-5C

HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

V

IH

V

IL

I

OH

I

OL

T

A

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

Supply voltage 4.75 5 5.25 V High-level input voltage (see Note 2) 2 5.5 V Low-level input voltage (see Note 2) 0.8 V High-level output current –3.2 mA Low-level output current 24 mA Operating free-air temperature 0 25 75 °C

noise. Testing these parameters should not be attempted without suitable equipment.



CIRCUITS

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

‡

I

OZH

‡

I

OZL

I

‡

I

IH

‡

I

IL

§

I

OS

I

CC

C

i

C

o

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

I/O leakage is the worst case of I

§

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.

VCC = 4.75 V, II = –18 mA –0.8 –1.5 V VCC = 4.75 V, IOH = –3.2 mA 2.4 2.7 V VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V VCC = 5.25 V, VO = 2.7 V 100 µA VCC = 5.25 V, VO = 0.4 V –100 µA VCC = 5.25 V, VI = 5.5 V 100 µA VCC = 5.25 V, VI = 2.7 V 25 µA VCC = 5.25 V, VI = 0.4 V –250 µA VCC = 5.25 V, VO = 0.5 V –30 –70 –130 mA VCC = 5.25 V, VI = 0, Outputs open 210 mA f = 1 MHz, VI = 2 V 8.5 pF f = 1 MHz, VO = 2 V 10 pF

and IIL or I

OZL

and IIH, respectively.

OZH

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

FROM

(INPUT)

I, I/O O, I/O

t

pd

t

en

t

dis

I, I/O O, I/O I, I/O O, I/O 2 7 2 7 ns

I, I/O O, I/O 2 7 2 7 ns

TO

(OUTPUT)

with up to 4 outputs switching

with more than 4 outputs switching

TEST

CONDITIONS

R1 = 200 Ω, R2 = 200 Ω, See Figure 8

TIBPAL20L8-5CFN

MIN MAX MIN MAX

1.5 5 1.5 5

1.5 5 1.5 5.5

TIBPAL20L8-5CJT TIBPAL20L8-5CNT

UNITPARAMETER

ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

TIBPAL20R4-5C, TIBPAL20R6-5C HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

V

CC

V

IH

V

IL

I

OH

I

OL

f

clock w

t

su

t

h

T

A

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

Supply voltage 4.75 5 5.25 V High-level input voltage (see Note 2) 2 5.5 V Low-level input voltage (see Note 2) 0.8 V High-level output current –3.2 mA Low-level output current 24 mA Clock frequency 0 125 MHz

Pulse duration, clockt Setup time, input or feedback before clock↑ 4.5 ns

Hold time, input or feedback after clock↑ 0 ns Operating free-air temperature 0 25 75 °C

noise. Testing these parameters should not be attempted without suitable equipment.



CIRCUITS

High 4 Low 4

MIN NOM MAX UNIT

ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL20R4-5C, TIBPAL20R6-5C

HIGH-PERFORMANCE IMPACT -X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

I

OZH

I

OZL

I

IH

I

IL

I

OS

I

CC

C

‡

§

i

o

I 8.5 CLK/OE 7.5 I/O 10 Q 7

VCC = 4.75 V, II = –18 mA –0.8 –1.5 V VCC = 4.75 V, IOH = –3.2 mA 2.4 2.7 V VCC = 4.75 V, IOL = 24 mA 0.3 0.5 V VCC = 5.25 V, VO = 2.7 V 100 µA VCC = 5.25 V, VO = 0.4 V –100 µA VCC = 5.25 V, VI = 5.5 V 100 µA VCC = 5.25 V, VI = 2.7 V 25 µA VCC = 5.25 V, VI = 0.4 V –250 µA VCC = 5.25 V, VO = 0.5 V –30 –70 –130 mA VCC = 5.25 V, VI = 0, Outputs open 210 mA

VI = 2 Vf = 1 MHz,

f = 1 MHz,

VO = 2 V



CIRCUITS

pF

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TIBPAL20R4-5CJT

FROM

(INPUT)

without feedback 125 125

¶

f

max

t

pd

t

pd

t

pd

t

en

t

dis

t

en

t

dis

t

r

t

f

t

sk(o)

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

I/O leakage is the worst case of I

§

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.

¶

See ’f

max

#

t

is the skew time between registered outputs.

sk(o)

with internal feedback (counter configuration) 125 125 MHz

with external feedback 117 111 CLK↑ Q 1.5 4 1.5 4.5 ns CLK↑ Internal feedback R1 = 200 Ω, 3.5 3.5 ns

I, I/O I/O R2 = 200 Ω, 1.5 5 1.5 5 ns

OE↓ Q See Figure 8 1.5 6 1.5 6 ns

OE↑ Q 1 6.5 1 7 ns I, I/O I/O 2 7 2 7 ns I, I/O I/O 2 7 2 7 ns

#

Specification’ near the end of this data sheet.

Skew between registered outputs 0.5 0.5 ns

and IIL or I

OZL

TO

(OUTPUT)

and IIH, respectively.

OZH

TEST

CONDITIONS

TIBPAL20R4-5CFN TIBPAL20R6-5CFN

MIN TYP†MAX MIN TYP†MAX

1.5 1.5 ns

TIBPAL20R4-5CNT

TIBPAL20R6-5CJT

TIBPAL20R6-5CNT

UNITPARAMETER

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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11

TIBPAL20R8-5C HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

V

CC

V

IH

V

IL

I

OH

I

OL

f

clock w

t

su

t

h

T

A

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

Supply voltage 4.75 5 5.25 V High-level input voltage (see Note 2) 2 5.5 V Low-level input voltage (see Note 2) 0.8 V High-level output current –3.2 mA Low-level output current 24 mA Clock frequency 0 125 MHz

Pulse duration, clockt Setup time, input or feedback before clock↑ 4.5 ns

Hold time, input or feedback after clock↑ 0 ns Operating free-air temperature 0 25 75 °C

noise. Testing these parameters should not be attempted without suitable equipment.



CIRCUITS

High 4 Low 4

MIN NOM MAX UNIT

ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL20R8-5C

HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS UNIT

V

IK

V

OH

V

OL

I

OZH

I

OZL

I

IH

I

IL

I

OS

I

CC

i

C

o

‡

I 8.5 6.5 CLK/OE 7.5 5.5

VCC = 4.75 V, II = –18 mA –0.8 –1.5 –0.8 –1.5 V VCC = 4.75 V, IOH = –3.2 mA 2.4 2.7 2.4 2.7 V VCC = 4.75 V, IOL = 24 mA 0.3 0.5 0.3 0.5 V VCC = 5.25 V, VO = 2.7 V 100 100 µA VCC = 5.25 V, VO = 0.4 V –100 –100 µA VCC = 5.25 V, VI = 5.5 V 100 100 µA VCC = 5.25 V, VI = 2.7 V 25 25 µA VCC = 5.25 V, VI = 0.4 V –250 –250 µA VCC = 5.25 V, VO = 0.5 V –30 –70 –130 –30 –70 –130 mA VCC = 5.25 V, VI = 0, Outputs open 210 210 mA

VI = 2 Vf = 1 MHz,C

f = 1 MHz, VO = 2 V 10 8 pF

TIBPAL20R8-5CFN

MIN TYP†MAX MIN TYP†MAX

TIBPAL20R8-5CJT

TIBPAL20R8-5CNT



CIRCUITS

pF

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

FROM

(INPUT)

without feedback 125 125

§

f

max

t

pd

¶

t

pd

t

en

t

dis

t

r

t

f

t

sk(o)

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.

§

See ’f

max

¶

This parameter is calculated from the measured f

#

t

is the skew time between registered outputs.

sk(o)

with internal feedback (counter configuration) 125 125 MHz

with external feedback 117 111

CLK↑ Q

CLK↑ Q CLK↑ Internal feedback 3.5 3.5 ns

OE↓ Q 1.5 6 1.5 6 ns OE↑ Q 1 6.5 1 7 ns

#

Specification’ near the end of this data sheet.

Skew between outputs 0.5 0.5 ns

TO

(OUTPUT)

with up to 4 outputs switching

with more than 4 outputs switching

with internal feedback in a counter configuration (see Figure 4 for illustration).

max

TEST

CONDITIONS

R1 = 200 Ω, R2 = 200 Ω, See Figure 8

TIBPAL20R8-5CFN

MIN TYP†MAX MIN TYP†MAX

1.5 4 1.5 4

1.5 4 1.5 4.5

1.5 1.5 ns

TIBPAL20R8-5CJT

TIBPAL20R8-5CNT

UNITPARAMETER

ns

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.

recommended operating conditions

V

CC

V

IH

V

IL

I

OH

I

OL

f

clock

†

w

†

t

su

†

t

h

T

A

†

f

clock

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

Supply voltage 4.5 5 5.5 V High-level input voltage (see Note 2) 2 5.5 V Low-level input voltage (see Note 2) 0.8 V High-level output current –2 mA Low-level output current 12 mA

†

Clock frequency 0 100 MHz Pulse duration, clockt

Setup time, input or feedback before clock↑ 7 ns Hold time, input or feedback after clock↑ 0 ns

Operating free-air temperature –55 25 125 °C

, tw, tsu, and th do not apply to TIBPAL16L8’

noise. Testing these parameters should not be attempted without suitable equipment.



CIRCUITS

High 5 Low 5

MIN NOM MAX UNIT

ns

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

V

OH

V

OL

I

OZH

I

OZL

I

IH

I

IL

I

OS

I

CC

i

C

o

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to avoid test problems caused by test equipment ground degradation.

0, Q outputs 20 I/O ports 100 0, Q outputs –20 I/O ports –250

I/O ports 100 All others 25

‡

I 8.5 CLK/OE 7.5

VCC = 4.5 V, II = –18 mA –0.8 –1.5 V VCC = 4.5 V, IOH = –2 mA 2.4 2.7 V VCC = 4.5 V, IOL = 12 mA 0.25 0.5 V

VCC = 5.5 V,

VCC = 5.5 V, VI = 5.5 V 1 mA

VCC = 5.5 V,

VCC = 5.5 V, VI = 0.4 V –250 µA VCC = 5.5 V, VO = 0.5 V –30 –70 –130 mA VCC = 5.5 V, VI = GND, OE = VIH, Outputs open 220 mA

f = 1 MHz, VO = 2 V 10 pF

VO = 2.7 V

VO = 0.4 V

VI = 2 Vf = 1 MHz,C



CIRCUITS

µA

µAVI = 2.7 V

pF

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

§

f

max

t

pd

t

pd

t

en

t

dis

t

en

t

dis

§

See ’f and is calculated from the equation found in the f

Specification’ near the end of this data sheet. f

max

FROM

(INPUT)

without feedback 100

with internal feedback

(counter configuration)

with external feedback R1 = 390 Ω, 74

I, I/O O, I/O R2 = 750 Ω, 1 7 ns

CLK Q See Figure 8 1 7 ns OE↓ Q 1 8 ns OE↑ Q 1 10 ns I, I/O O, I/O 1 9 ns I, I/O O, I/O 1 10 ns

TO

(OUTPUT)

does not apply for TIBPAL20L8 ′. f

max

specifications section.

max

TEST CONDITION MIN MAX UNIT

100 MHz

with external feedback is not production tested

max

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

programming information

Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming T exas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.

asynchronous preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below.

Step 1. With V Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Step 3. Lower Pin 13 to 5 V. Step 4. Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the

voltage level at the output pin.

at 5 volts and Pin 1 at VIL, raise Pin 13 to V

CC



CIRCUITS

IHH

.

Pin 13

t

d

Registered Output

Figure 1. Asynchronous Preload Waveforms

NOTE 3: td = tsu = th = 100 ns to 1000 ns, V

= 10.25 V to 10.75 V

IHH

tsu + t

V

IHH

5 V

V

IL

t

h

d

V

IH

OutputInput

V

IL

V

OH

V

OL

16

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TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

1.5 V



CIRCUITS

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

power-up reset, see Figure 2

Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and feedback setup times are met.

V

CC

Active Low

Registered Output

Clock

4 V

†

t

pd

(600 ns typ, 1000 ns MAX)

1.5 V

t

w

‡

t

su

5 V

V

OH

OL

IH

IL

†

This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.

‡

This is the setup time for input or feedback.

Figure 2. Power-Up Reset Waveforms

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17

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

without feedback, see Figure 3

f

max

In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback. Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t However, the minimum fmax is determined by the minimum clock period (t

f

Thus,

without feedback

max

+

(twhigh



CIRCUITS

f

SPECIFICATIONS

max

1

)

twlow)

CLK

or

1

(tsu)

th)

high + tw low).

w

.

su

+ th).

f

with internal feedback, see Figure 4

max

Logic Array

tsu + t

tw high + tw low

Figure 3. f

h

or

Without Feedback

max

C1

1D

This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.

Thus,

f

with internal feedback

max

+

(tsu)

1

tpdCLK*to*FB)

.

Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.

CLK

Logic Array

C1

18

1D

t

su

Figure 4. f

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

With Internal Feedback

max

tpd CLK-to-FB

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

f

SPECIFICATIONS

max

with external feedback, see Figure 5

f

max

This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals

+ tpd CLK-to-Q).

(t

su

Thus,

f

with external feedback

max

+

CLK

(tsu)

1

tpdCLK*to*Q)

.



CIRCUITS

Logic Array

t

su

Figure 5. f

C1

1D

tpd CLK-to-Q t

With External Feedback

max

Next Device

su

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19

TIBPAL20R8-5C HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

THERMAL INFORMATION

thermal management of the TIBPAL20R8-5C

Thermal management of the TIBPAL20R8-5CNT and TIBPAL20R8-5CFN is necessary when operating at certain conditions of frequency , output loading, and outputs switching simultaneously. The device and system application will determine the appropriate level of management.



CIRCUITS

Determining the level of thermal management is based on factors such as power dissipation (P

), ambient

D

temperature (TA), and transverse airflow (FPM). Figures 6 (a) and 6 (b) show the relationship between ambient temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be determined at a particular ambient temperature and device power dissipation level in order to ensure the device specifications.

Figure 7 illustrates how power dissipation varies as a function of frequency and the number of outputs switching simultaneously . It should be noted that all outputs are fully loaded (C

= 50 pF). Since the condition of eight fully

L

loaded outputs represents the worst-case condition, each application must be evaluated accordingly.

1000

800

600

400

MINIMUM TRANSVERSE AIR FLOW

vs

AMBIENT TEMPERATURE

PD = 1.6 W PD = 1.4 W PD = 1.2 W

PD = 1 W PD = 0.8 W PD = 0.6 W

1000

800

600

400

MINIMUM TRANSVERSE AIR FLOW

vs

AMBIENT TEMPERATURE

PD = 1.6 W PD = 1.4 W PD = 1.2 W

PD = 1 W PD = 0.8 W PD = 0.6 W

200

Minimum Transverse Air Flow – ft/min

0

30

4020100

TA – Ambient Temperature –°C

(a) TIBPAL20-5CNT

60 70

8050

Figure 6

200

Minimum Transverse Air Flow – ft/min

0

30

402010

TA – Ambient Temperature –°C

(b) TIBPAL20R8-5CFN

60 70

8050

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THERMAL INFORMATION

POWER DISSIPATION

1800

VCC = 5 V TA = 25 °C CL = 50 pF

1600

8 Outputs Switching

1400

1200

1000

– Power Dissipation – mW

D

P

800

7 Outputs Switching 6 Outputs Switching 5 Outputs Switching 4 Outputs Switching 3 Outputs Switching 2 Outputs Switching

1 Output Switching

TIBPAL20R8-5C

HIGH-PERFORMANCE IMPACT-X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

vs

FREQUENCY



CIRCUITS

600

1 4 10 40 100

2 20 200

f – Frequency – MHz

Figure 7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test



CIRCUITS

5 V

S1

R1

Test

Point

Timing

Input

Data

Input

In-Phase

Output

Out-of-Phase

Output

(see Note D)

1.5 V

t

su

1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

t

pd 80 % 20 %

t

pd

20 % 80 %

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

1.5 V

1.5 V 1.5 V

1.5 V

t

r

t

f

(see Note A)

t

h

t

pd

1.5 V t

f

t

pd

t

r

C

L

LOAD CIRCUIT FOR

3-STATE OUTPUTS

3 V

0

3 V

0 (see Note B)

3 V

0

V

OH

V

OL

V

OH

V

OL

R2

High-Level

Pulse

Low-Level

Pulse

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note C)

Waveform 2

S1 Open

(see Note C)

1.5 V 1.5 V

t

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

t

en

t

en

t

1.5 V

t

dis

3 V

0

w

3 V

0 (see Note B)

3 V

0 (see Note B)

≈ 2.7 V

VOL + 0.5 V

V

OL

V

OH

VOH – 0.5 V

≈ 0 V

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t

B. All input pulses have the following characteristics: For C suffix, PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%; For M suffix,

PRR ≤ 10 MHz, tr = tf ≤ 2 ns, duty cycle = 50%

C. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control. D. When measuring propagation delay times of 3-state outputs, switch S1 is closed. E. Equivalent loads may be used for testing.

Figure 8. Load Circuit and Voltage Waveforms

22

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VOLTAGE WAVEFORMS

.

dis

TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

C1



CIRCUITS

HIGH-PERFORMANCE IMPACT -X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

metastable characteristics of TIBPAL20R4-5C, TIBPAL20R6-5C, and TIBPAL20R8-5C

At some point a system designer is faced with the problem of synchronizing two digital signals operating at two different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop can influence overall system reliability.

Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said to be in the metastable state if the output hangs up in the region between V lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum propagation delay time (CLK to Q max).

From a system engineering standpoint, a designer cannot use the specified data sheet maximum for propagation delay time when using the flip-flop as a data synchronizer – how long to wait after the specified data sheet maximum must be known before using the data in order to guarantee reliable system operation.

The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and ∆t for a selected flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V , the comparators are in opposite states. When the Q output of the DUT is higher than 2 V or lower than 0.8 V , the comparators are at the same logic level. The outputs of the two comparators are sampled a selected time (∆t) after SCLK. The exclusive OR gate detects the occurrence of a failure and increments the failure counter.

1D

DUT

C1

V

IH

Comparator

V

IL

Comparator

1D

C1

1D

C1

Noise

Generator

Data in

SCLK

and VIH. This metastable condition

IL

1D

MTBF

Counter

+

SCLK + ∆t

Figure 9. Metastable Evaluation Test Circuit

In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10. Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.

Data

SCLK

SCLK + ∆t

MTBF

t

rec

Time (sec)

+

# Failures

= ∆t – CLK to Q (max)

∆t

Figure 10. Timing Diagram

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23

TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C HIGH-PERFORMANCE IMPACT -X PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

By using the described test circuit, MTBF can be determined for several different values of ∆t (see Figure 9). Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop. Figure 11 shows the results for the TIBPAL20’-5C operating at 1 MHz.

9

10 10 10 10 10

MTBF (s)

10 10 10 10

10 yr

8

1 yr

7

1 mo

6

1 wk

5

1 day

4

1 hr

3 2

1 min 10 s

1

0 10203040506070



CIRCUITS

∆t (ns)

f

clk

f

data

= 1 MHz

= 500 kHz

Figure 11. Metastable Characteristics

From the data taken in the above experiment, an equation can be derived for the metastable characteristics at other clock frequencies.

The metastable equation:

1

MTBF

+

f

SCLK

xf

data

xC1e

(*C2 xDt)

The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data,

–3

these constants can be solved for: C1 = 4.37 X 10

and C2 = 2.01

Therefore

MTBF

1

+

f

SCLK

xf

x4.37x10

data

*

3e(*2.01 xDt)

definition of variables

DUT (Device Under Test): The DUT is a 5-ns registered PLD programmed with the equation Q : = D. MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a

violation of the device specifications. f

(system clock frequency): Actual clock frequency for the DUT.

SCLK

f

(data frequency): Actual data frequency for a specified input to the DUT.

data

C1: Calculated constant that defines the magnitude of the curve. C2: Calculated constant that defines the slope of the curve. t

(metastability recovery time): Minimum time required to guarantee recovery from metastability , at a given

rec

MTBF failure rate. t ∆t: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.

= ∆t – tpd (CLK to Q, max)

rec

The test described above has shown the metastable characteristics of the TIBP AL20R4/R6/R8-5C series. For additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI Applications publication SDAA004, ”Metastable Characteristics, Design Considerations for ALS, AS, and LS Circuits.’’

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

TYPICAL CHARACTERISTICS



CIRCUITS

LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

20

VCC = 5 V TA = 25 °C

15

10

5

0

–5

–10

– Low-Level Output Current – mA

OL

I

–15

–20

–0.8 –0.6 –0.4 –0.2 0 0.2

VOL – Low-Level Output Voltage – V

Figure 12

0.4 0.6 0.8

HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

0

VCC = 5 V

–10

TA = 25 °C –20

–30

–40 –50

–60 –70

– High-Level Output Current – mA

–80

OH

I

–90

–100

0 0.5 1 1.5 2 2.5

VOH – High-Level Output Voltage – V

Figure 13

3

SUPPLY CURRENT

FREE-AIR TEMPERATURE

220

200

180

160

140

– Supply Current – mA

CC

I

120

100

–75 –50 –25 0 25 50

TA – Free-Air Temperature – °C

Figure 14

vs

VCC = 5.5 V VCC = 5.25 V

VCC = 4.5 V VCC = 4.75 V VCC = 5 V

75 100 125

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

TYPICAL CHARACTERISTICS

POWER DISSIPATION

vs

FREQUENCY

8-BIT COUNTER MODE

1100

VCC = 5 V

1000

TA = 80 °C



CIRCUITS

PROPAGATION DELAY TIME

6

TA = 25 °C CL = 50 pF R1 = 200 Ω

5

R2 = 200 Ω 1 Output Switching

SUPPLY VOLTAGE

vs

900

– Power Dissipation – mW

D

800

P

700

TA = 25 °C

TA = 0 °C

TA = 80 °C

2 20 200

1 4 10 40 100

f – Frequency – MHz

TA = 0 °C

Figure 15

PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

6

VCC = 5 V CL = 50 pF R1 = 200 Ω

5

R2 = 200 Ω 1 Output Switching

4

t

3

2

Propagation Delay Time – ns

1

0

PLH

t

(CLK to Q)

PLH

4.5 4.75 5

PROPAGATION DELAY TIME

16

VCC = 5 V TA = 25 °C

14

R1 = 200 Ω R2 = 200 Ω

1 Output Switching

12

t

(I, I/O to O, I/O)

PHL

(I, I/O to O, I/O)

t

(CLK to Q)

PHL

VCC – Supply Voltage – V

Figure 16

vs

LOAD CAPACITANCE

5.25 5.5

26

4

t

(I, I/O to O, I/O)

PHL

3

t

(I, I/O to O, I/O)

PLH

2

t

(CLK to Q)

PLH

Propagation Delay Time – ns

1

0

–75 –50 –25 0 25 50

TA – Free-Air Temperature – °C

Figure 17

t

(CLK to Q)

PHL

75 100 125

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t

(I, I/O to O, I/O)

10

8

t

PHL

6

4

Propagation Delay Time – ns

2

0

0 600

PHL

(CLK to Q)

t

(I, I/O to O, I/O)

PLH

t

(CLK to Q)

PLH

100 200 300 400

CL – Load Capacitance – pF

Figure 18

500

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C

TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M

HIGH-PERFORMANCE IMPACT-X  PAL

SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992

TYPICAL CHARACTERISTICS



CIRCUITS

SKEW BETWEEN OUTPUTS

vs

NUMBER OF OUTPUTS SWITCHING

0.8 VCC = 5 V TA = 25 °C

0.7

R1 = 200 Ω R2 = 200 Ω CL = 50 pF

0.6 8-Bit Counter

0.5

0.4

Outputs Switching in the Opposite Direction

0.3

0.2

– Skew Between Outputs Switching – ns

0.1

sk(o)

t

0

Outputs Switching in the Same Direction

23 4 56

Number of Outputs Switching

Figure 19

78

PROPAGATION DELAY TIME

NUMBER OF OUTPUTS SWITCHING

6

VCC = 5 V TA = 25 °C CL = 50 pF

5

R1 = 200 Ω R2 = 200 Ω

4

3

2

= t

(I, I/O to O, I/O)

Propagation Delay Time – ns

1

0

12345

PHL

= t

(I, I/O to O, I/O)

PLH

= t

(CLK to Q)

PHL

= t

(CLK to Q)

PLH

Number of Outputs Switching

Figure 20

vs

678

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

27

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1992 T exas Instruments Incorporated

D0892

SRPS010F

IMPORTANT NOTICE

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Datasheet TIBPAL20R8-5CNT, TIBPAL20R8-5CFN, TIBPAL20R8-7MWB, TIBPAL20R8-7MJTB, TIBPAL20R4-5CNT Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual