Datasheet TIBPAL20R8-7CFN, TIBPAL20R8-7CNT, TIBPAL20L8-10MWB, TIBPAL20L8-10MJTB, TIBPAL20L8-10MFKB Datasheet (Texas Instruments)

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C

TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all
parameters.

• High-Performance Operation:

f

max

(no feedback)
TIBPAL20R’ -7C Series . . . 100 MHz
TIBPAL20R’ -10M Series . . . 62.5 MHz

f

max

(internal feedback)
TIBPAL20R’ -7C Series . . . 100 MHz
TIBPAL20R’ -10M Series . . . 62.5 MHz

f

max

(external feedback)
TIBPAL20R’ -7C Series . . . 74 MHz
TIBPAL20R’ -10M Series . . . 50 MHz

Propagation Delay

TIBPAL20L8-7C Series . . . 7 ns Max
TIBPAL20L8-10M Series . . . 10 ns Max

• Functionally Equivalent, but Faster Than

Existing 24-Pin PLD Circuits

• Preload Capability on Output Registers

Simplifies T esting

• Power-Up Clear on Registered Devices (All

Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)

• Package Options Include Both Plastic and

Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs

• Security Fuse Prevents Duplication

• Dependable Texas Instruments Quality and

Reliability

DEVICE

I

INPUTS

3-STATE

O OUTPUTS

REGISTERED

Q OUTPUTS

I/O

PORT

S

PAL20L8 14 2 0 6
PAL20R4 12 0 4 (3-state buffers) 4
PAL20R6 12 0 6 (3-state buffers) 2
PAL20R8 12 0 8 (3-state buffers) 0

description

These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board. In addition, chip carriers are available for futher reduction in board
space.

All of the register outputs are set to a low level during power-up. Extra circuitry has been provided to allow loading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.

The TIBPAL20’ C series is characterized from 0°C to 75°C. The TIBPAL20’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.

These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

I
I
I
I
I
I
I
I
I
I
I

GND

V

CC

I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I

TIBPAL20L8’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

3212827

12 13

5
6
7
8
9
10
11

25
24
23
22
21
20
19

I/O
I/O
I/O
NC
I/O
I/O
I/O

I
I
I

NC

I
I
I

426

14 15 16 17 18

I

I

GND

NC

I

I

O

I

I

I

NC

I

O

TIBPAL20L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE

(TOP VIEW)

NC

– No internal connection

Pin assignments in operating mode

V

CC

TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2

CLK

I
I
I
I
I
I
I
I
I
I

GND

I
I/O
I/O
Q
Q
Q
Q
I/O
I/O
I

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

V

CC

OE

TIBPAL20R4’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

I

I

GND

NC

I

I/O

I

I

CLKNCI

I/O

(TOP VIEW)

V

CC

11

19

12 13 14 15 16 17 18

4

10

9

8

7

6

5 I/O

20

21

22

23

24

25

3 2 1 282726

I
I
I

NC

I
I
I

Q
Q
NC
Q
Q
I/O

TIBPAL20R4’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE

NC – No internal connection

OE

CLK

I
I
I
I
I
I
I
I
I
I

GND

I
I/O
Q
Q
Q
Q
Q
Q
I/O
I

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OE

I

I

GND

NC

I

I/O

I

I

CLKNCI

I/O

V

CC

11 19

12 13 14 15 16 17 18

4

10

9

8

7

6

5Q

20

21

22

23

24

25

3 2 1 282726

I
I
I

NC

I
I
I

Q
Q
NC
Q
Q
Q

OE

V

CC

(TOP VIEW)

TIBPAL20R6’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

TIBPAL20R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE

CLK

I
I
I
I
I
I
I
I
I
I

GND

I
Q
Q
Q
Q
Q
Q
Q
Q
I

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OE

I

I

GND

NC

I

Q

I

I

CLKNCI

Q

V

CC

11 19

12 13 14 15 16 17 18

4

10

9

8

7

6

5Q

20

21

22

23

24

25

3 2 1 282726

I
I
I

NC

I
I
I

Q
Q
NC
Q
Q
Q

OE

V

CC

(TOP VIEW)

TIBPAL20R8’

C SUFFIX . . . JT OR NT PACKAGE

M SUFFIX . . . JT PACKAGE

(TOP VIEW)

TIBPAL20R8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE

Pin assignments in operating mode

TIBPAL20L8-7C, TIBPAL20R4-7C

TIBPAL20L8-10M, TIBPAL20R4-10M

HIGH-PERFORMANCE IMPACT-X  PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

functional block diagrams (positive logic)

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I

EN

≥1

&

40 X 64

14 20

206

7

7

7

7

7

7

7

7

6

20 x

denotes fused inputs

Q

I/O

I/O

I/O

I/O

I

EN

12 20

204

7

7

7

8

8

8

7

4

20 x

≥1

&

40 X 64

≥1

8

Q

Q

Q

4

1D

I = 0

2

CLK

C1

EN 2

OE

4

TIBPAL20L8’

TIBPAL20R4’

TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4

functional block diagrams (positive logic)

denotes fused inputs

TIBPAL20R6’

TIBPAL20R8’

Q

I/O

I/O

I

EN

12 20

202

7

8

8

8

7

2

20 x

≥1

&

40 X 64

≥1

8

Q

Q

Q

6

1D

I = 0

2

CLK

C1

EN 2

OE

6

8

Q

8

Q

Q

I

12 20

208

8

8

8

8

20 x

8

Q

Q

Q

1D

I = 0

2

CLK

C1

EN 2

8

Q

8

Q

&

40 X 64

≥1

OE

8

Q

8

Q

4 8 12 16 20 24 28 32

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

O

22

I/O

21

I/O

20

I/O

19

I/O

18

I/O

17

I/O

16

O

15

I

14

Increment

I

1

Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.

0
40
80

120
160
200
240
280

320
360
400
440
480
520
560
600

640
680
720
760
800
840
880
920

960
1000
1040
1080
1120
1160
1200
1240

1280
1320
1360
1400
1440
1480
1520
1560

1600
1640
1680
1720
1760
1800
1840
1880

1920
1960
2000
2040
2080
2120
2160
2200

2240
2280
2320
2360
2400
2440
2480
2520

First Fuse
Numbers

36 390

I

2

I

23

I

11

I

13

TIBPAL20L8-7C

TIBPAL20L8-10M

HIGH-PERFORMANCE IMPACT-X PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

logic diagram (positive logic)

Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.

4 8 12 16 20 24 28 32

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I/O

22

I/O

21

I/O

16

I/O

15

Increment

0
40
80

120
160
200
240
280

320
360
400
440
480
520
560
600

640
680
720
760
800
840
880
920

960
1000
1040
1080
1120
1160
1200
1240

1280
1320
1360
1400
1440
1480
1520
1560

1600
1640
1680
1720
1760
1800
1840
1880

1920
1960
2000
2040
2080
2120
2160
2200

2240
2280
2320
2360
2400
2440
2480
2520

First Fuse
Numbers

36 390

I

2

I

23

I

11

I

14

Q

20

Q

19

Q

18

Q

17

C1

1D

I = 0

C1

1D

I = 0

C1

1D

I = 0

C1

1D

I = 0

13

OE

CLK

1

TIBPAL20R4-7C
TIBPAL20R4-10M
HIGH-PERFORMANCE IMPACT-X PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6

logic diagram (positive logic)

Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.

4 8 12 16 20 24 28 32

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

I/O

22

I/O

15

Increment

0
40
80

120
160
200
240
280

320
360
400
440
480
520
560
600

640
680
720
760
800
840
880
920

960
1000
1040
1080

1120

1160
1200
1240

1280
1320
1360
1400
1440
1480
1520
1560

1600
1640
1680
1720
1760
1800
1840
1880

1920
1960
2000
2040
2080
2120
2160
2200

2240
2280
2320
2360
2400
2440
2480
2520

First Fuse
Numbers

36 390

I

2

I

23

I

11

I

14

Q

20

Q

19

Q

18

Q

17

C1

1D

I = 0

C1

1D

I = 0

C1

1D

I = 0

C1

1D

I = 0

13

OE

CLK

1

Q

21

C1

1D

I = 0

Q

16

C1

1D

I = 0

TIBPAL20R6-7C

TIBPAL20R6-10M

HIGH-PERFORMANCE IMP ACT-X PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

logic diagram (positive logic)

Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.

4 8 12 16 20 24 28 32

I

3

I

4

I

5

I

6

I

7

I

8

I

9

I

10

Increment

0
40
80

120
160
200
240
280

320
360
400
440
480
520
560
600

640
680
720
760
800
840
880
920

960
1000
1040
1080

1120

1160
1200
1240

1280
1320
1360
1400
1440
1480
1520
1560

1600
1640
1680
1720
1760
1800
1840
1880

1920
1960
2000
2040
2080
2120
2160
2200

2240
2280
2320
2360
2400
2440
2480
2520

First Fuse
Numbers

36 390

I

2

I

23

I

11

I

14

Q

20

Q

19

Q

18

Q

17

C1

1D

I = 0

C1

1D

I = 0

C1

1D

I = 0

C1

1D

I = 0

13

OE

CLK

1

Q

21

C1

1D

I = 0

Q

16

C1

1D

I = 0

Q

22

C1

1D

I = 0

Q

15

C1

1D

I = 0

TIBPAL20R8-7C
TIBPAL20R8-10M
HIGH-PERFORMANCE IMP ACT-X PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8

logic diagram (positive logic)

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C

HIGH-PERFORMANCE IMPACT-X PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range 0°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 4.75 5 5.25 V

V

IH

High-level input voltage (see Note 2) 2 5.5 V

V

IL

Low-level input voltage (see Note 2) 0.8 V

I

OH

High-level output current –3.2 mA

I

OL

Low-level output current 24 mA

f

clock

†

Clock frequency 0 100 MHz

High 5
Low 5

t

su

†

Setup time, input or feedback before clock↑ 7 ns

t

h

†

Hold time, input or feedback after clock↑ 0 ns

T

A

Operating free-air temperature 0 25 75 °C

†

f

clock

, tw, tsu, and th do not apply for TIBPAL20L8’.

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

noise. Testing these parameters should not be attempted without suitable equipment.

ns

Pulse duration, clock (see Note 2)t

w

†

I, I/O

O, I/Ot

pd

ns

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
HIGH-PERFORMANCE IMPACT-X PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 4.75 V , II = –18 mA –0.8 –1.5 V

V

OH

VCC = 4.75 V , IOH = –3.2 mA 2.4 3.2 V

V

OL

VCC = 4.75 V , IOL = 24 mA 0.3 0.5 V

I

OZH

‡

VCC = 5.25 V , VO = 2.7 V 100 µA

I

OZL

‡

VCC = 5.25 V , VO = 0.4 V –100 µA

I

I

VCC = 5.25 V , VI = 5.5 V 100 µA

I

IH

‡

VCC = 5.25 V , VI = 2.7 V 25 µA

I

IL

‡

VCC = 5.25 V , VI = 0.4 V –80 –250 µA

I

OS

§

VCC = 5.25 V , VO = 0.5 V –30 –70 –130 mA

I

CC

VCC = 5.25 V , VI = 0, Outputs open 150 210 mA

C

i

f = 1 MHz, VI = 2 V 5 pF

C

o

f = 1 MHz, VO = 2 V 6 pF

C

clk

f = 1 MHz, V

CLK

= 2 V 6 pF

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITION MIN TYP†MAX UNIT

without feedback 100

f

max

¶

with internal feedback

(counter configuration)

100 MHz

with external feedback 74

1 or 2 outputs switching 3 5.5 7

8 outputs switching R1 = 200 Ω, 3 6 7.5

t

pd

CLK↑ Q R2 = 390 Ω, 2 4 6.5 ns

t

pd

#

CLK↑ Feedback input See Figure 6 3 ns

t

en

OE↓ Q 4 7.5 ns

t

dis

OE↑ Q 4 7.5 ns

t

en

I, I/O O, I/O 6 9 ns

t

dis

I, I/O O, I/O 6 9 ns

t

sk(o)

||

Skew between registered outputs 0.5 ns

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

I/O leakage is the worst case of I

OZL

and IIL or I

OZH

and IIH respectively.

§

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.

¶

See section for f

max

specifications.

#

This parameter applies to TIBPAL20R4’ and TIBPAL20R6’ only (see Figure 4 for illustration) and is calculated from the measured f

max

with internal

feedback in the counter configuration.

||

This parameter is the measurement of the difference between the fastest and slowest tpd (CLK-to-Q) observed when multiple registered outputs
are switching in the same direction.

TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL



CIRCUITS

SRPS005D – D3307, OCTOBER 1989 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 4.5 5 5.5 V

V

IH

High-level input voltage 2 5.5 V

V

IL

Low-level input voltage 0.8 V

I

OH

High-level output current –2 mA

I

OL

Low-level output current 12 mA

f

clock

†

Clock frequency 0 62.5 MHz

High 8
Low 8

t

su

†

Setup time, input or feedback before clock↑ 10 ns

t

h

†

Hold time, input or feedback after clock↑ 0 ns

T

A

Operating free-air temperature –55 25 125 °C

†

f

clock

, tw, tsu, and th do not apply for TIBPAL20L8’.

NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester

noise. Testing these parameters should not be attempted without suitable equipment.

ns

Pulse duration, clock (see Note 2)t

w

†

µAVI = 2.7 V

VCC =

5.5

V,

I

IH

‡

TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

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electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 4.5 V, II = –18 mA –0.8 –1.5 V

V

OH

VCC = 4.5 V, IOH = –2 mA 2.4 3.2 V

V

OL

VCC = 4.5 V, IOL = 12 mA 0.3 0.5 V

I

OZH

‡

VCC = 5.5 V, VO = 2.7 V 20 µA

I

OZL

‡

VCC = 5.5 V, VO = 0.4 V –0.1 mA

I

I

VCC = 5.5 V, VI = 5.5 V 1 mA
I/O ports 100
All others 25

I

IL

‡

VCC = 5.5 V, VI = 0.4 V –0.08 –0.25 mA

I

OS

§

VCC = 5.5 V, VO = 0.5 V –30 –70 –130 mA

I

CC

VCC = 5.5 V,

VI = 0,

Outputs open
OE = V

IH

140 220 mA

C

i

f = 1 MHz, VI = 2 V 5 pF

C

o

f = 1 MHz, VO = 2 V 6 pF

C

clk

f = 1 MHz, V

CLK

= 2 V 6 pF

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

TEST CONDITION MIN TYP†MAX UNIT

without feedback 62.5

f

max

¶

with internal feedback

(counter configuration)

62.5 MHz

with external feedback 50

t

pd

I, I/O O, I/O R1 = 390 Ω, 1 6 10 ns

t

pd

CLK↑ Q R2 = 750 Ω, 1 4 10 ns

t

pd

#

CLK↑ Feedback input See Figure 6 5 ns

t

en

OE↓ Q 1 4 10 ns

t

dis

OE↑ Q 1 4 10 ns

t

en

I, I/O O, I/O 1 6 12 ns

t

dis

I, I/O O, I/O 1 6 10 ns

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

I/O leakage is the worst case of I

OZL

and IIL or I

OZH

and IIH respectively.

§

Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. VO is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.

¶

See section for f

max

specifications. f

max

with external feedback is not production tested but is calculated from the equation found in the f

max

specification section.

#

This parameter applies to TIBPAL20R4’ and TIBPAL20R6’ only (see Figure 4 for illustration) and is calculated from the measured f

max

with internal

feedback in the counter configuration.

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C

TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

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programming information

Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.

Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming T exas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at [phone].

preload procedure for registered outputs (see Figure 1 and Note 3)

The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.

Step 1. With V

CC

at 5 volts and Pin 1 at VIL, raise Pin 13 to V

IHH

.
Step 2. Apply either VIL or VIH to the output corresponding to the register to be preloaded.
Step 3. Pulse Pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower Pin 13 to VIL. Preload can be verified by observing the

voltage level at the output pin.

t

d

t

su

t

w

t

d

V

IHH

V

IL

V

IL

V

OL

V

OH

V

IH

Pin 13

Pin 1

Registered I/O Input Output

V

IH

V

IL

Figure 1. Preload Waveforms

NOTE 3: td = tsu = th = 100 ns to 1000 ns V

IHH

= 10.25 V to 10.75 v

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

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14

power-up reset (see Figure 2)

Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not
occur until all applicable input and feedback setup times are met.

1.5 V

t

su

‡

t

pd

†

t

w

V

IL

V

IH

5 V

V

CC

Active Low

Registered Output

CLK

4 V

V

OH

V

OL

1.5 V

(600 ns TYP, 1000 ns MAX)

1.5 V

†

This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.

‡

This is the setup time for input or feedback.

Figure 2. Power-Up Reset Waveforms

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C

TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

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f

max

SPECIFICATIONS

f

max

without feedback, see Figure 3

In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t

su

+ th).

However, the minimum f

max

is determined by the minimum clock period (tw high + tw low).

Thus,

f

max

without feedback

+

1

(twhigh

)

twlow)

or

1

(tsu)

th)

.

CLK

LOGIC

ARRAY

tsu + t

h

or

tw high + tw low

C1

1D

Figure 3. f

max

Without Feedback

f

max

with internal feedback, see Figure 4

This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.

Thus,

f

max

with internal feedback

+

1

(tsu)

tpdCLK*to*FB)

.

Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.

CLK

LOGIC

ARRAY

t

su

tpd CLK-to-FB

C1

1D

Figure 4. f

max

With Internal Feedback

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

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16

f

max

SPECIFICATIONS

f

max

with external feedback, see Figure 5

This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(t

su

+ tpd CLK-to-Q).

Thus,

f

max

with external feedback

+

1

(tsu)

tpdCLK*to*Q)

.

tpd CLK-to-Q t

su

CLK

LOGIC

ARRAY

NEXT DEVICE

t

su

C1

1D

Figure 5. f

max

With External Feedback

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C

TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

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PARAMETER MEASUREMENT INFORMATION

t

su

S1

R2

C

L

(see Note A)

LOAD CIRCUIT FOR

3-STATE OUTPUTS

(3.5 V) [3 V]

(0.3 V) [0]

1.5 V

1.5 V

t

h

1.5 V

t

pd

t

pd

t

pd

t

pd

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

V

OH

V

OH

V

OL

V

OL

1.5 V 1.5 V

1.5 V 1.5 V

t

w

1.5 V 1.5 V

≈ 3.3 V

V

OL

V

OH

VOH –0.5 V

≈ 0 V

t

en

t

en

t

dis

t

dis

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATIONS

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

1.5 V

R1

VOL +0.5 V

5 V

(3.5 V) [3 V]

(0.3 V) [0]

(3.5 V) [3 V]

(0.3 V) [0]

(3.5 V) [3 V]

(0.3 V) [0]

(3.5 V) [3 V]

(0.3 V) [0]

(3.5 V) [3 V]

(0.3 V) [0]

From Output
Under Test

Test
Point

Input

Out-of-Phase

Output

(see Note D)

Timing

Input

Data

Input

In-Phase

Output

High-Level

Pulse

Low-Level

Pulse

Output

Control

(low-level

enabling)

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t

dis

.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. W aveform 2

is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%. For C suffix, use the voltage levels

indicated inparentheses ( ). For M suffix, use the voltage levels indicated in brackets [ ].
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.

Figure 6. Load Circuit and Voltage Waveforms

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C
TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M
HIGH-PERFORMANCE IMPACT-X  PAL

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TYPICAL CHARACTERISTICS

160

140

120

100

–75 –50 –25 0 25 50

Figure 7

180

200

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

220

75 100 125

TA – Free-Air Temperature – °C

I

CC

– Supply Current – mA

4

2

1

0

4.5 4.75 5

Figure 8

Propagation Delay Time – ns

6

7

PROPAGATION DELAY TIME

vs

SUPPLY VOLTAGE

8

5.25 5.5

5

3

VCC – Supply Voltage – V

TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω

t

PHL

(I, I/O to O, I/O)

t

PLH

(I, I/O to O, I/O)

t

PHL

(CLK to Q)

t

PLH

(CLK to Q)

1 Output Switching

CL – Load Capacitance – pF

4

2

1

0

–75 –50 –25 0 25 50

Figure 9

Propagation Delay Time – ns

6

7

8

75 100 125

5

3

PROPAGATION DELAY TIME

vs

FREE-AIR TEMPERATURE

VCC = 5 V
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω

1 Output Switching

t

PHL

(I, I/O to O, I/O)

t

PLH

(I, I/O to O, I/O)

t

PHL

(CLK to Q)

t

PLH

(CLK to Q)

TA – Free-Air Temperature – °C

8

4

2

0

100 200 300 400

Figure 10

Propagation Delay Time – ns

12

14

16

500

10

6

PROPAGATION DELAY TIME

vs

LOAD CAPACITANCE

t

PHL

(I, I/O to O, I/O)

t

PLH

(I, I/O to O, I/O)

t

PHL

(CLK to Q)

t

PLH

(CLK to Q)

VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 390 Ω

1 Output Switching

0 600

TIBPAL20L8-7C, TIBPAL20R4-7C, TIBPAL20R6-7C, TIBPAL20R8-7C

TIBPAL20L8-10M, TIBPAL20R4-10M, TIBPAL20R6-10M, TIBPAL20R8-10M

HIGH-PERFORMANCE IMPACT-X  PAL

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TYPICAL CHARACTERISTICS

Number of Outputs Switching

0.4

0.2

0.1

0

23 4 5 6

Figure 12

0.6

0.7

0.8

78

0.5

0.3

PROPAGATION DELAY TIME

†

vs

NUMBER OF OUTPUTS SWITCHING

VCC = 5 V
TA = 25 °C
R1 = 200 Ω
R2 = 390 Ω
CL = 50 pF
8-Bit Counter

4

2

1

0

012345

Figure 13

Propagation Delay Time – ns

6

7

8

678

5

3

PROPAGATION DELAY TIME

vs

NUMBER OF OUTPUTS SWITCHING

t

skew

– Skew Between Outputs Switching – ns

VCC = 5 V
TA = 25 °C
CL = 50 pF
R1 = 200 Ω
R2 = 390 Ω

Number of Outputs Switching

t

PHL

(I, I/O to O, I/O)

t

PLH

(I, I/O to O, I/O)

t

PHL

(CLK to Q)

t

PLH

(CLK to Q)

1 4 10 40 100

Figure 11

F – Frequency – MHz

POWER DISSIPATION

vs

FREQUENCY

8-BIT COUNTER MODE

800

600

1000

700

900

VCC = 5 V

P

D

– Power Dissipation – mW

TA = 0 °C

TA = 25 °C

TA = 80 °C

†

Outputs switching in the same direction (t

PLH compared to

t

PLH/tPHL to

t

PHL)

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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