Datasheet TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M Datasheet (TEXAS INSTRUMENTS)
Page 1
查询TIBPAL16L8-15M供应商
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
CIRCUITS
D
High-Performance Operation:
Propagation Delay . . . 15 ns Max
D
Power-Up Clear on Registered Devices (All
Register Outputs are Set High, but Voltage
Levels at the Output Pins Go Low)
D
Package Options Include Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (J) 300-mil DIPs
D
Dependable Texas Instruments Quality and
Reliability
DEVICE
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0
I
INPUTS
3-STATE
O OUTPUTS
REGISTERED
Q OUTPUTS
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMP ACT-X circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for futher
reduction in board space.
The TIBPAL16’ M series is characterized for
operation over the full military temperature range
of –55°C to 125°C.
I/O
PORTS
TIBPAL16L8’
J OR W PACKAGE
(TOP VIEW)
I
I
I
I
I
I
I
I
I
GND
FK PACKAGE
3 2 1 20 19
I
4
I
5
I
6
I
7
I
8
910111213
1
2
3
4
5
6
7
8
9
10
TIBPAL16L8’
(TOP VIEW)
I
I
I
V
20
CC
O
19
I/O
18
I/O
17
I/O
16
15
I/O
14
I/O
13
I/O
12
O
11
I
CC
I
O
V
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I
O
I/O
GND
Pin assignments in operating mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
Page 2
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16R4’
J OR W PACKAGE
(TOP VIEW)
CLK
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
GND
GND
10
TIBPAL16R6’
J OR W PACKAGE
(TOP VIEW)
CLK
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
10
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
V
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
V
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
CC
CC
TIBPAL16R4’
FK PACKAGE
(TOP VIEW)
I
3212019
I
4
I
5
I
6
I
7
I
8
910111213
I
TIBPAL16R6’
FK PACKAGE
(TOP VIEW)
I
3212019
I
4
I
5
I
6
I
7
I
8
910111213
I
I
CLK
GND
I
CLK
GND
OE
OE
V
I/O
V
I/O
CC
CC
I/O
18
17
16
15
14
I/O
I/O
18
17
16
15
14
Q
I/O
Q
Q
Q
Q
Q
Q
Q
Q
Q
J OR W PACKAGE
CLK
I
I
I
I
I
I
I
I
GND
Pin assignments in operating mode
TIBPAL16R8’
(TOP VIEW)
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
V
Q
Q
Q
Q
Q
Q
Q
Q
OE
CC
TIBPAL16R8’
FK PACKAGE
(TOP VIEW)
I
3212019
I
4
I
5
I
6
I
7
I
8
910111213
I
I
CLK
GND
OE
V
Q
CC
Q
18
17
16
15
14
Q
Q
Q
Q
Q
Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
functional block diagrams (positive logic)
HIGH-PERFORMANCE IMPACT PAL
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16L8’
CIRCUITS
OE
CLK
10 16
I
16 x
&
32 X 64
166
32 X 64
7
7
7
7
7
7
7
7
6
TIBPAL16R4 ’
&
8
8
EN
≥1
≥1
EN 2
C1
I = 1
1D
O
O
I/O
I/O
I/O
I/O
I/O
I/O
2
Q
Q
denotes fused inputs
816
I
16 x
4
164
8
8
≥1
EN
7
7
7
7
4
4
Q
Q
I/O
I/O
I/O
I/O
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
functional block diagrams (positive logic)
TIBPAL16R6’
OE
CLK
816
I
16 x
6
162
&
32 X 64
8
8
8
8
8
8
7
7
2
6
TIBPAL16R8 ’
EN
≥1
≥1
EN 2
C1
I = 1
1D
2
Q
Q
Q
Q
Q
Q
I/O
I/O
OE
CLK
denotes fused inputs
816
I
16 x
168
&
32 X 64
EN 2
C1
1D
I = 1
2
Q
Q
Q
Q
Q
Q
Q
Q
8
8
8
8
8
8
8
8
8
≥1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
TIBPAL16L8-15M logic diagram (positive logic)
1
I
First
Fuse
Numbers
2
I
3
I
4
I
5
I
1024
1056
1088
1120
1152
1184
1216
1248
6
I
1280
1312
1344
1376
1408
1440
1472
1504
7
I
1536
1568
1600
1632
1664
1696
1728
1760
8
I
1792
1824
1856
1888
1920
1952
1984
2016
9
I
0 4 8 12 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
Increment
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
19
O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
O
11
I
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16R4-15M logic diagram (positive logic)
1
CLK
First
Fuse
Numbers
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
0 4812 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
Fuse number = First fuse number + Increment
Increment
I = 1
1D
I = 1
1D
I = 1
1D
I = 1
1D
C1
C1
C1
C1
19
18
17
16
15
14
13
12
11
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
TIBPAL16R6-15M logic diagram (positive logic)
1
CLK
First
Fuse
Numbers
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
0 4 8 12 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
Fuse number = First fuse number + Increment
Increment
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
19
I/O
I = 1
1D
18
Q
C1
I = 1
1D
17
Q
C1
I = 1
1D
16
Q
C1
I = 1
1D
15
Q
C1
I = 1
1D
14
Q
C1
I = 1
1D
13
Q
C1
12
I/O
11
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
TIBPAL16R8-15M logic diagram (positive logic)
1
CLK
First
Fuse
Numbers
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
0 4 8 12 16 20 24 28 31
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
Fuse number = First fuse number + Increment
Increment
I = 1
1D
I = 1
1D
I = 1
1D
I = 1
1D
I = 1
1D
I = 1
1D
I = 1
1D
I = 1
1D
C1
C1
C1
C1
C1
C1
C1
C1
19
18
17
16
15
14
13
12
11
Q
Q
Q
Q
Q
Q
Q
Q
OE
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
twPulse duration, clock (see Note 2)
ns
PARAMETER
TEST CONDITIONS
UNIT
I
V
V
V
A
I
V
V
V
A
I
V
V
V
mA
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
t
su
t
h
T
A
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, f
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 5.5 V
Low-level input voltage 0.8 V
High-level output current –2 mA
Low-level output current 12 mA
Clock frequency 0 50 MHz
High 9
Low 10
Setup time, input or feedback before clock↑ 15 ns
Hold time, input or feedback after clock↑ 0 ns
Operating free-air temperature –55 25 125 °C
. The minimum pulse durations specified are
only for clock high or low, but not for both simultaneously.
clock
†
electrical characteristics over recommended operating free-air temperature range
TIBPAL16R4-15M
MIN TYP‡MAX
V
IK
V
OH
V
OL
OZH
OZL
I
I
IH
I
IL
I
OS
I
CC
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
Outputs
I/O ports
Outputs
I/O ports
Pin 1, 11
All others
Pin 1, 11 50
I/O ports
All others 25
§
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V, IOH = –2 mA 2.4 3.3 V
VCC = 4.5 V, IOL = 12 mA 0.35 0.5 V
= 5.5 V,
CC
= 5.5 V,
CC
= 5.5 V,
CC
VCC = 5.5 V, VI = 2.7 V
VCC = 5.5 V, VI = 0.4 V –0.25 mA
VCC = 5.5 V, VO = 0.5 V –30 –250 mA
VCC = 5.5 V, VI = 0, Outputs open 170 220 mA
= 2.7
O
= 0.4
O
= 5.5
I
20
100
–20
–250
0.2
0.1
100
µ
µ
µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
Page 10
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
PARAMETER
TEST CONDITIONS
UNIT
I
V
V
V
A
I
V
V
V
A
I
V
V
V
mA
I
V
5.5 V
V
0.4 V
mA
HIGH-PERFORMANCE IMPACT PAL
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
electrical characteristics over recommended operating free-air temperature range
TIBPAL16L8-15M
TIBPAL16R6-15M
TIBPAL16R8-15M
MIN TYP†MAX
V
IK
V
OH
V
OL
OZH
OZL
I
I
IH
IL
I
OS
I
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
Outputs
I/O ports
Outputs
I/O ports
Pin 1, 11
All others
Pin 1, 11 50
I/O ports
All others 20
I/O ports
All others
‡
VCC = 4.5 V, II = –18 mA –1.5 V
VCC = 4.5 V, IOH = –2 mA 2.4 3.3 V
VCC = 4.5 V, IOL = 12 mA 0.35 0.5 V
= 5.5 V,
CC
= 5.5 V,
CC
= 5.5 V,
CC
VCC = 5.5 V, VI = 2.7 V
,
=
CC
VCC = 5.5 V, VO = 0.5 V –30 –250 mA
VCC = 5.5 V, VI = 0, Outputs open 170 220 mA
= 2.7
O
= 0.4
O
= 5.5
I
=
I
20
100
–20
–250
0.2
0.1
100
–0.25
–0.2
µ
µ
µA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
§
f
max
t
pd
t
pd
t
en
t
dis
t
en
t
dis
†
All typical values are at VCC = 5 V, TA = 25°C.
§
Maximum operating frequency and propagation delay are specified for the basic building block. When using feedback, limits must be calculated
accordingly.
FROM
(INPUT)
I, I/O O, I/O
CLK↑ Q R1 = 390 Ω, 7 12 ns
OE↓ Q R2 = 750 Ω, 8 12 ns
OE↑ Q See Figure 1 7 12 ns
I, I/O O, I/O 8 15 ns
I, I/O O, I/O 8 15 ns
TO
(OUTPUT)
TEST CONDITIONS MIN TYP†MAX UNIT
50 MHz
8 15 ns
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 11
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
CIRCUITS
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
The TIBPAL16R4-15M with date codes prior to 9616A must be programmed according to programming
algorithms/specifications corresponding to the TIBP AL16R4-12C. The TIBPAL16R4-15M with date code 9616A
or newer must be programmed according to programming algorithms/specifications corresponding to the
TIBPAL16R4-10C.
Regardless of date code, the TIBPAL16L8-15M, TIBPAL16R6-15M, and TIBPAL16R8-15M must be
programmed according to programming algorithms/specifications corresponding to the TIBPAL16L8-12C,
TIBPAL16R6-12C, and TIBPAL16R8-12C, respectively. Failure to do so may damage the devices.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming T exas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
Table 1. Programming Reference Table
(see Note 3)
DEVICE
TIBPAL16L8-15MJB 5962-8515509RA 9A/17
TIBPAL16L8-15MFKB 5962-85155092A 9A/717
TIBPAL16L8-15MWB 5962-8515509SA 9A/17
TIBPAL16R4-15MJB 5962-8515512RA A1/24
TIBPAL16R4-15MFKB 5962-85155122A 0A1/724
TIBPAL16R4-15MWB 5962-8515512SA A1/24
TIBPAL16R6-15MJB 5962-8515511RA 9A/24
TIBPAL16R6-15MFKB 5962-85155112A 9A/724
TIBPAL16R6-15MWB 5962-8515511SA 9A/24
TIBPAL16R8-15MJB 5962-8515510RA 9A/24
TIBPAL16R8-15MFKB 5962-85155102A 9A/724
TIBPAL16R8-15MWB 5962-8515510SA 9A/24
NOTE 3: Programming information for TIBPAL16R4-15M with date codes
9616A or newer. Programming information for TIBPAL16L8-15M,
TIBPAL16R6-15M, and TIBPAL16R8-15M regardless of date code.
DESC SMD
NUMBER
FAMILY/PINOUT
CODE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
Page 12
TIBPAL16L8-15M, TIBPAL16R4-15M, TIBPAL16R6-15M, TIBPAL16R8-15M
HIGH-PERFORMANCE IMPACT PAL
CIRCUITS
SRPS018A – D3338, JANUARY 1986 – REVISED MAY 1996
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
Timing
Input
t
Data
Input
Input
t
pd
In-Phase
Output
t
pd
Out-of-Phase
Output
(see Note D)
PROPAGATION DELAY TIMES
1.5 V
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
(see Note A)
t
h
1.5 V
t
pd
1.5 V
t
pd
C
L
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
3 V
0
3 V
0
V
OH
V
OL
V
OH
V
OL
R2
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
1.5 V 1.5 V
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
t
en
t
en
1.5 V
1.5 V
t
t
dis
dis
3 V
0
3 V
0
3 V
0
≈ 3.3 V
VOL + 0.5 V
V
OL
V
OH
VOH – 0.5 V
≈ 0 V
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for t
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VOLTAGE WAVEFORMS
.
dis
Page 13
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...