Datasheet THS6032IGQER, THS6032IDWPR, THS6032IDWP, THS6032CGQER, THS6032EVM Datasheet (Texas Instruments)

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Low Power ADSL Line Driver Ideal for

Central Office
– 1.35-W Total Power Dissipation for

Full-Rate ADSL Into a 25-Ω Load

D Low-Impedance Shutdown Mode

– Allows Reception of Incoming Signal

During Standby

D Two Modes of Operation

– Class-G Mode: 4 Power Supplies, 1.35 W

Power Dissipation

– Class-AB Mode: 2 Power Supplies, 2 W

Power Dissipation

D Low Distortion

– THD = –62 dBc at f = 1 MHz,

V

O(PP)

= 20 V, 25-Ω Load

– THD = –69 dBc at f = 1 MHz,

V

O(PP)

= 2 V, 25-Ω Load

D 400-mA Minimum Output Current Into a

25-Ω Load

D High Speed

– 65-MHz Bandwidth (–3dB) , 25-Ω Load
– 100-MHz Bandwidth (–3dB) , 100-Ω Load
– 1200 V/µs Slew Rate

D Thermal Shutdown and Short Circuit

Protection

D Evaluation Module Available

description

The THS6032 is a low-power line driver ideal for asymmetrical digital subscriber line (ADSL) applications. This
device contains two high-current, high-speed current-feedback drivers, which can be configured differentially
for driving ADSL signals at the central office. The THS6032 features a unique class-G architecture to lower
power consumption to 1.35 W. The THS6032 can also be operated in a traditional class-AB mode to reduce
the number of power supplies to two.

HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY

DEVICE

DRIVER RECEIVER 5 V ±5 V ±15 V DESCRIPTION

THS6002

•

• • • 500-mA differential line driver and receiver
THS6012 • • • 500-mA differential line driver
THS6022 • • • 250-mA differential line driver
THS6032 • • • 500-mA low-power ADSL central-office line driver
THS6062 • • • • Low-noise ADSL receiver
THS6072 • • • Low-power ADSL receiver
THS7002 • • • Low-noise programmable-gain ADSL receiver

CAUTION: The THS6032 provides ESD protection circuitry. However, permanent damage can still occur if this device is subjected
to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss
of functionality.

Copyright  2000, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

PAD

†

V

CCH

–

1OUT

V

CCL

–
1IN–
1IN+

NC
SHDN1
SHDN2

PAD

†

PAD

†

V

CCH

+
2OUT
V

CCL

+
2IN–
2IN+
NC
NC
DGND
PAD

†

THERMALLY ENHANCED SOIC (DWP)

PowerPAD PACKAGE

(TOP VIEW)

NC – Not Connected

†

This terminal is internally connected to the thermal pad.

Cross section view showing PowerPAD

(SIDE VIEW)

MicroStar Junior (GQE) PACKAGE

(TOP VIEW)

PowerPAD and MicroStar Junior are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The class-G architecture supplies current to the load from four supplies. For low output voltages (typically
–2.5 < VO < +2.5), some of the output current is supplied from the +V

CC(L)

and –V

CC(L)

supplies (typically ±5 V).

For large output voltages (typically V

O

< –2.5 and VO > +2.5), the output current is supplied from +V

CC(H)

and

–V

CC(H)

(typically ±15 V). This current sharing between V

CC(L)

and V

CC(H)

minimizes power dissipation within

the THS6032 output stages for high crest factor ADSL signals.
The THS6032 features a low-impedance shutdown mode, which allows the central office to receive incoming

calls even after the device has been shut down. The THS6032 is available packaged in the patented PowerP AD
package. This package provides outstanding thermal characteristics in a small-footprint surface-mount
package, which is fully compatible with automated surface-mount assembly procedures. It is also available in
the new MicoStar Junior BGA package. This package is only 25 mm

2

in area, allowing for high density PCB

designs.
Shutdown (SHDN1 and SHDN2) allows for powering down the internal circuitry for power conservation or for

multiplexing. Separate shutdown controls are available for each channel on the THS6032. The control levels
are TTL compatible. When turned off, each driver output is placed in a low impedance state which is determined
by the voltage at DGND. This virtual ground at the outputs allows proper termination of a transmission line.

AVAILABLE OPTIONS

PACKAGED DEVICES PACKAGED DEVICES

T

A

PowerPAD PLASTIC SMALL OUTLINE

(DWP)

MicroStar Junior (BGA)

(GQE)

EVALUATION MODULES

0°C to 70°C

THS6032CDWP THS6032CGQE

THS6032EVM

THS6032GQE EVM

‡

–40°C to 85°C

THS6032IDWP THS6032IGQE —

†

The THS6032 is available taped and reeled. Add an R suffix to the device type (i.e.,THS6032CDWPR)

‡

Uses the THS6032CGQE packaging option.

Terminal Functions

TERMINAL

NAME DWP PACKAGE

TERMINAL NO.

GQE PACKAGE

TERMINAL NO.

1OUT 3 B1
1IN– 5 F1
1IN+ 6 H1
2OUT 18 B9
2IN– 16 F9
2IN+ 15 H9
V

CCH–

2 A3

V

CCH+

19 A7

V

CCL–

4 D1

V

CCL+

17 D9
SHDN1 8 J2
SHDN2 9 J4
DGND 12 J7
PAD 1, 10, 11, 20 N/A
NC 7, 13, 14 N/A

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pin assignments

98765

A

B

C

D

E

F

321

G

H

J

4

DGND

V

CCL+

SHDN1

1OUT

1IN–

NC

NC

NC

NC

NC

NCNC NC NC NC

NC NC NC

NC NC NC

NC NC NC

NC NC

NC NC NC

2OUT

NCNC

NCNC

NC

NC

NCNC NC

NCNC NC

NC NC

NC NC NC

NC

NC

NC

NC

NC NC

NC

V

CCH+

SHDN2

NC

NC

NC NCNC NC

NC

NC NC NC

NC

NC

V

CCH–

NC NC NC

2IN–

NC

NCNC

NC

1IN+

V

CCL–

NOTE: Shaded terminals are used for thermal connection to the ground plane.

2IN+

MicroStar Junior (GQE) PACKAGE

(TOP VIEW)

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram (SOIC package)

V

CCL+

DGND

–

+

V

CCH+

2OUT

19

18
17

16

15

12

2IN–

2IN+

1OUT

1IN–

1IN+

V

CCL–

V

CCH–

SHDN1

8

5

6

3

2

4

–

+

SHDN2

9

NOTE A: Terminals 1, 10, 11, and 20 are internally connected to the thermal pad.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, V

CC(L)

and V

CC(H)

(see Note 1) 33 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, VI ±V

CCH

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, I

O

(see Note 2) 800 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, VID ±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Total power dissipation at (or below) 25°C free-air temperature

(see Note 2) See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature, T

A

, C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I-suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature, T

stg

–65°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. V

CC(L)

must always be less than or equal to V

CC(H)

2. The THS6032 incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which
could permanently damage the device. See the Thermal Information section for more information about utilizing the PowerPAD
thermally enhanced packages.

DISSIPATION RATING TABLE

‡

PACKAGE

θ

JA

(°C/W)

θ

JC

(°C/W)

TA = 25°C

POWER RATING

DWP 21.5 0.37 5.8 W
GQE 37.8 4.56 3.3 W

‡

This data was taken using 2 oz. trace and copper pad that is soldered directly to a JEDEC
standard 4 layer 3 in × 3 in PCB.

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

V

CC(L) – Class G mode

±3 ±5 ±V

CCH

V

Supply voltage

V

CC(L) – Class AB mode

0 0 0 V

Su ly voltage

V

CC(H)

±5 ±15 ±16 V

p

p

C-suffix 0 70

°

Operating free-air temperatures, T

A

I-suffix –40 85

°C

electrical characteristics, V

CC(L)

= ±5 V, V

CC(H)

= ±15 V , RL = 25 Ω, TA = 25 °C (unless otherwise noted)

dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RL = 25 Ω 65

Gain = 1, RF = 1.3 kΩ

RL = 100 Ω 100

MHz

Small signal bandwidth (–3 dB)

RL = 25 Ω 60

BW

Gain = 2, RF = 1.1 kΩ

RL = 100 Ω 70

MHz

BW

Gain = 1 30

Bandwidth for 0.1 dB flatness

Gain = 2 25

MHz

Full power bandwidth

†

V

OPP

= 20 V 19 MHz

SR Slew rate

‡

Gain = 5, V

O(PP)

= 20 V 1200 V/µs

t

s

Settling time to 0.1% Gain = 1, RL = 25 Ω, 5 V Step 120 ns

†

Full power bandwidth = slew rate/2π V

PEAK

‡

Slew rate is defined from the 25% to the 75% output levels.

noise/distortion performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VO = 20 V

(pp)

, Gain = 5, f = 1 MHz –62

THD T otal harmonic distortion

VO = 2 V

(pp)

, Gain = 2,

f = 1 MHz –69

dBc

V

n

Input voltage noise f = 10 kHz 2.4

nV/√Hz

I

n+

11

I

n

Input current noise f = 10 kHz

I

n–

15

nV/√Hz

RL = 150 Ω 0.016%

Differential gain error Gain = 2, NTSC

RL = 25 Ω 0.020%
RL = 150 Ω 0.04°

Differential phase error Gain = 2, NTSC

RL = 25 Ω 0.30°

Crosstalk f = 1 MHz, Gain = 2, RF = 1.1 kΩ –62 dB

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, V

CC(L)

= ±5 V, V

CC(H)

= ±15 V , RL = 25 Ω, TA = 25 °C (unless otherwise noted)

(continued)

dc performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Z

(t)

Open loop transimpedance RL = 1 kΩ 2 MΩ

TA = 25°C 1.5 5

V

IO

Input offset voltage

TA = full range

7

mV

Offset voltage drift 10 µV/°C

TA = 25°C 0.5 3

Differential offset voltage

TA = full range

6

mV

TA = 25°C 1.5 9

Negative input bias current

TA = full range 12

I

IB

TA = 25°C 1.5 9

µA

Positive input bias current

TA = full range 12

input characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ICR

Input common-mode voltage range ±13.2 ±13.4 V

CMRR Common-mode rejection ratio TA = full range 64 72 dB

Inverting terminal 15 Ω

r

i

Input resistance

Non inverting terminal

400 kΩ

Differential input capacitance 1.4 pF

output characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Single-ended RL = 25 Ω ±10.5 ±11

V

O

Output voltage

Differential

RL = 50 Ω ±21 ±22

V

I

O

Output current

†

RL = 25 Ω 400 440 mA

I

SC

Short-circuit current

†

800 mA

†

A heat sink is required to keep junction temperature below absolute maximum when an output is heavily loaded or shorted. See “absolute
maximum ratings.”

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

CCL

0 ±5 ±V

CCH

V

CC

Operating range

V

CCH

±5 ±15 ±16.5

V

TA = 25°C 4.3 5.8

V

CCL

TA = full range 6.2

mA

I

CC

Quiescent current (per amplifier)

TA = 25°C 4 5

V

CCH

TA = full range 5.5

mA

TA = 25°C 90 100

V

CCL

TA = full range 80

dB

PSRR Power supply rejection ratio

TA = 25°C 69 80

V

CCH

TA = full range 66

dB

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, V

CC(L)

= ±5 V, V

CC(H)

= ±15 V , RL = 25 Ω, TA = 25 °C (unless otherwise noted)

(continued)

shutdown characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

IL

Shutdown voltage for power up Relative to DGND terminal 0.8 V

V

IH

Shutdown voltage for power down Relative to DGND terminal 2 V

I

IH

Shutdown input current-high V

(SHDN)

= 5 V 200 300 µA

I

IL

Shutdown input current-low V

(SHDN)

= 0.5 V 20 40 µA

Z

o

Output impedance (while in shutdown state) V

(SHDN)

= 2.5 V, f = 1 MHz 0.5 Ω

I

CCL

pp

p

p

0.05 0.2

I

CCH

Supply current (per amplifier) (while in shutdown state) V

(SHDN)

= 2.5 V, VO = 0 V

2.4 3

mA

t

dis

Disable time

†

1.1 µS

t

en

Enable time

†

1.5 µS

†

Disable/enable time begins when the logic signal is applied to the shutdown terminal and ends when the supply current has reached half of its
final value.

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 1

–7

–6

–5

–4

–3

–2

–1

0

1

2

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +1
RL = 25 Ω
VO = 0.2 V

RMS

RF = 1.5 kΩ

1 M 10 M 100 M100 k 500 M

Output Amplitude – dB

RF = 1 kΩ

RF = 1.3 kΩ

Figure 2

–0.4

–0.3

–0.2

–0.1

–0.0

0.1

0.2

0.3

0.4

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +1
RL = 25 Ω
VO = 0.2 V

RMS

RF = 1.5 kΩ

1 M 10 M 100 M100 k 500 M

Output Amplitude – dB

RF = 1.3 kΩ

RF = 1 kΩ

Figure 3

–1

0

1

2

3

4

5

6

7

8

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +2
RL = 25 Ω
VO = 0.4 V

RMS

RF = 1.1 kΩ

1 M 10 M 100 M100 k 500 M

Output Amplitude – dB

RF = 1.3 kΩ

RF = 820 Ω

Figure 4

5.6

5.7

5.8

5.9

6.0

6.1

6.2

6.3

6.4

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +2
RL = 25 Ω
VO = 0.4 V

RMS

RF = 1.1 kΩ

1 M 10 M 100 M100 k 500 M

Output Amplitude – dB

RF = 1.3 kΩ

RF = 820 Ω

Figure 5

7

8

9

10

11

12

13

14

15

16

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +5
RL= 25 Ω
Vo = 0.2 V

RMS

RF = 1.5 kΩ

1M 10M 100M100k 500M

Output Amplitude – dB

RF = 820 Ω

RF = 330 Ω

Figure 6

13

14

15

16

17

18

19

20

21

22

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +10
RL= 25 Ω
Vo = 0.2 V

RMS

1M 10M 100M100k 500M

Output Amplitude – dB

RF = 1 kΩ

RF = 510 Ω

Figure 7

–6

–4

–2

0

2

4

6

8

CLASS-AB MODE OUTPUT AMPLITUDE

vs

FREQUENCY

V

CC(H)

= ± 15 V

V

CC(L)

= GND

G = +2
RF =1.1 kΩ

RL = 25 Ω
VI = 0.2 V

RMS

1 M 10 M 100 M100 k 500 M

Class-AB Mode Output Amplitude – dB

G = +1
RF =1.3 kΩ

f – Frequency – Hz

Figure 8

–8

–6

–4

–2

0

2

4

6

8

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
RL = 100 Ω
VIN = 0.2 V

RMS

Gain = +2, RF = 1.1 kΩ

1 M 10 M 100 M100 k 500 M

Output Amplitude – dB

Gain = +1, RF = 1.3 kΩ

Figure 9

–18

–12

–6

0

6

12

18

SMALL AND LARGE SIGNAL

FREQUENCY RESPONSE

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V

1 M 10 M 100 M100 k 500 M

V

O(PP)

= 4 V

V

O(PP)

= 2 V

V

O(PP)

= 1 V

V

O(PP)

= 0.5 V

V

O(PP)

= 0.25 V

Gain = +1
RL = 25 Ω

RF = 1.3 k Ω

– Normalized Output Voltage – dBV
V

O

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

–12

–6

0

6

12

18

24

SMALL AND LARGE SIGNAL

FREQUENCY RESPONSE

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V

1 M 10 M 100 M100 k 500 M

V

O(PP)

= 8 V

V

O(PP)

= 4 V

V

O(PP)

= 2 V

V

O(PP)

= 1 V

V

O(PP)

= 0.5 V

Gain = +2
RL = 25 Ω

RF = 1.1 k Ω

– Normalized Output Voltage – dBV
V

O

Figure 11

–100

–90

–80

–70

–60

–50

–40

–30

–20

CLASS-G MODE DISTORTION

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V to ± 7.5 V
Gain = +2
RF = 1.1 kΩ
RL = 25 Ω
V

O(PP)

= 2 V

2nd Harmonic

1 M 10 M100 k 20 M

Class-G Mode Distortion – dBc

3rd Harmonic

THD

Figure 12

–100

–90

–80

–70

–60

–50

–40

–30

–20

CLASS-AB MODE DISTORTION

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= GND
Gain = +2
RF = 1.1 kΩ
RL = 25 Ω
V

O(PP)

= 2 V

2nd Harmonic

1 M 10 M100 k 20 M

Class-AB Mode Distortion – dBc

3rd Harmonic

THD

Figure 13

–90

–85

–80

–75

–70

–65

–60

–55

–50

0 5 10 15 20

2ND ORDER DISTORTION

vs

OUTPUT VOLTAGE

V

O(PP)

– Output Voltage – V

V

CC(H)

= ± 15 V
Gain = +5
RF= 1.1 kΩ
RL = 25 Ω
f = 1 MHz

V

CC(L)

= ± 5 V

2ND Order Distortion – dBc

V

CC(L)

= ± 7.5 V

V

CC(L)

= ± 6 V

V

CC(L)

= GND

Figure 14

–90

–85

–80

–75

–70

–65

–60

–55

–50

0 5 10 15 20

3RD ORDER DISTORTION

vs

OUTPUT VOLTAGE

V

O(PP)

– Output Voltage – V

V

CC(H)

= ± 15 V
Gain = +5
RF= 1.1 kΩ
RL = 25 Ω
f = 1 MHz

V

CC(L)

= ± 5 V

3RD Order Distortion – dBc

V

CC(L)

= ± 7.5 V

V

CC(L)

= ± 6 V

V

CC(L)

=GND

Figure 15

–90

–85

–80

–75

–70

–65

–60

–55

–50

0 5 10 15 20

THD

vs

OUTPUT VOLTAGE

V

O(PP)

– Output Voltage – V

V

CC(H)

= ± 15 V
Gain = +5
RF= 1.1 kΩ
RL = 25 Ω
f = 1 MHz

V

CC(L)

= ± 5 V

Total Harmonic Distortion – dBc

V

CC(L)

= ± 7.5 V

V

CC(L)

= ± 6 V

V

CC(L)

=GND

Figure 16

–80

–70

–60

–50

–40

–30

–20

–10

0

CROSSTALK

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +2
RF = 1.1 kΩ
RL = 25 Ω

Input = Ch. 2
Output = Ch. 1

Input = Ch. 1
Output = Ch. 2

1 M 10 M 100 M100 k 500 M

Crosstalk – dB

Figure 17

0

200

400

600

800

1000

1200

1400

0 5 10 15 20

SLEW RATE

vs

OUTPUT STEP

V

O(pp)

– Output Voltage Step – V

SR – Slew Rate – V/ µs

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +5
RF = 1.1 kΩ
RL = 25 Ω

+SR

–SR

Figure 18

VOLTAGE AND CURRENT NOISE

vs

FREQUENCY

100

1

10

f – Frequency – Hz

100 100 k10 k1 k10

V

N

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V

TA = 25°C

In–

In+

nV/ Hz– Voltage Noise –V

n

I

n

– Current Noise – pA/

Hz

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 19

20

40

60

80

100

120

140

TRANSIMPEDANCE

vs

FREQUENCY

f – Frequency – Hz

1 k 10 k 100 k

Transimpedance – dB

1 M 10 M 100 M 1 G

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V

RL= 1 kΩ

Ω

Figure 20

0

20

40

60

80

100

120

POWER SUPPLY REJECTION RATIO

vs

FREQUENCY

f – Frequency – Hz

10 k 100 k 1 M 10 M 100 M

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +2
RF = 1.1 kΩ
RL = 25 Ω

PSRR – Power Supply Rejection Ratio – dB

+V

CC(L)

–V

CC(L)

±V

CC(H)

Figure 21

0

10

20

30

40

50

60

70

80

COMMON-MODE REJECTION RATIO

vs

FREQUENCY

f – Frequency – Hz

10 k 100 k 1 M 10 M 100 M

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
RF = 1 kΩ
RL = 25 Ω

CMRR – Common-Mode Rejection Ratio – dB

Figure 22

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

–40 –20 0 20 40 60 80 100

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

I

CC(L)

TA – Free-Air Temperature – °C

I

CC

– Supply Current – mA

I

CC(H)

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V

Per Amplifier

Figure 23

10.6

10.8

11.0

11.2

11.4

11.6

11.8

12.0

–40 –20 0 20 40 60 80 100

MAXIMUM OUTPUT VOLTAGE

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

V

CC(H)

= ± 15 V

V

CC(L)

=± 5 V

OUT

– Maximum Output Voltage – VV

+V

OUT

–V

OUT

Figure 24

1.0

1.2

1.4

1.6

1.8

2.0

–40 –20 0 20 40 60 80 100

INPUT OFFSET VOLTAGE

vs

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

V

CC(H)

= ± 15

V

CC(L)

=± 5 V

V

IO

– Input Offset Voltage – mV

–40 –20 0 20 40 60 80 100

Figure 25

INPUT BIAS CURRENT

vs

FREE-AIR TEMPERATURE

lib+

I

IB

– Input Bias Current – Aµ

TA – Free-Air Temperature – °C

lib–

2

1.75

1.5

1.25

1

0.75

0.5

0.25
0

Figure 26

12345678

DIFFERENTIAL GAIN

vs

LOADING

Gain = 2
RF = 1.1 kΩ
40 IRE Modulation
Worst Case
± 100 IRE Ramp

Number of 150 Ω Loads

0.02

0.03

0.04

0.05

0.01

0

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V

PAL

NTSC

Differential Gain – %

Figure 27

0.0

0.1

0.2

0.3

0.4

0.5

12345678

DIFFERENTIAL PHASE

vs

LOADING

Gain = 2
RF = 1.1 kΩ
40 IRE Modulation
Worst Case
± 100 IRE Ramp

Number of 150 Ω Loads

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V

PAL

NTSC

Differential Phase – %

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 28

100

1000

.01

0.1

1

10

CLOSED LOOP OUTPUT IMPEDANCE

vs

FREQUENCY

f – Frequency – Hz

– Closed Loop Output Impedance –Z

o

Ω

1 M 10 M 100 M100 k 500 M

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +2
RF = 1 kΩ

Shut-down

Mode

Not
Shut-down

0

Figure 29

–40 –20 0 20 40 60 80 100

STANDBY SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

I

CC(L)

TA – Free-Air Temperature – °C

I

CC(H)

I

CC(H)

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
VSD = 2.5 V
Per Amplifier

2.25

2.50

2.75

3.00

2.00

1.50

1.75

50

52

54

56

48

44

46

I

CC(L)

– Stanby Supply Current – A

– Stanby Supply Current – mA

µ

Figure 30

–90

–80

–70

–60

–50

–40

–30

–20

–10

SHUTDOWN ISOLATION

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +2
RL = 25 Ω
RF = 1.1 kΩ
VI = 0.2 V

RMS

1 M 10 M 100 M100 k 500 M

Shutdown Isolation – dB

Reverse
Isolation

Forward
Isolation

Figure 31

–90

–80

–70

–60

–50

–40

–30

–20

–10

SHUTDOWN ISOLATION

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = –1
RL = 25 Ω
RF = 1.1 kΩ
VI = 0.2 V

RMS

1 M 10 M 100 M100 k 500 M

Shutdown Isolation – dB

Reverse
Isolation

Forward
Isolation

Figure 32

800

600

200

0

SHUTDOWN RESPONSE

t – Time – µs

0481216

400

10

5

0

–200

20

Gain = +2
RF = 1.1 kΩ
RL = 25 Ω

– Output Voltage – mV
V

O

2 6 10 14 18

V

SD

– Shutdown Voltage – V

Figure 33

–0.6

–0.4

–0.2

–0.0

0.2

0.4

0.6

0 50 100 150 200

1 VOLT STEP RESPONSE

t – Time – ns

– Output Voltage – V
V

O

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +2
RL = 25 Ω
RF = 1.1 kΩ

Figure 34

–3

–2

–1

0

1

2

3

0 50 100 150 200

5 VOLT STEP RESPONSE

t – Time – ns

– Output Voltage – V
V

O

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +5
RL = 25 Ω
RF = 1.1 kΩ

Figure 35

2

0

–4
–6

10 V PULSE RESPONSE

t – Time – ns

0755025 100 125 175150 200 225

–2

8

6

4

–8

250

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +5
RF = 1.1 kΩ
RL = 25 Ω
TR/TF = 6 ns

– Output Voltage – V
V

O

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

ADSL

The THS6032 was primarily designed as a low-power line driver for ADSL (asymmetrical digital subscriber line).
The driver output stage has been sized to provide full ADSL power levels of 20 dBm onto the telephone lines.
Although actual driver output peak voltages and currents vary with each particular ADSL application, the
THS6032 is specified for a minimum full output current of 400 mA at its full output voltage of approximately 1 1 V .
This performance meets the demanding needs of ADSL at the central office end of the telephone line. A typical
ADSL schematic is shown in Figure 36.

_

+

6.8 µF0.1 µF

6.8 µF0.1 µF

V

CC(H)

15 V

200 Ω

+

+

V

I+

_

+

6.8 µF0.1 µF

6.8 µF0.1 µF

–V

CC(H)

–15 V

680 Ω

+

+

V

I–

+

–

0.1 µF

2 kΩ

12.5 Ω

+

–

2 kΩ

1:2

Telephone Line

12.5 Ω

15 V

–15 V

0.1 µF

THS6072

THS6072

V

O+

V

O–

THS6032

Driver 1

THS6032

Driver 2

100 Ω

V

CC(L)

6 V

–V

CC(L)

–6 V

Driver

1 kΩ

1 kΩ

1 kΩ

Receiver

0.1
µF

0.1
µF

680 Ω

1 kΩ

Figure 36. THS6032 ADSL Application

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

ADSL (continued)

The ADSL transmit band consists of 255 separate carrier frequencies, each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as
low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier
frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies.

The THS6032 has been specifically designed for ultralow distortion by careful circuit implementation and by
taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended
distortion measurements are shown in Figures 11 – 15. It is commonly known that in the differential driver
configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion
(THD) will be primarily due to the third order harmonics. Additionally, distortion should be reduced as the
feedback resistance drops. This is because the bandwidth of the amplifier increases, which allows the amplifier
to react faster to any nonlinearities in the closed-loop system.

Another significant point is the fact that distortion decreases as the impedance load increases. This is because
the output resistance of the amplifier becomes less significant as compared to the output load resistance.

One problem that has been receiving a lot of attention in the ADSL area is power dissipation. One way to
substantially reduce power dissipation is to lower the power supply voltages. This is because the RMS voltage
of an ADSL central office signal is 1.65-V RMS at each driver’s output with a 1:2 transformer. But, to meet ADSL
requirements, the drivers must have a voltage peak-to-RMS crest factor of 5.6 in order to keep the bit-error
probability rate below 10

–7

. Hence, the power supply voltages must be high enough to accomplish the driver’s

peak output voltage of 1.65 V × 5.6 = 9.25 V

(PEAK)

.

This high peak output voltage requirement, coupled with a low RMS voltage requirement, does not lend itself
to conventional high efficiency designs. One way to save power is to decrease the bias currents internal to the
amplifier. The drawback of doing this is an increase in distortion and a lower frequency response bandwidth.

This is where the THS6032 class-G architecture is useful. The class-G output stage utilizes both a high supply
voltage [V

CC(H)

typically ±15 V] and a low supply voltage [(V

CC(L)

typically ±6 V]. As long as the output voltage

is less than [V

CC(L)

–2.5 V], then part of the output current will be drawn from the V

CC(L)

supplies. If the output

signal goes above this cutoff point [for example, V

O

> V

CC(L)

–2.5 V], then all of the output current will be supplied

by V

CC(H)

.

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

ADSL (continued)

To ensure that the cutoff point does not introduce distortion into the system, the entire output stage is always
biased on. This constant biasing scheme will cause a decrease in the efficiency over hard switching class-G
circuits, but the very low distortion results tend to outweigh the efficiency loss. The biasing scheme used in the
THS6032 can be shown by the currents being supplied by the V

CC(L)

power supplies in Figure 37. This graph

shows there is no discrete current transfer point between the V

CC(L)

supplies and the V

CC(H)

supplies. This was

done to ensure low distortion throughout the entire output range. By changing the V

CC(L)

supply voltage, the

system efficiency can be tailored to suit almost any system with high crest factor requirements.

Figure 37

70

60

50

0

0123 45 6

Output Current Distribution – %

80

90

RMS – Output Voltage – V

OUTPUT CURRENT DISTRIBUTION

vs

OUTPUT VOLTAGE

100

7

40
30

20
10

V

CC(H)

= 15 V
VI = 1 MHz
RL = 25 Ω

V

CC(L)

= ±7.5 V

V

CC(L)

= ±5 V

I

CC(L)

Current Draw

class-AB mode operation

The class-G architecture produces sizable power dissipation savings over traditional class-AB designs while
maintaining low distortion requirements. The only drawback to the class-G design is the requirement of 4 power
supply voltages, 2 more than a typical line driver requires. In certain instances, the addition of two separate
power supplies may be cost prohibitive or PCB space prohibitive. There are two options in this case, use a
traditional amplifier, such as a THS6012, or use the THS6032 in class-AB mode.

Using the THS6032 in class-AB mode will give several functional benefits over the THS6012. This includes
shutdown capability , low-impedance output while in shutdown state, and a slight reduction in quiescent current.
One important thing to remember is that the THS6032 running in class-AB mode, will be only about as efficient
as the THS6012. This means that the power dissipation of the THS6032 will increase dramatically and must
be accounted for. Failure to do so will result in a part which continuously overheats and may lead to failure.

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

class-AB mode operation (continued)

T o use the THS6032 in class-AB mode, the user should always connect the V

CC(L)

power supply pins to GND.

The internal V

CC(L)

paths were not designed for continuous full output current and could possibly fail. The V

CC(H)

paths were designed for the full output currents and thus, should be used for class-AB mode operation.
The performance of the THS6032 while in class-AB mode is very similar to the class-G mode. Figure 7 and

Figures 12 to15 show the THS6032 while in class-AB mode.

device protection features

The THS6032 has two built-in features that protect the device against improper operation. The first protection
mechanism is output current limiting. Should the output become shorted to ground the output current is
automatically limited to the value given in the data sheet. While this protects the output against excessive
current, the device internal power dissipation increases due to the high current and large voltage drop across
the output transistors. Continuous output shorts are not recommended and could damage the device.
Additionally , connection of the amplifier output to one of the high supply rails [±V

CC(H)

] can cause failure of the

device and is not recommended.
The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above

approximately 180°C, the device automatically shuts down. Such a condition could exist with improper heat
sinking or if the output is shorted to ground. When the junction temperature drops below 150°C, the internal
thermal shutdown circuit automatically turns the device back on.

thermal information

The THS6032 is available in a thermally-enhanced DWP package, which is a member of the PowerP AD family
of packages. This package is constructed using a downset leadframe upon which the die is mounted
[see Figure 38(a) and Figure 38(b)]. This arrangement results in the lead frame being exposed as a thermal pad
on the underside of the package [see Figure 38(c)]. Because this thermal pad has direct thermal contact with
the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal
pad.

DIE

Side View (a)

End View (b)

Bottom View (c)

DIE

Thermal

Pad

NOTE A: The thermal pad is electrically isolated from all terminals in the package.

Figure 38. Views of Thermally Enhanced DWP Package

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

thermal information (continued)

The THS6032 is also available in the MicroStar Junior GQE package. Just like the DWP package, the GQE
package utilizes the PowerP AD functionality to improve thermal performance. The GQE package is part of the
new ball-grid array (BGA) family developed by Texas Instruments (TI). This package allows for even higher
density layouts with virtually no loss in thermal performance. Its construction is similar to the DWP construction
(see Figure 39 (a) and (b)), but utilizes the BGA’s to transfer the heat away from the die.

(TOP VIEW)

(a)

(b)

NOTE: Shaded areas are part of the thermally conductive path.

Die

(Side VIEW)

Figure 39. Views of Thermally Enhanced GQE Package

The PowerP AD packages allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads or balls are being soldered), the thermal areas can
also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper
area, heat can be conducted away from the package into either a ground plane or other heat dissipating device.
This is discussed in more detail in the

PCB design considerations

section of this document.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.

Because of its power dissipation, proper thermal management of the THS6032 is required. There are several
ways to properly heatsink both the DWP and GQE packages. There are several TI application notes on how
to best accomplish the thermal mounting scheme required for each package. For the DWP package, refer to
the T exas Instruments Technical Brief,

PowerP AD Thermally Enhanced Package

, literature number SLMA002.

There is also a more compact technical paper entitled

PowerPad Made Easy

, literature number SLMA004. For

the GQE – MicroStar Junior package, refer to the

MicroStar BGA Packaging Reference Guide

, literature number

SSYZ015A and the compact version entitled

MicroStar Junior Made Easy

, literature number SSYA009. This

literature is available on TI’s web site at

http://www.ti.com.

TI is a trademark of Texas Instruments Incorporated.

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

thermal information (continued)

The actual thermal performance achieved with the THS6032 in its PowerPAD package depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θJA, is about 21.5°C/W for the DWP package and 37.8°C/W for the GQE
package. For a given θ

JA

, the maximum power dissipation is shown in Figure 40 and is calculated by the

following formula:

P

D

+

ǒ

T

MAX–TA

q

JA

Ǔ

Where:

P

D

= Maximum power dissipation of THS6032 (watts)

T

MAX

= Absolute maximum junction temperature (150°C)

T

A

= Free-ambient air temperature (°C)

θ

JA

= θJC + θ

CA

θJC = Thermal coefficient from junction to case (DWP =0.37°C/W; GQE = 4.56°C/W)
θ

CA

= Thermal coefficient from case to ambient

TA – Free-Air Temperature – °C

–40 –20 0 20 80 1006040

MAXIMUM POWER DISSIPATION

vs

FREE-AIR TEMPERATURE

5

3

1
0

4

2

6

7

Maximum Power Dissipation – W

8

9

TJ = 150°C
PCB Size = 3” x 3”
No Air Flow

DWP
θJA = 21.5°C/W
2 oz Trace and
Copper Pad
with Solder

DWP
θJA = 43.9°C/W
2 oz Trace and Copper Pad
without Solder

GQE

Figure 40. Maximum Power Dissipation vs Free-Air Temperature

THS6032
LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

PCB design considerations

Proper PCB design techniques in two areas are important to assure proper operation of the THS6032. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6032 is a
high-speed part, the following guidelines are recommended.

D Ground plane – It is essential that a ground plane be used on the board to provide all components with a

low inductive ground connection. Although a ground connection directly to a terminal of the THS6032 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and
it provides the path for heat removal.

D Input stray capacitance – To minimize potential problems with amplifier oscillation, the capacitance at the

inverting input of the amplifiers must be kept to a minimum. T o do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This
is especially true in the noninverting configuration. An example of this can be seen in Figure 41, which shows
what happens when a 2.2 pF capacitor is added to the inverting input terminal in the noninverting
configuration. The bandwidth increases dramatically at the expense of peaking. This is because some of
the error current is flowing through the stray capacitor instead of the inverting node of the amplifier. While
the device is in the inverting mode, stray capacitance at the inverting input has a minimal effect. This is
because the inverting node is at a virtual ground and the voltage does not fluctuate nearly as much as in
the noninverting configuration. This can be seen in Figure 42, where a 27-pF capacitor adds only 2.5 dB
of peaking. In general, as the gain of the system increases, the output peaking due to this capacitor
decreases. While this can initially appear to be a faster and better system, overshoot and ringing are more
likely to occur under fast transient conditions. So, proper analysis of adding a capacitor to the inverting input
node should always be performed for stable operation.

Figure 41

–5

–4

–3

–2

–1

0

1

2

3

4

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +1
RL = 25 Ω
VO = 0.2 V

RMS

1 M 10 M 100 M100 k 500 M

Ci = 2.2 pF

Output Amplitude – dB

Ci = 0 pF

1.3 kΩ

C

i

V

I

+

–

V

O

25 Ω

50 Ω

Figure 42

–5

–4

–3

–2

–1

0

1

2

3

4

OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = –1
RL = 25 Ω
VO = 0.2 V

RMS

1 M 10 M 100 M100 k 500 M

Ci = 27 pF

Output Amplitude – dB

Ci = 0 pF

1.1 kΩ

C

i

V

I

+

–

V

O

RL = 25 Ω

50 Ω

1.1 kΩ

THS6032

LOW-POWER ADSL CENTRAL-OFFICE LINE DRIVER

SLOS233C – APRIL1999 – REVISED MARCH 2000

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

PCB design considerations (continued)

D Proper power supply decoupling – Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF

ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the
supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible
to the supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor
less effective. The designer should strive for distances of less than 0.1 inches between the device power
terminal and the ceramic capacitors.

D Differential power supply decoupling – The THS6032 was designed for driving low-impedance differential

signals. The 25 Ω load which each amplifier drives causes large amounts of currents to flow from amplifier
to amplifier. Power supply decoupling for differential current signals must be accounted for to ensure low
distortion of the THS6032. By simply connecting a 0.1-µF ceramic capacitor from the +V

CC(H)

pin to the

–V

CC(H)

pin, along with another 0.1-µF ceramic capacitor from the +V

CC(L)

pin to the –V

CC(L)

pin, differential
current loops will be minimized (see Figure 36). This will help keep the THS6032 operating at peak
performance.

recommended feedback and gain resistor values

As with all current feedback amplifiers, the bandwidth of the THS6032 is an inversely proportional function of
the value of the feedback resistor. This can be seen from Figures 1 to 6. The recommended resistors for the
optimum frequency response with a 25-Ω load system can be seen in Table 1. These should be used as a
starting point and once optimum values are found, 1% tolerance resistors should be used to maintain frequency
response characteristics. For most applications, a feedback resistor value of 1.3 kΩ is recommended, which
is a good compromise between bandwidth and phase margin that yields a very stable amplifier.

Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor . This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and the internal dominant-pole capacitor. The ability to control the amplifier gain independently
of the bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage
feedback amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust
the value of the gain resistor to increase or decrease the overall amplifier gain.

Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance
decreases the loop gain and increases the distortion. It is also important to know that decreasing load
impedance increases total harmonic distortion (THD). Typically, the third order harmonic distortion increases
more than the second order harmonic distortion.

Table 1. Recommended Feedback Resistor Values for 25 Ω Loads

GAIN R

f

1 1.3 kΩ

2, –1 1.1 kΩ

5 820 Ω

7.8 680 Ω
10 510 Ω

THS6032
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APPLICATION INFORMATION

shutdown control

There are two shutdown pins which control the shutdown for each amplifier of the THS6032. When the shutdown
pin signals are low, the THS6032 is active. But, when a shutdown pin is high (≥2 V), the corresponding amplifier
is turned off. The shutdown logic is not latched and should always have a signal applied to it. To help ensure
a fixed logic state, an internal 50 kΩ resistor to DGND is utilized. An external resistor, such as a 3.3 kΩ, to DGND
may be added to help improve noise immunity within harsh environments. If no external resistor is utilized and
SHDN

X

pins are left unconnected, the THS6032 will default to a power-on state. A simplified circuit can be seen

in Figure 43

.

+V

CC(H)

To Internal

Bias Circuitry

Control

–V

CC(H)

DGND

DGND

50 kΩ

SHDN

X

Figure 43. Simplified THS6032 Shutdown Control Circuit

shutdown function

The THS6032 incorporates a shutdown circuit to conserve power. T raditionally when an amplifier is placed into
shutdown mode, the input and output circuitry are turned off. This conserves a large amount of power , but the
output impedance will be a very high, typically greater than several kΩ. This situation does not allow for proper
line termination resulting in a severe reduction of the receive signal coming through the transmission line (see
Figure 36).

The THS6032 eliminates this problem. When the SHDNX pin voltage is greater than 2 V , the THS6032 enters
shutdown mode to conserve power. Unlike the traditional amplifier , the THS6032’s output impedance is typically

0.5 Ω at 1 MHz (see Figure 28). The shutdown mode function results in the proper termination of the line without
degradation in performance of the receive signal coming through the transmission line.

There are a few design considerations in order to fully achieve this type of functionality. To better understand
these design considerations, it is helpful to examine what is happening inside the THS6032. Figure 44 shows
the simplified shutdown components. Notice that there are two similar input stages; the normal input stage
consisting of transistors Q

1

through Q4 and the shutdown input stage consisting of transistors QS1 through QS4.

When in shutdown mode, the I

(BIAS–1)

and I

(BIAS–2)

current sources are turned off. This turns off the normal

input stage of the amplifier. The I

(BIAS–S1)

and I

(BIAS–S2)

current sources are then turned on. The shutdown
input stage signals are then fed through the same internal circuitry which the normal input stage drove. This
allows for sinking and sourcing large amounts of current at the output of the THS6032 during shutdown
operation. The Q

S1

through QS4 transistors are not designed for the performance like the Q1 through Q

4

transistors because their only function is to amplify the DC ground reference, DGND. A 1-kΩ resistor connects
internally to the output node of the amplifier, which provides a feedback loop in shutdown mode. This forces the
output impedance to become very small, making for proper transmission line termination.

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APPLICATION INFORMATION

shutdown function (continued)

1 kΩ

To Internal

Output

Node

Q

2

+IN
Pin

–IN

Pin

To Output

Drive

Circuitry

Q

1

Q

3

Q

4

Q

5

Q

6

+V

CC(H)

I

BIAS–1

I

BIAS–2

DGND

Q

S1

I

BIAS–S1

I

BIAS–S2

Q

S2

Q

S3

Q

S4

Shut–Down Circuitry

Active

Load

Active

Load

CC(H)

–V

Figure 44. Simplified THS6032 Input Stages

Because the DGND pin voltage is effectively at a noninverting terminal, any signal or voltage fluctuation at this
node is amplified by the THS6032. This could possibly cause a noisy output to appear during shutdown
operation. Figure 45 shows the frequency response of the THS6032 due to an input signal at the DGND
terminal. The maximum DGND voltage signal which the THS6032 will follow linearly during shutdown operation
is less than ±4 V. With this dynamic range capability, it is recommended that the DGND pin be as noise-free
as possible to ensure proper transmission line termination.

Figure 45

–6

–5

–4

–3

–2

–1

0

1

2

3

DGND OUTPUT AMPLITUDE

vs

FREQUENCY

f – Frequency – Hz

100 k 1 M 10 M 100 M

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
RL = 25 Ω
VSD = +10 V
VI = DGND Pin

DGND Output Amplitude – dB

V

O(PP)

= 0.2 V

V

O(PP)

= 2 V

THS6032
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APPLICATION INFORMATION

shutdown function (continued)

The second design consideration is due to transistors Q5 and Q6. These transistors ensure the +IN to – IN
voltage separation is less than a VBE drop (about 0.7 V). This protects the other transistors, Q1 to Q4, from
saturating during fast transients. Transistors Q5 and Q6 also enhance the slew rate capabilities of the THS6032.
When a fast transient is applied to the input, these transistors will quickly apply the currents to the active load
stages. A design issue with this setup is that while in shutdown mode, a large enough signal being applied to
the input pins may turn on these transistors. Once the input voltage differential between the +IN and –IN pins
reaches ±0.7-V, transistors Q

5

and Q6 turn on applying the difference signal to the rest of the amplifier circuitry .
Because these two transistors are designed for much higher performance levels than the shutdown circuitry
transistors (QS3 and QS4), they will become dominant and the difference input signal will be utilized instead of
the DGND signal. Because the external negative feedback resistor path is still connected around the amplifier,
this difference input signal will be amplified just like a normal amplifier is designed to do (see Figure 46). As long
as the +IN and –IN input signals are kept below ±0.7 V , the isolation from input-to-output is very high as shown
in the Shutdown Isolation vs Frequency graphs (see Figures 30 and 31).

To ensure proper shutdown functionality of the THS6032, it is important to keep the DGND voltage noise-free.
Additionally, the +IN and – IN signals should be limited to less than ±0.7 V during shutdown mode. This will
ensure proper line termination functionality while conserving power.

Figure 46

0

1

2

3

4

5

6

7

0246810

SHUTDOWN FEEDTHROUGH

VIN – Input Voltage – V

V

CC(H)

= ± 15 V

V

CC(L)

=± 5 V
RL = 25 Ω
VSD = 5 V

OUT

– Output Voltage – VV

G = 5

G = 2

G = +1;
G = –1

slew rate

The slew rate performance of a current feedback amplifier, like the THS6032, is affected by many different
factors. Some of these factors are external to the device, such as amplifier configuration and PCB parasitics,
and others are internal to the device, such as available currents and node capacitance. Understanding some
of these factors should help the PCB designer arrive at a more optimum circuit with fewer problems.

THS6032

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APPLICATION INFORMATION

slew rate (continued)

Whether the THS6032 is used in an inverting amplifier configuration or a noninverting configuration can impact
the output slew rate. Slew rate performance in the inverting configuration is generally faster than the
noninverting configuration. This is because in the inverting configuration the input terminals of the amplifier are
at a virtual ground and do not significantly change voltage as the input changes. Consequently, the time to
charge any capacitance on these input nodes is less than for the noninverting configuration, where the input
nodes actually do change in voltage an amount equal to the size of the input step. In addition, any PCB parasitic
capacitance on the input nodes degrades the slew rate further simply because there is more capacitance to
charge. If the main supply voltage V

CC(H)

to the amplifier is reduced, slew rate decreases because there is less
current available within the amplifier to charge the capacitance on the input nodes as well as other internal
nodes. Also, as the load resistance decreases, the slew rate typically decreases due to the increasing internal
currents, which slow down the transitions.

Internally , the THS6032 has other factors that impact the slew rate. The amplifier’s behavior during the slew rate
transition varies slightly depending upon the rise time of the input. This is because of the way the input stage
handles faster and faster input edges. Slew rates (as measured at the amplifier output) of less than about
1200 V/µs are processed by the input stage in a very linear fashion. Consequently, the output waveform
smoothly transitions between initial and final voltage levels. For slew rates greater than 1200 V/µs, additional
slew-enhancing transistors present in the input stage (transistors Q5 and Q6 in Figure 44) begin to turn on to
support these faster signals. The result is an amplifier with extremely fast slew rate capabilities. The additional
aberrations present in the output waveform with these faster slewing input signals are due to the brief saturation
of the internal current mirrors. This phenomenon, which typically lasts less than 20 ns, is considered normal
operation and is not detrimental to the device in any way . If for any reason this type of response is not desired,
then increasing the feedback resistor or slowing down the input signal slew rate reduces the effect.

Figure 47

2

0

–4
–6

SLEWING 10 V PULSE

t – Time – ns

0 50 100 150 200

–2

8

6

4

–8

250

SR = 1400 V/

µs

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +5
RF = 1.1 kΩ
RL = 25 Ω
TR/TF = 1 ns

– Output Voltage – V
V

O

25 75 125 175 225

Figure 48

4

0

–8

–12

SLEWING 20 V PULSE

t – Time – ns

0 50 100 150 200

–4

16

12

8

–16

250

SR = 4000 V/

µs

V

CC(H)

= ± 15 V

V

CC(L)

= ± 5 V
Gain = +5
RF = 1.1 kΩ
RL = 25 Ω
TR/TF = 1 ns

– Output Voltage – V
V

O

25 75 125 175 225

THS6032
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APPLICATION INFORMATION

noise calculations and noise figure

Noise can cause errors on very small signals. This is especially true for the amplifying small signals. The noise
model for current feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only
difference between the two is that the CFB amplifiers generally specify different current noise parameters for
each input, while VFB amplifiers usually only specify one noise current parameter. The noise model is shown
in Figure 49. This model includes all of the noise sources as follows:

• e

n

= Amplifier internal voltage noise (nV/√Hz)

• IN+ = Noninverting current noise (pA/√Hz)

• IN– = Inverting current noise (pA/√Hz)

• e

Rx

= Thermal voltage noise associated with each resistor (eRx = 4 kTRx)

_

+

R

F

R

S

R

G

e

Rg

e

Rf

e

Rs

e

n

IN+

Noiseless

IN–

e

ni

e

no

Figure 49. Noise Model

The total equivalent input noise density (eni) is calculated by using the following equation:

e

ni

+

ǒ

e

n

Ǔ

2

)

ǒ

IN ) R

S

Ǔ

2

)

ǒ

IN– ǒRFø R

G

Ǔ

Ǔ

2

) 4kTRs) 4kTǒRFø R

G

Ǔ

Ǹ

Where:

k = Boltzmann’s constant = 1.380658 × 10

–23

T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and R

G

To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).

eno+ eniAV+ e

ni

ǒ

1 )

R

F

R

G

Ǔ

(Noninverting Case)

THS6032

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APPLICATION INFORMATION

noise calculations and noise figure (continued)

As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.

For more information on noise analysis, please refer to

Noise Analysis in Operational Amplifier Circuits

,

literature number SLVA043A
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise

figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.

NF + 10log

ȧ

ȱ
Ȳ

e

2

ni

ǒ

e

Rs

Ǔ

2

ȧ

ȳ
ȴ

Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:

NF + 10log

ȧ

ȧ
ȧ
ȧ
ȧ

ȱ

Ȳ

1 )

ȧ

ȡ
Ȣ

ǒ

e

n

Ǔ

2

)

ǒ

IN ) R

S

Ǔ

2

ȧ

ȣ
Ȥ

4kTR

S

ȧ

ȧ
ȧ
ȧ
ȧ

ȳ

ȴ

THS6032
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APPLICATION INFORMATION

noise calculations and noise figure (continued)

Figure 50 shows the noise figure graph for the THS6032.

NOISE FIGURE

vs

SOURCE RESISTANCE

Noise Figure – dB

0

2

4

6

8

10

12

14

16

18

20

10 100 1000 10000

Source Resistance – R

S (Ω)

f = 10 kHz
T

A

= 25 Deg. C

Figure 50. Noise Figure vs Source Resistance

offset voltage

The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB)
times the corresponding gains. Figure 51 can be used to calculate the output offset voltage.

VOO+ V

IO

ǒ

1 ) ǒ

R

F

R

G

Ǔ

Ǔ

" I

IB)

R

S

ǒ

1 ) ǒ

R

F

R

G

Ǔ

Ǔ

" I

IB–RF

+

–

V

I

+

R

G

R

S

R

F

I

IB–

V

O

I

IB+

Figure 51. Output Offset Voltage Model

THS6032

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APPLICATION INFORMATION

general configurations

A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS6032,
like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors
directly from the output to the inverting input is not recommended. This is because, at high frequencies, a
capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when
using a current-feedback amplifier. Because of this, simple low-pass filters, which are easily implemented on
a VFB amplifier, have to be designed slightly dif ferently. If filtering is required, simply place an RC-filter at the
noninverting terminal of the operational-amplifier (see Figure 52).

V

I

V

O

C1

+

–

R

G

R

F

R1

f

–3dB

+

1

2pR1C1

V

O

V

I

+ ǒ1 )

R

F

R

G

Ǔ

ǒ

1

1 ) sR1C1

Ǔ

Figure 52. Single-Pole Low-Pass Filter

If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because
of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. One implementation of the Sallen-Key filter is shown in Figure 53. For more information on Sallen-Key
filters, refer to the

Analysis of the Sallen-Key Architecture

, literature number SLOA024A.

V

I

C2

R2R1

C1

R

F

R

G

R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)

(

=

1

Q

2 –

)

R

G

R

F

_

+

f

–3dB

+

1

2pRC

Figure 53. 2-Pole Low-Pass Sallen-Key Filter

Another good use for the THS6032 amplifiers is as video distribution amplifiers. One characteristic of distribution
amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the
number of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout
the distribution system to minimize reflections and capacitive loading.

THS6032
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APPLICATION INFORMATION

general configurations (continued)

+

–

1.1 kΩ1.1 kΩ

75 Ω

75 Ω

75 Ω

75 Ω

75 Ω

N Lines

V

O1

V

ON

THS6032

75 Ω Transmission Line

V

I

1/2

Figure 54. Video Distribution Amplifier Application

driving a capacitive load

Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS6032 has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 55. A minimum value of 10 Ω should work well for most applications. For
example, in ADSL systems, setting the series resistor value to 12.5 Ω both isolates any capacitance loading
and provides the proper line impedance matching at the source end.

+

_

THS6032

C

LOAD

1.1 kΩ

Input

Output

1.1 kΩ
10 Ω

Figure 55. Driving a Capacitive Load

evaluation board

Evaluation boards are available for the THS6032. Each board has been configured for proper thermal
management of the THS6032 depending on package selection. The circuitry has been designed for a typical
ADSL application as shown previously in this document. To order the evaluation board, contact your local TI
sales office or distributor.

THS6032

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MECHANICAL DATA

DWP (R-PDSO-G**) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

Gage Plane

0.419 (10,65)

0.400 (10,16)

0.010 (0,25) NOM

Thermal Pad
(See Note D)

0.010 (0,25)

0.016 (0,40)

0.050 (1,27)

Seating Plane

4147575/A 04/98

11

10

A

20-PIN SHOWN

20

1

0.104 (2,65) MAX

0.293 (7,45)

0.299 (7,59)

0.020 (0,51)

0.014 (0,35)

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–ā8°

0.710

28

0.510200.610

24

0.700

(18,03)

(17,78)

0.500

(15,49)

(15,24)

0.600

0.410

16

DIM

PINS **

(10,41)

(10,16)

0.400

A MIN

A MAX

(12,95)

(12,70)

0.006 (0,15)

0.002 (0,05)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

PowerPAD is a trademark of Texas Instruments Incorporated.

THS6032
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MECHANICAL DATA

GQE (S-PLGA-N80) PLASTIC LAND GRID ARRAY

98765

J
H
G
F
E
D

321

C
B
A

4

4,00 TYP

Seating Plane

5,20
4,80

SQ

0,87

0,93

0,08 MAX

0,23

0,33

1,00 MAX

0,50

0,50

0,08

M

∅ 0,05

4200461/A 10/99

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. MicroStar Junior LGA configuration

MicroStar Junior LGA is a trademark of Texas Instruments Incorporated.

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright  2000, Texas Instruments Incorporated