Datasheet THS5671EVM, THS5671AIPWR, THS5671AIPW, THS5671AIDWR, THS5671AIDW Datasheet (Texas Instruments)

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Page 1

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Member of the Pin-Compatible CommsDAC Product Family

125 MSPS Update Rate

14-Bit Resolution

Spurious Free Dynamic Range (SFDR) to Nyquist at 40 MHz Output: 63 dBc

1 ns Setup/Hold Time

Differential Scalable Current Outputs: 2 mA to 20 mA

On-Chip 1.2 V Reference

3 V and 5 V CMOS-Compatible Digital Interface

Straight Binary or Twos Complement Input

Power Dissipation: 175 mW at 5 V, Sleep Mode: 25 mW at 5 V

Package: 28-Pin SOIC and TSSOP

description

The THS5671A is a 14-bit resolution digital-to-analog converter (DAC) specifically optimized for digital data transmission in wired and wireless communication systems. The 14-bit DAC is a member of the CommsDAC series of high-speed, low-power CMOS digital-to-analog converters. The CommsDAC family consists of pin compatible 14-, 12-, 10-, and 8-bit DACs. All devices offer identical interface options, small outline package, and pinout. The THS5671A offers superior ac and dc performance while supporting update rates up to 125 MSPS.

The THS5671A operates from an analog supply of 4.5 V to 5.5 V . Its inherent low power dissipation of 175 mW ensures that the device is well-suited for portable and low-power applications. Lowering the full-scale current output reduces the power dissipation without significantly degrading performance. The device features a SLEEP mode, which reduces the standby power to approximately 25 mW, thereby optimizing the power consumption for system needs.

The THS5671A is manufactured in Texas Instruments advanced high-speed mixed-signal CMOS process. A current-source-array architecture combined with simultaneous switching shows excellent dynamic performance. On-chip edge-triggered input latches and a 1.2 V temperature-compensated bandgap reference provide a complete monolithic DAC solution. The digital supply range of 3 V to 5.5 V supports 3 V and 5 V CMOS logic families. Minimum data input setup and hold times allow for easy interfacing with external logic. The THS5671A supports both a straight binary and twos complement input word format, enabling flexible interfacing with digital signal processors.

The THS5671A provides a nominal full-scale differential output current of 20 mA and >300 kΩ output impedance, supporting both single-ended and differential applications. The output current can be directly fed to the load (e.g., external resistor load or transformer), with no additional external output buffer required. An accurate on-chip reference and control amplifier allows the user to adjust this output current from 20 mA down to 2 mA, with no significant degradation of performance. This reduces power consumption and provides 20 dB gain range control capabilities. Alternatively , an external reference voltage and control amplifier may be applied in applications using a multiplying DAC. The output voltage compliance range is 1.25 V.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

D13 D12 D11 D10

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

CLK DV

DGND MODE AV

COMP2 IOUT1 IOUT2 AGND COMP1 BIASJ EXTIO EXTLO SLEEP

SOIC (DW) OR TSSOP (PW) PACKAGE

(TOP VIEW)

CommsDAC is a trademark of Texas Instruments Incorporated.

Page 2

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The THS5671A is available in both a 28-pin SOIC and TSSOP package. The device is characterized for operation over the industrial temperature range of –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

28-TSSOP

(PW)

28-SOIC

(DW)

–40°C to 85°C THS5671AIPW THS5671AIDW

functional block diagram

IOUT1

IOUT2

CLK

D[13:0]

EXTLO

DGND

EXTIO

COMP2

Current

Source

Array

Output

Current

Switches

AGND

1.2 V REF

BIASJ

–

Control AMP

0.1 µF

2 kΩ

BIAS

COMP1

Logic

Control

50 Ω

1 nF

BIAS

SLEEP

MODE

LOAD

EXT

0.1 µF 0.1 µF

50 Ω

Page 3

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 20 I Analog ground return for the internal analog circuitry AV

24 I Positive analog supply voltage (4.5 V to 5.5 V) BIASJ 18 O Full-scale output current bias CLK 28 I External clock input. Input data latched on rising edge of the clock. COMP1 19 I Compensation and decoupling node, requires a 0.1 µF capacitor to AVDD. COMP2 23 I Internal bias node, requires a 0.1 µF decoupling capacitor to AGND. D[13:0] [1:14] I Data bits 0 through 13.

D13 is most significant data bit (MSB), D0 is least significant data bit (LSB). DGND 26 I Digital ground return for the internal digital logic circuitry DV

27 I Positive digital supply voltage (3 V to 5.5 V)

EXTIO 17 I/O Used as external reference input when internal reference is disabled (i.e., EXTLO = AVDD). Used as internal

reference output when EXTLO = AGND, requires a 0.1 µF decoupling capacitor to AGND when used as reference

output. EXTLO 16 O Internal reference ground. Connect to A VDD to disable the internal reference source. IOUT1 22 O DAC current output. Full scale when all input bits are set 1 IOUT2 21 O Complementary DAC current output. Full scale when all input bits are 0 MODE 25 I Mode select. Internal pulldown. Mode 0 is selected if this pin is left floating or connected to DGND. See

timing diagram. SLEEP 15 I Asynchronous hardware power down input. Active high. Internal pulldown. Requires 5 µs to power down but 3 ms

to power up.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, AVDD (see Note 1) –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DVDD (see Note 2) –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage between AGND and DGND –0.3 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, AV

to DVDD –6.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLK, SLEEP, MODE (see Note 2) –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . .

Digital input D13–D0 (see Note 2) –0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . .

IOUT1, IOUT2 (see Note 1) –1 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

COMP1, COMP2 (see Note 1) –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . .

EXTIO, BIASJ (see Note 1) –0.3 V to AV

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

EXTLO (see Note 1) –0.3 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs) –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: THS5671AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Measured with respect to AGND.

2. Measured with respect to DGND.

Page 4

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DV

= 5 V, IOUTFS = 20 mA (unless otherwise noted)

dc specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 14 Bits DC accuracy

†

INL Integral nonlinearity

–7 ±2.5 7 LSB

DNL Differential nonlinearity

= –

40°C to 85°C

–3.5 ±2 3.5 LSB

Monotonicity At 11-bit level Monotonic Analog output

Offset error 0.02 %FSR

Without internal reference 2.3

Gain error

With internal reference 1.3

%FSR

Full scale output current

‡

2 20 mA Output compliance range AVDD = 5 V, IOUTFS = 20 mA –1 1.25 V Output resistance 300 kΩ Output capacitance 5 pF

Reference output

Reference voltage 1.18 1.22 1.32 V Reference output current

100 nA

Reference input

EXTIO

Input voltage range 0.1 1.25 V Input resistance 1 MΩ Small signal bandwidth

Without C

COMP1

1.3 MHz

Input capacitance 100 pF

Temperature coefficients

Offset drift 0

Without internal reference ±40

ppm of

Gain drift

With internal reference ±120

m of

FSR/°C

Reference voltage drift ±35

Power supply

Analog supply voltage 4.5 5 5.5 V

Digital supply voltage 3 5.5 V Analog supply current 25 30 mA

AVDD

Sleep mode supply current Sleep mode 3 5 mA

DVDD

Digital supply current

5 6 mA

Power dissipation

AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA 175 mW

±0.4

Power supply rejection ratio

±0.025

%FSR/V

Operating range –40 85 °C

†

Measured at IOUT1 in virtual ground configuration.

‡

Nominal full-scale current IOUTFS equals 32X the IBIAS current.

Use an external buffer amplifier with high impedance input to drive any external load.

Reference bandwidth is a function of external cap at COMP1 pin and signal level.

Measured at f

CLK

= 50 MSPS and f

OUT

= 1 MHz.

Measured for 50 Ω R

LOAD

at IOUT1 and IOUT2, f

CLK

= 50 MSPS and f

OUT

= 20 MHz.

Specifications subject to change

Page 5

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DV

= 5 V , IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load

(unless otherwise noted)

ac specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Analog output

DVDD = 4.5 V to 5.5 V 100 125

CLK

Maximum output update rate

DVDD = 3 V to 3.6 V 70 100

MSPS

s(DAC)

Output settling time to 0.1%

†

35 ns

Output propagation delay 1 ns

GE Glitch energy

‡

Worst case LSB transition (code 8191 – code 8192) 5 pV-s

r(IOUT)

Output rise time 10% to 90%

†

1 ns

f(IOUT)

Output fall time 90% to 10%

†

1 ns

IOUTFS = 20 mA 15

Output noise

IOUTFS = 2 mA 10

A/√HZ

AC linearity

CLK

= 25 MSPS, f

OUT

= 1 MHz, TA = 25°C –74

CLK

= 50 MSPS, f

OUT

= 1 MHz, TA = –40°C to 85°C –73 –66

THD

Total harmonic distortion

CLK

= 50 MSPS, f

OUT

= 2 MHz, TA = 25°C –71

dBc

CLK

= 100 MSPS, f

OUT

= 2 MHz, TA = 25°C –71

CLK

= 25 MSPS, f

OUT

= 1 MHz, TA = 25°C 82

CLK

= 50 MSPS, f

OUT

= 1 MHz, TA = –40°C to 85°C 68

CLK

= 50 MSPS, f

OUT

= 1 MHz, TA = 25°C 82

CLK

= 50 MSPS, f

OUT

= 2.51 MHz, TA = 25°C 75

dBc

purious free dynamic range to

CLK

= 50 MSPS, f

OUT

= 5.02 MHz, TA = 25°C 74

Nyquist

CLK

= 50 MSPS, f

OUT

= 20.2 MHz, TA = 25°C 57

SFDR

CLK

= 100 MSPS, f

OUT

= 5.04 MHz, TA = 25°C 70 dBc

CLK

= 100 MSPS, f

OUT

= 20.2 MHz, TA = 25°C 66 dBc

CLK

= 100 MSPS, f

OUT

= 40.4 MHz, TA = 25°C 63 dBc

CLK

= 50 MSPS, f

OUT

= 1 MHz, TA= 25°C,1 MHz span 90

purious free dynamic range

CLK

= 50 MSPS, f

OUT

= 5.02 MHz, 2 MHz span 89

dBc

within a window

CLK

= 100 MSPS, f

OUT

= 5.04 MHz, 4 MHz span 89

†

Measured single ended into 50 Ω load at IOUT1.

‡

Single-ended output IOUT1, 50 Ω doubly terminated load.

Measured with a 50%/50% duty cycle (high/low percentage of the clock). Optimum ac linearity is obtained when limiting the duty cycle to a range from 45%/55% to 55%/45%.

Page 6

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, AVDD = 5 V, DV

= 5 V, IOUTFS = 20 mA (unless otherwise noted)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Interface

DVDD = 5 V 3.5 5

VIHHigh-level input voltage

DVDD = 3.3 V 2.1 3.3

DVDD = 5 V 0 1.3

VILLow-level input voltage

DVDD = 3.3 V 0 0.9

High-level input current DVDD = 3 V to 5.5 V –10 10 µA

Low-level input current DVDD = 3 V to 5.5 V –10 10 µA

Input capacitance 1 5 pF

Timing

su(D)

Input setup time 1 ns

h(D)

Input hold time 1 ns

w(LPH)

Input latch pulse high time 4 ns

d(D)

Digital delay time

1 clk

Specifications subject to change

Page 7

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

0 1020304050

Figure 1

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 0 dBFS

out

– Output Frequency – MHz

CLK

= 5 MSPS

SFDR – Spurious Free Dynamic Range – dBc

CLK

= 50 MSPS

CLK

= 70 MSPS

DVDD = 5 V

CLK

= 25 MSPS

CLK

= 100 MSPS

CLK

= 125 MSPS

Figure 2

0 0.5 1.0 1.5 2.0 2.5

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 5 MSPS

out

– Output Frequency – MHz

0 dBFS

SFDR – Spurious Free Dynamic Range – dBc

–6 dBFS

–12 dBFS

DVDD = 5 V

024681012

Figure 3

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 25 MSPS

out

– Output Frequency – MHz

–6 dBFS

SFDR – Spurious Free Dynamic Range – dBc

–12 dBFS

0 dBFS

DVDD = 5 V

0 5 10 15 20 25

Figure 4

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 50 MSPS

out

– Output Frequency – MHz

–6 dBFS

SFDR – Spurious Free Dynamic Range – dBc

–12 dBFS

0 dBFS

DVDD = 5 V

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise

noted.)

Page 8

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

0 10203040

Figure 5

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 70 MSPS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

–12 dBFS

–6 dBFS

0 dBFS

DVDD = 5 V

Figure 6

0 1020304050

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 100 MSPS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

–12 dBFS

–6 dBFS

0 dBFS

DVDD = 5 V

0 1020304050

Figure 7

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 125 MSPS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 5 V

–12 dBFS

–6 dBFS

0 dBFS

0 10203040

Figure 8

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 0 dBFS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 3.3 V

CLK

= 5 MSPS

CLK

= 50 MSPS

CLK

= 25 MSPS

CLK

= 100 MSPS

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise

noted.)

Page 9

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

Figure 9

0 0.5 1.0 1.5 2.0

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 5 MSPS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 3.3 V

–12 dBFS

–6 dBFS

0 dBFS

0246810

Figure 10

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 25 MSPS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 3.3 V

–12 dBFS

0 dBFS

–6 dBFS

Figure 11

0 5 10 15 20 25

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 50 MSPS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 3.3 V

–12 dBFS

–6 dBFS

0 dBFS

0 10203040

Figure 12

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 70 MSPS

out

– Output Frequency – MHz

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 3.3 V

–12 dBFS

–6 dBFS

0 dBFS

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise

noted.)

Page 10

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

Figure 13

–27 –24 –21 –18 –15 –12 –9 –6 –3 0

SPURIOUS FREE DYNAMIC RANGE

OUT

AT F

OUT

= F

CLOCK

/11

out

– dBFS

2.27 MHz @ 25 MSPS

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 5 V

4.55 MHz @ 50 MSPS

6.36 MHz @ 70 MSPS

9.1 MHz @ 100 MSPS

Figure 14

–27 –24 –21 –18 –15 –12 –9 –6 –3 0

SPURIOUS FREE DYNAMIC RANGE

OUT

AT F

OUT

= F

CLOCK/5

out

– dBFS

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 5 V

20 MHz @ 100 MSPS

5 MHz @ 25 MSPS

10 MHz @ 50 MSPS

14 MHz @ 70 MSPS

Figure 15

–27 –24 –21 –18 –15 –12 –9 –6 –3 0

DUAL TONE SPURIOUS FREE DYNAMIC RANGE

OUT

AT F

OUT

= F

CLOCK/7

out

– dBFS

SFDR – Spurious Free Dynamic Range – dBc

DVDD = 5 V

0.675/0.725 MHz @ 5 MSPS

3.38/3.63 MHz @ 25 MSPS

6.75/7.25 MHz @ 50 MSPS

9.67/10.43 MHz @ 70 MSPS

13.5/14.5 MHz @ 100 MSPS

Figure 16

–90

–84

–78

–72

–66

0 20406080100120

TOTAL HARMONIC DISTORTION

CLOCK FREQUENCY AT F

OUT

= 2 MHZ

clock

– Clock Frequency – MSPS

2nd Harmonic

THD – Total Harmonic Distortion – dBc

DVDD = 5 V

3rd Harmonic

4th Harmonic

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise

noted.)

Page 11

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

2 4 6 8 101214161820

SFDR – Spurious Free Dynamic Range – dBc

out

= 10 MHz

out

= 40 MHz

DVDD = 5 V

IOUTFS – Full-Scale Output Current – mA

out

= 28.6 MHz

Figure 17

SPURIOUS FREE DYNAMIC RANGE

FULL-SCALE OUTPUT CURRENT AT 100 MSPS

out

= 2.5 MHz

Figure 18

0 5 10 15 20 25 30 35 40 45 50

SPURIOUS FREE DYNAMIC RANGE

OUTPUT FREQUENCY AT 100 MSPS

out

– Output Frequency – MHz

DIFF @ 0 dBFS

SFDR – Spurious Free Dynamic Range – dBc

DIFF @ –6 dBFS

IOUT1 @ –6 dBFS

IOUT1 @ 0 dBFS

DVDD = 5 V

Figure 19

–40 –20 0 20 40 60 80

SPURIOUS FREE DYNAMIC RANGE

TEMPERATURE AT 70 MSPS

TA – Temperature – °C

out

= 2 MHz

SFDR – Spurious Free Dynamic Range – dBc

out

= 10 MHz

out

= 25 MHz

DVDD = 5 V

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise

noted.)

Page 12

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

Figure 20

INL – Integral Nonlinearity – LSB

Code

INTEGRAL NONLINEARITY

–4

–2

2048

4096

6144

8192 10240

12288

14336

16384

Figure 21

DNL – Differential Nonlinearity – LSB

Code

DIFFERENTIAL NONLINEARITY

–2

–1

2048

4096 6144

8192

10240 12288

14336

16384

–3

–4

Figure 22

Amplitude – dBm

SINGLE-TONE OUTPUT SPECTRUM

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 5 10 15 20 25

out

= 5 MHz at

clock

= 50 MSPS,

DVDD = 5 V

Frequency – MHz

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise

noted.)

Page 13

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

Figure 23

Amplitude – dBm

SINGLE-TONE OUTPUT SPECTRUM

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 1020304050

out

= 10 MHz at

clock

= 100 MSPS,

DVDD = 5 V

Frequency – MHz

Figure 24

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 1020304050

Amplitude – dBm

Frequency – MHz

DUAL-TONE OUTPUT SPECTRUM

clock

= 100 MSPS

out1

= 13.2 MHz,

out2

= 14.2 MHz,

DVDD = 5 V

Figure 25

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0 5 10 15 20 25

Amplitude – dBm

Frequency – MHz

FOUR-TONE OUTPUT SPECTRUM

clock

= 50 MSPS

out1

= 6.25 MHz,

out2

= 6.75 MHz,

out3

= 7.25 MHz,

out4

= 7.75 MHz,

DVDD = 5 V

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)

Page 14

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

†

Figure 26

2 4 6 8 101214161820

SUPPLY CURRENT

FULL-SCALE OUTPUT CURRENT

IOUTFS – Full-Scale Output Current – mA

I(AVDD) – Supply Current – mA

DVDD = 5 V

Figure 27

0 0.1 0.2 0.3 0.4 0.5

DIGITAL SUPPLY CURRENT

RATIO (Fclock/Fout) AT DV

= 5 V

Ratio – (Fclock/Fout)

100 MSPS

I(DVDD) – Supply Current – mA

70 MSPS

50 MSPS

25 MSPS

5 MSPS

Figure 28

0 0.1 0.2 0.3 0.4 0.5

5 MSPS

DIGITAL SUPPLY CURRENT

RATIO (Fclock/Fout) AT DV

= 3.3 V

Ratio – (Fclock/Fout)

I(DVDD) – Supply Current – mA

25 MSPS

50 MSPS

70 MSPS

†AV

= 5 V, IOUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly terminated load, TA = 25°C (unless otherwise noted.)

Page 15

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The THS5671A architecture is based on current steering, combining high update rates with low power consumption. The CMOS device consists of a segmented array of PMOS transistor current sources, which are capable of delivering a full-scale current up to 20 mA. High-speed differential current switches direct the current of each current source to either one of the output nodes, IOUT1 or IOUT2. The complementary output currents thus enable differential operation, canceling out common mode noise sources (on-chip and PCB noise), dc offsets, even order distortion components, and increases signal output power by a factor of two. Major advantages of the segmented architecture are minimum glitch energy , excellent DNL, and very good dynamic performance. The DAC’s high output impedance of >300 kΩ and fast switching result in excellent dynamic linearity (spurious free dynamic range SFDR).

The full-scale output current is set using an external resistor R

BIAS

in combination with an on-chip bandgap

voltage reference source (1.2 V) and control amplifier. The current I

BIAS

through resistor R

BIAS

is mirrored

internally to provide a full-scale output current equal to 32 times I

BIAS

. The full-scale current can be adjusted

from 20 mA down to 2 mA.

data interface and timing

The THS5671A comprises separate analog and digital supplies, i.e. A VDD and DVDD. The digital supply voltage can be set from 5.5 V down to 3 V , thus enabling flexible interfacing with external logic. The THS5671A provides two operating modes, as shown in Table 1. Mode 0 (mode pin connected to DGND) supports a straight binary input data word format, whereas mode 1 (mode pin connected to DV

) sets a twos complement input

configuration. Figure 29 shows the timing diagram. Internal edge-triggered flip-flops latch the input word on the rising edge

of the input clock. The THS5671A provides for minimum setup and hold times (> 1 ns), allowing for noncritical external interface timing. Conversion latency is one clock cycle for both modes. The clock duty cycle can be chosen arbitrarily under the timing constraints listed in the digital specifications table. However, a 50% duty cycle will give optimum dynamic performance. Figure 30 shows a schematic of the equivalent digital inputs of the THS5671A, valid for pins D13–D0, SLEEP, and CLK. The digital inputs are CMOS-compatible with logic thresholds of DV

/2 ±20%. Since the THS5671A is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the THS5671A, as well as its required min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feed-through and noise. Additionally , operating the THS5671A with reduced logic swings and a corresponding digital supply (DV

) will reduce data feed-through.

Note that the update rate is limited to 70 MSPS for a digital supply voltage DVDD of 3 V to 3.6 V.

Page 16

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

data interface and timing (continued)

CLK

D[13:0]

DAC

Output

(IOUT1 or

IOUT2)

w(LPH)

d(D)

0.1%

0.1% 50%

h(D)

Valid Data

su(D)

s(DAC)

1/f

CLK

r(IOUT)

90%

10%

50% 50% 50% 50%

Figure 29. Timing Diagram

Table 1. Input Interface Modes

MODE 0 MODE 1

FUNCTION/MODE

MODE PIN CONNECTED TO

DGND

MODE PIN CONNECTED TO

Input code format Binary Twos complement

External

Digital in

Internal Digital in

Figure 30. Digital Equivalent Input

Page 17

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

DAC transfer function

The THS5671A delivers complementary output currents IOUT1 and IOUT2. Output current IOUT1 equals the approximate full-scale output current when all input bits are set high in mode 0 (straight binary input), i.e. the binary input word has the decimal representation 16383. For mode 1, the MSB is inverted (twos complement input format). Full-scale output current will flow through terminal IOUT2 when all input bits are set low (mode 0, straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:

IOUT1+IOUTFS*

IOUT2

where IOUTFS is the full-scale output current. The output currents can be expressed as:

IOUT1+IOUTFS

CODE

16384

IOUT2+IOUTFS

(16383*CODE)

16384

where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive resistor loads R

LOAD

or a transformer with equivalent input load resistance R

LOAD

. This would translate into

single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:

VOUT1+IOUT1 R

LOAD

CODE

16384

IOUTFS

LOAD

VOUT2+IOUT2 R

LOAD

(16383–CODE)

16384

IOUTFS

LOAD

The differential output voltage VOUT

DIFF

can thus be expressed as:

VOUT

DIFF

VOUT1–VOUT2

(2CODE–16383)

16384

IOUTFS

LOAD

The latter equation shows that applying the differential output will result in doubling of the signal power delivered to the load. Since the output currents of IOUT1 and IOUT2 are complementary, they become additive when processed differentially. Care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would lead to increased signal distortion.

Page 18

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

reference operation

The THS5671A comprises a bandgap reference and control amplifier for biasing the full-scale output current. The full-scale output current is set by applying an external resistor R

BIAS

. The bias current I

BIAS

through resistor

BIAS

is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current

equals 32 times this bias current. The full-scale output current IOUTFS can thus be expressed as:

IOUTFS+32

BIAS

32 V

EXTIO

BIAS

where V

EXTIO

is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of 1.2 V . This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor C

EXT

of 0.1 µF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally be used for external reference operation. In that case, an external buffer with high impedance input should be applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be disabled and overridden by an external reference by connecting EXTLO to A VDD. Capacitor C

EXT

may

hence be omitted. Terminal EXTIO thus serves as either input or output node. The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor R

BIAS

or changing the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the full-scale output current range of 20 dB. The bandwidth of the internal control amplifier is defined by the internal 1 nF compensation capacitor at pin COMP1 and the external compensation capacitor C1. The relatively weak internal control amplifier may be overridden by an externally applied amplifier with sufficient drive for the internal 1 nF load, as shown in Figure 31. This provides the user with more flexibility and higher bandwidths, which are specifically attractive for gain control and multiplying DAC applications. Pin SLEEP should be connected to AGND or left disconnected when an external control amplifier is used.

1.2 V REF

REF AMP

1 nF

–

AVDD

AGND

EXTLO

EXTIO

BIASJ

IOUT1 or IOUT2

External

Control AMP

EXT Reference

Voltage

COMP1SLEEP

Current Source Array

EXT

Internal

Control AMP

THS4041

Figure 31. Bypassing the Internal Reference and Control Amplifier

Page 19

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

analog current outputs

Figure 32 shows a simplified schematic of the current source array output with corresponding switches. Differential PMOS switches direct the current of each individual PMOS current source to either the positive output node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5 pF.

Output nodes IOUT1 and IOUT2 have a negative compliance voltage of –1 V , determined by the CMOS process. Beyond this value, transistor breakdown may occur, resulting in reduced reliability of the THS5671A device. The positive output compliance depends on the full-scale output current IOUT

and positive supply voltage A VDD. The positive output compliance equals 1.25 V for AVDD = 5 V and IOUTFS = 20 mA. Exceeding the positive compliance voltage adversely affects distortion performance and integral nonlinearity . The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V (e.g. when applying a 50 Ω doubly terminated load for 20 mA full-scale output current). Applications requiring the THS5671A output (i.e., OUT1 and/or OUT2) to extend its output compliance should size R

LOAD

accordingly .

Current Source Array

IOUT1 IOUT2

LOAD

Current Sources

Switches

Figure 32. Equivalent Analog Current Output

Figure 33(a) shows the typical differential output configuration with two external matched resistor loads. The nominal resistor load of 50 Ω will give a differential output swing of 2 VPP when applying a 20 mA full-scale output current. The output impedance of the THS5671A depends slightly on the output voltage at nodes IOUT1 and IOUT2. Consequently , for optimum dc integral nonlinearity , the configuration of Figure 33(b) should be chosen. In this I–V configuration, terminal IOUT1 is kept at virtual ground by the inverting operational amplifier. The complementary output should be connected to ground to provide a dc current path for the current sources switched to IOUT2. Note that the INL/DNL specifications for the THS5671A are measured with IOUT1 maintained at virtual ground. The amplifier’s maximum output swing and the DAC’s full-scale output current determine the value of the feedback resistor R

. Capacitor CFB filters the steep edges of the THS5671A current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration, the op amp should operate on a dual supply voltage due to its positive and negative output swing. Node IOUT1 should be selected if a single-ended unipolar output is desirable.

Page 20

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

IOUT2

IOUT1

IOUT2

IOUT1

VOUT

100 Ω

–

–)

VOUT

–)

50 Ω

(a) (b)

50 Ω

THS4001 THS4011

Figure 33. Differential and Single-Ended Output Configuration

The THS5671A can be easily configured to drive a doubly terminated 50-Ω cable. Figure 34(a) shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent load resistance of 25 Ω. Node IOUT2 should be connected to ground or terminated with a resistor of 25 Ω. Differential-to-single conversion (e.g., for measurement purposes) can be performed using a properly selected RF transformer, as shown in Figure 34(b). This configuration provides maximum rejection of common-mode noise sources and even order distortion components, thereby doubling the power to the output. The center tap on the primary side of the transformer is connected to AGND, enabling a dc current flow for both IOUT1 and IOUT2. Note that the ac performance of the THS5671A is optimum and specified using this differential transformer coupled output, limiting the voltage swing at IOUT1 and IOUT2 to ±0.5 V.

IOUT2

IOUT1

VOUT

IOUT2

IOUT1

VOUT

50 Ω

100 Ω

(a) (b)

25 Ω

50 Ω

1:1

Figure 34. Driving a Doubly Terminated 50-Ω Cable

Page 21

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

sleep mode

The THS5671A features a power-down mode that turns off the output current and reduces the supply current to less than 5 mA over the analog supply range of 4.5 V to 5.5 V and temperature range. The power-down mode is activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal pulldown circuit at node SLEEP ensures that the THS5671A is enabled if the input is left disconnected. Power-up and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal capacitor value of 0.1 µF power down takes less than 5 µs, and approximately 3 ms to power backup. The SLEEP mode should not be used when an external control amplifier is used, as shown in Figure 31.

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

offset error

Offset error is defined as the deviation of the output current from the ideal of zero at a digital input value of 0.

gain error

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (S/N+D or SINAD)

S/N+D or SINAD is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

total harmonic distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels.

output compliance range

The maximum and minimum allowable voltage of the output of the DAC, beyond which either saturation of the output stage or breakdown may occur.

settling time

The time required for the output to settle within a specified error band.

glitch energy

The time integral of the analog value of the glitch transient.

Page 22

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

definitions of specifications and terminology (continued)

offset drift

The change in offset error versus temperature from the ambient temperature (T

= 25°C) in ppm of full-scale

range per °C.

gain drift

The change in gain error versus temperature from the ambient temperature (TA = 25°C) in ppm of full-scale range per °C.

reference voltage drift

The change in reference voltage error versus temperature from the ambient temperature (T

= 25°C) in ppm

of full-scale range per °C.

THS5671A evaluation board

An evaluation module (EVM) board for the THS5671A digital-to-analog converter is available for evaluation. This board allows the user the flexibility to operate the THS5671A in various configurations. Possible output configurations include transformer coupled, resistor terminated, and inverting/noninverting amplifier outputs. The digital inputs are designed to interface with the TMS320 C5000 or C6000 family of DSPs or to be driven directly from various pattern generators with the onboard option to add a resistor network for proper load termination.

See the

THS56x1 Evaluation Module User’s Guide

for more details (SLAU032).

Page 23

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999



POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 23

–5VA

D48D57D66D75D84D9

D10

D111CLK

MODE

DVDD

DGND

AGND

AVDD

EXTLO16EXTIO17BIASJ

COMP119COMP2

IOUT122IOUT2

SLEEP

D113D0

THS5671A

FB3

C12

0.1 µF

C18

4.7 µF

+5VA

R24

49.9

R29

49.9

DAC[2..15]

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

DAC8

DAC9

DAC10

DAC11

DAC12

DAC13

DAC14

DAC15

DSP[2..15]

R4A

R10A

R10B

R10C

R10D

R10E

R10F

R10G

R4B

R10H

R11A

R11B

R11C

R11D

R11E

R11F

R11G

R11H

R5G

R5F

R5E

R5H

R4E

R4C

R4D

R4F

R4G

R4H

R5A

R5B

R5C

R5D

T1–1T–KK81

R25

TDB

~OE

R20

10 K

R18

49.9

DSP2

DSP3

DSP4

DVDCC

DSP5

+5VA

DSP6

DSP7

DSP8

DSP9

DSP10

DSP11

DSP12

DSP13

DSP14

CLKOUT

DSP15

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

C17

0.1 µF

R14

5 K

C13

0.1 µF

C16

0.1 µF

0 Ω

C32

C25

CLKOUT

DSP0

DSP1

~OE

C11

0.1 µF

DVDCC

10K

10 K

DVDCC

DSP0

DSP1

DSP2

DSP3

DSP4

DSP5

DSP6

DSP7

DSP8

DSP9

DSP10

DSP11

DSP12

DSP13

DSP14

DSP15

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

DAC8

DAC9

DAC10

DAC11

DAC12

DAC13

DAC14

DAC15

DIR

A12A23A34A45A56A67A78A8

B118B217B316B415B514B613B712B8

VCC

GND

SN74LVT245B

DIR

A12A23A34A45A56A67A78A8

B118B217B316B415B514B613B712B8

VCC

GND

SN74LVT245B

R23

100

R1233R933R7

U6A

SN74ALVC08

SN74HC1G32

0.1 µF

10 µF

1 µF

0.1 µF

0.01 µF

C23

0.1 µF

C24

10 µF

C31

1 µF

C30

0.1 µF

C29

0.01 µF

FB4

DVDCC

+5VA

0.1 µF

C10

0.1 µF

DVDCC

MiscellaniousDigital Bypass Caps

R16

3.0 K

1.5 K

THS3001

R30

750

R28

750

R26

750

R27

750

R22

ABCDE

I/OSTROBE

PDAC

SN74AHC1G00

DVDCC

0.1 µF

C15

10 µF

C22

1 µF

C21

0.1 µF 0.01 µF

FB2

–5VA

123

+5VA

AD1580BRT

R15

2.94 K

R19

C19

4.7 µF

C14

0.01 µF

123456789

101112

U6B

U6C

LT1004D

ALTERNATECONFIGURATION

C35

4.7 µF

C34

0.1 µF

C33

0.01 µF

+5VA

C28

4.7 µF

C27

0.1 µF

C26

0.01 µF

–5VA

U6D

R13R8R17

R21

0 Ω

4.7 µH

0 Ω

Figure 35. Schematic

APPLICATION INFORMATION

D12

D13

FB1

C20

Page 24

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Figure 36. Board Layout, Layer 1

Figure 37. Board Layout, Layer 2

Page 25

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Figure 38. Board Layout, Layer 3

Figure 39. Board Layout, Layer 4

Page 26

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Figure 40. Board Layout, Layer 5

Table 2. Bill of Materials

QTY REF. DES PART NUMBER DESCRIPTION MFG.

3 C1, C22, C31 1206ZC105KAT2A Ceranucm 1 µF, 10 V, X7R, 10% AVX 4 C18, C19, C28, C35 ECST OJY475 6.3 V , 4.7 µF, tantalum Panasonic 3 C15, C24, C4 ECSTOJY106 6.3 V, 10 µF, tantalum Panasonic 0 C25, C32 Ceramic, not installed, 50 V , X7R, 10% 6 C14, C2, C20, C26, C29, C33 12065C103KAT2A Ceramic, 0.01 µF, 50 V, X7R, 10% AVX

17 C10, C11, C12, C13, C16,

C17, C21, C23, C27, C3, C30, C34, C5, C6, C7, C8, C9

12065C104KAT2A Ceramic, 0.1 µF, 50 V, X7R, 10% AVX

2 D1, D2 AND/AND5GA or equivalent GREEN LED, 1206 size SM chip LED 4 FB1, FB2, FB3, FB4 27-43-037447 Fair-Rite SM beads #27-037447 FairRite 1 J1 TSW-1 17-07-L-D or equivalent 34-Pin header for IDC Samtec 1 J2 KRMZ2 or equivalent 2 Terminal screw connector ,

2TERM_CON

Lumberg

1 J3 TSW-1 12-07-L-S or equivalent Single row 12-pin header Samtec 1 J4 KRMZ3 or equivalent 3 Terminal screw connector Lumberg 3 J5, J6, J7 142-0701-206 or equivalent PCB Mount SMA jack, SMA_PCB_MT Johnson Components 0 J8, J9 142-0701-206 or equivalent PCB Mount SMA jack, not installed Johnson Components 3 L1, L2, L3 DO1608C-472 DO1608C-series, DS1608C-472 Coil Craft 1 R1 1206 1206 Chip resistor, 1.5K, 1/4 W, 1% 4 R10, R11, R4, R5 CTS/CTS766-163-(R)330-G-TR 8 Element isolated resistor pack, 33 Ω

Page 27

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Table 2. Bill of Materials (Continued)

QTY REF. DES PART NUMBER DESCRIPTION MFG.

4 R12, R19, R7, R9 1206 1206 Chip resistor , 33 Ω, 1/4 W, 1% 5 R13, R17. R2, R21, R8 1206 1206 Chip resistor, 0 Ω, 1/4 W, 1% 1 R14 3214W-1-502 E or equivalent 4 mm SM Pot, 5K Bourns 1 R15 1206 1206 Chip resistor, 2.94K, 1/4 W, 1% 1 R16 1206 1206 Chip resistor, 3K, 1/4 W, 1% 3 R18, R24, R29 1206 1206 Chip resistor, 49.94K, 1/4 W , 1% 3 R20, R3, R6 1206 1206 Chip resistor, 10K, 1/4 W, 1% 1 R22 1206 1206 Chip resistor, 10K, 1/4 W, 1% 1 R23 1206 1206 Chip resistor, 100K, 1/4 W, 1% 1 R25 1206 1206 Chip resistor, TBD, 1/4 W, 1% 4 R26, R27, R28, R30 1206 1206 Chip resistor, 750K, 1/4 W, 1% 1 T1 T1-1T-KK81 RF Transformer, T1-1T-KK81 MiniCircuits 2 U1, U2 SN74LVT245BDW Octal bus transceiver, 3-state,

SN74LVT245B

1 U3 SN74AHCT1G00DBVR/

SN74AHC1G00DBVR

Single gate NAND, SN74AHC1G00 TI

1 U4 SN74AHCT1G32DBVR/

SN74AHCC1G32DBVR

Single 2 input positive or gate, SN74AHC1G32

THS5641 THS5641IDW DAC, 3–5.5 V , 8 Bit, 100 MSPS TI THS5651A THS5651AIDW DAC, 3–5.5 V, 10 Bit, 125 MSPS TI THS5661A THS5661AIDW DAC, 3–5.5 V, 12 Bit, 125 MSPS TI

THS5671A THS5671AIDW DAC, 3–5.5 V, 14 Bit, 125 MSPS TI 1 SN74ALVC08 SN74ALVC08D Quad AND gate TI 1 LT1004D LT1004CD-1-2/LT1004ID-1-2 Precision 1.2 V reference TI 0 NOT INSTALLED AD1580BRT Precision voltage reference, not

installed 1 THS3001 THS3001CD/THS2001ID THS3001 high-speed op amp TI 4 W2 TSW-102-07-L-S or equivalent 2 position jumper_.1’’ spacing, W2 Samtec 3 W3 TSW-102-07-L-S or equivalent 3 position jumper_.1’’ spacing, W3 Samtec 2 2X3_JUMPER TSW-102-07-L-S or equivalent 6-Pin header dual row, 0.025×0.1,

2X3_JUMPER

Samtec

Page 28

THS5671A 14-BIT, 125 MSPS, CommsDAC DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

4040000/C 07/96

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.293 (7,45)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

(17,78)

0.700

(18,03)

0.710

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MS-013

Page 29

THS5671A

14-BIT, 125 MSPS, CommsDAC

DIGITAL-TO-ANALOG CONVERTER

SLAS201 – DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

0,10

0,25

0,50

0,75

0,15 NOM

Gage Plane

9,80

9,60

7,90

7,70

2016

6,60

6,40

4040064/F 01/97

0,30

6,60 6,20

0,19

4,30

4,50

0,15

1,20 MAX

5,10

4,90

3,10

2,90

A MAX

A MIN

DIM

PINS **

0,05

4,90

5,10

Seating Plane

0°–8°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

Page 30

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet THS5671EVM, THS5671AIPWR, THS5671AIPW, THS5671AIDWR, THS5671AIDW Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual