Datasheet THS1408CPFB, THS1403IPFB, THS1403QPFB, THS1403CPFB, THS1401QPFB Datasheet (Texas Instruments)

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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features

D

14-Bit Resolution

D

1, 3, and 8 MSPS Speed Grades Available

D

Differential Nonlinearity (DNL) ±0.6 LSB Typ

D

Integral Nonlinearity (INL) ±1.5 LSB Typ

D

Internal Reference

D

Differential Inputs

D

Programmable Gain Amplifier

D

µP Compatible Parallel Interface

D

Timing Compatible With TMS320C6000 DSP

D

3.3-V Single Supply

D

Power-Down Mode

D

Monolithic CMOS Design

applications

D

xDSL Front Ends

D

Communication

D

Industrial Control

D

Instrumentation

14 15

WR
OE
DGND
DGND
CLK
DV

DD

DV

DD

D0
D1
D2
DV

DD

DGND

36
35
34
33
32
31
30
29
28
27
26
25

16

1
2
3
4
5
6
7
8
9
10
11
12

IN–

AV

DD

VBG

CML
REF+
REF–

AGND
AGND
DGND

OV
D13
D12

17 18 19 20

A0A1NC

NC

47 46 45 44 4348 42

IN+AVAGND

AGND

AGND

D5D4D3

DGND

D9D8D7

D6

40 39 3841

21

22 23 24

37

13

CS

D11

D10

PFB PACKAGE

(TOP VIEW)

DD

AV

DD

DV

DD

DV

DD

DV

DD

NC – No internal connection

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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description

The THS1401, THS1403, and THS1408 are 14-bit, 1/3/8 MSPS, single supply analog-to-digital converters with
an internal reference, differential inputs, programmable input gain, and an on-chip sample and hold amplifier .

Implemented with a CMOS process, the device has outstanding price/performance and power/speed ratios.
The THS1401, THS1403, and THS1408 are designed for use with 3.3-V systems, and with a high-speed µP
compatible parallel interface, making them the first choice for solutions based on high-performance DSPs like
the TI TMS320C6000 series.

The THS1401, THS1403, and THS1408 are available in a TQFP-48 package in standard commercial and
industrial temperature ranges.

functional block diagram

PGA

0..7 dB

REF

14-Bit

ADC

Buffer

14 15

CONTROL

LOGIC

REF+

REF–

IN+

IN–

D[13:0] + OV bit

A[1:0]

6

CLK

1.5 V
BG

VBG

CS
WR
OE

AVAILABLE OPTIONS

PACKAGED DEVICE

T

A

TQFP
(PFB)

0°C to 70°C

THS1401CPFB,
THS1403CPFB,
THS1408CPFB,

–40°C to 85°C

THS1401IPFB,
THS1403IPFB,
THS1408IPFB

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

A[1:0] 40, 41 I Address input
AGND 7,8, 44,

45, 46

P Analog ground

AV

DD

2, 43, 47 P Analog power supply
CLK 32 I Clock input
CML 4 Reference midpoint. This pin requires a 0.1-µF capacitor to AGND.
CS 37 I Chip select input. Active low
DGND 9, 15, 25,

33, 34

P Digital ground

DV

DD

14, 20, 26,

30, 31, 42

P Digital power supply

D[13:0] 11, 12, 13,

16, 17, 18,

19,21, 22,

23, 24, 27,

28, 29

I/O Data inputs/outputs

NC 38, 39 No connection, do not use. Reserved
IN+ 48 I Positive differential analog input
IN– 1 I Negative dif ferential analog input
OE 35 I Output enable. Active low
OV 10 O Out of range output
REF+ 5 O Positive reference output. This pin requires a 0.1-µF capacitor to AGND.
REF– 6 O Negative reference output. This pin requires a 0.1-µF capacitor to AGND.
VBG 3 I Reference input. This pin requires a 1-µF capacitor to AGND.
WR 36 I Write signal. Active low

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, (AVDD to AGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage, (DVDD to DGND) 4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range, VBG – 0.3 V to AV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range – 0.3 V to AV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to DV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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recommended operating conditions

PARAMETER MIN NOM MAX UNIT

Supply voltage, AVDD, DV

DD

3 3.3 3.6 V

High level digital input, V

IH

2 3.3 V

Low level digital input, V

IL

0

0.8

V

Load capacitance, C

L

5 15 pF

THS1401 0.1 1 1 MHz

Clock frequency, f

CLK

THS1403 0.1 3 3 MHz
THS1408 0.1 8 8 MHz

Clock duty cycle 40% 50% 60%

p

p

C suffix 0 25 70 °C

Operating free-air temperature

I suffix –40 25 85 °C

electrical characteristics over recommended operating conditions

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Power Supply

I

DDA

Analog supply current 81 90 mA

I

DDD

Digital supply current 5 10 mA
Power 270 360 mW
Power down current 20 µA

DC Characteristics

Resolution 14 Bits

DNL Differential nonlinearity ±0.6 ±1 LSB

THS1401 ±1.5 ±2.5 LSB

INL Integral nonlinearity

THS1403

Best fit

±1.5 ±2.5 LSB

THS1408 ±3 ±5 LSB
Offset error IN+ = IN–, PGA = 0 dB 0.3 %FSR
Gain error PGA = 0 dB 1 %FSR

AC Characteristics

ENOB Effective number of bits 11.2 1 1.5 Bits

THS1401/3/8 fi = 100 kHz –81

THD Total harmonic distortion

THS1403/8

fi = 1 MHz –78

dB
THS1408 fi = 4 MHz –77
THS1401/3/8 fi = 100 kHz 72

SNR Signal-to-noise ratio

THS1403/8

fi = 1 MHz 70 72

dB
THS1408 fi = 4 MHz 71
THS1401/3/8 fi = 100 kHz 70

SINAD Signal-to-noise ratio + distortion

THS1403/8

fi = 1 MHz 69 70

dB
THS1408 fi = 4 MHz 70
THS1401/3/8 fi = 100 kHz 80

SFDR Spurious free dynamic range

THS1403/8

fi = 1 MHz 73 80

dB
THS1408 fi = 4 MHz 80

Analog input bandwidth 140 MHz

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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electrical characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Reference Voltage

Bandgap voltage, internal mode 1.425 1.5 1.575 V

VBG

Input impedance 40 kΩ
Positive reference voltage, REF+ 2.5 V
Negative reference voltage, REF– 0.5 V
Reference difference, ∆REF, REF+ – REF– 2 V
Accuracy, internal reference 5%
T emperature coef ficient 40 ppm/°C
Voltage coefficient 200 ppm/V

Analog Inputs

Positive analog input, IN+ 0 AV

DD

V

Negative analog input, IN– 0 AV

DD

V

Analog input voltage difference ∆Ain = IN+ – IN–, V

ref

= REF+ – REF– –V

ref

V

ref

V
Input impedance 25 kΩ
PGA range 0 7 dB
PGA step size 1 dB
PGA gain error ±0.25 dB

Digital Inputs

V

IH

High-level digital input 2 V

V

IL

Low-level digital input 0.8 V
Input capacitance 5 pF
Input current ±1 µA

Digital Outputs

V

OH

High-level digital output IOH = 50 µA 2.6 V

V

OL

Low-level digital output IOL = 50 µA 0.4 V

I

OZ

Output current, high impedance ±10 µA

Clock Timing (CS low)

THS1401 0.1 1 1 MHz

f

CLK

Clock frequency

THS1403

0.1 3 3 MHz

THS1408 0.1 8 8 MHz

t

d

Output delay time 25 ns
Latency 9.5 Cycles

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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PARAMETER MEASUREMENT INFORMATION

sample timing

The THS1401/3/8 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results
appear on the digital output 9.5 clock cycles after the input signal was sampled.

S9

S10

S11

S12

CLK

Data

Out

Analog

Input

C1 C2

C3

t

w(CLK)

t

w(CLK)

t

d

Figure 1. Sample Timing

The parallel interface of the THS1401/3/8 ADC features 3-state buffers making it possible to directly connect
it to a data bus. The output buffers are enabled by driving the OE input low.

Besides the sample results, it is also possible to read back the values of the control register, the PGA register,
and the control register. Which register is read is determined by the address inputs A[1,0]. The ADC results are
available at address 0.

The timing of the control signals is described in the following sections.

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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PARAMETER MEASUREMENT INFORMATION

read timing (15-pF load)

PARAMETER MIN TYP MAX UNIT

t

su(OE–ACS)

Address and chip select setup time 4 ns

t

en

Output enable 15 ns

t

dis

Output disable

10

ns

t

h(A)

Address hold time 1 15 ns

t

h(CS)

Chip select hold time 0 ns

NOTE: All timing parameters refer to a 50% level.

DATA

ADDRESS

CS

OE

D[13:0]

O V

A[1:0]

X X

t

su(OE–ACS)

t

en

t

h(CS)

t

dis

t

h(A)

Figure 2. Read Timing

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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PARAMETER MEASUREMENT INFORMATION

write timing (15-pF load)

PARAMETER MIN TYP MAX UNIT

t

su(WE–CS)

Chip select setup time 4 ns

t

su(DA)

Data and address setup time 29 ns

t

h(DA)

Data and address hold time 0 ns

t

h(CS)

Chip select hold time 0 ns

t

wH(WE)

Write pulse duration high 15 ns

NOTE: All timing parameters refer to a 50% level.

DATA

ADDRESS

CS

WE

D[13:0]

A

X X

X

X

t

su(WE–CS)

t

su(DA)

t

h(CS)

t

h(DA)

Figure 3. Write Timing

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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TYPICAL CHARACTERISTICS

268

270

272

274

276

278

280

282

284

0.1 1 10

Power – mW

f – Frequency – MHz

POWER

vs

FREQUENCY

Figure 4

0

10

20

30

40

50

60

70

80

90

0 50 100 150 200 250 300

– Supply Current – mA

t – Time – ns

SUPPLY CURRENT

vs

TIME

I

CC

Figure 5

–100

–140

0 100 200 300

Output – dB

–40

–20

f – Frequency – kHz

FAST FOURIER TRANSFORM

0

400 500

–60
–80

–120

fs = 1 MSPS,
fI = 100 kHz,
–1 dB

Figure 6

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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TYPICAL CHARACTERISTICS

–100

–140

0.1 0.4 0.7 1

Output – dB

–40

–20

f – Frequency – MHz

FAST FOURIER TRANSFORM

0

1.3

–60
–80

–120

fs = 3 MSPS,
fI = 1 MHz,
–1 dB

Figure 7

–60

–140

0.1 0.4 0.7 1 1.6 1.9 2.5

Output – dB

–40

–20

f – Frequency – MHz

FAST FOURIER TRANSFORM

0

2.8 3.1 3.7 4

–80
–100
–120

1.3

2.2

3.4

fs = 8 MSPS,
fI = 1 MHz,
–1 dB

Figure 8

–0.5

–2

0 2048 4096 6144 8192 10240

INL – Integral Nonlinearity – LSB

1

1.5

Samples

INTEGRAL NONLINEARITY

2

12288 14336 16384

0.5
0

–1

–1.5

fs = 1 MSPS

Figure 9

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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TYPICAL CHARACTERISTICS

–0.5

–2

0 2048 4096 6144 8192 10240

INL – Integral Nonlinearity – LSB

1

1.5

Samples

INTEGRAL NONLINEARITY

2

12288 14336 16384

0.5
0

–1

–1.5

fs = 3 MSPS

Figure 10

–2

–4

2

3

4

1
0

–1

–3

0 2048 4096 6144 8192 10240

INL – Integral Nonlinearity – LSB

Samples

INTEGRAL NONLINEARITY

12288 14336 16384

fs = 8 MSPS

Figure 11

–0.2

–1

0 2048 4096 6144 8192 10240

DNL – Differential Nonlinearity – LSB

0.6

0.8

Samples

DIFFERENTIAL NONLINEARITY

1

12288 14336 16384

0.4

0.2

0

–0.4
–0.6
–0.8

fs = 1 MSPS

Figure 12

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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TYPICAL CHARACTERISTICS

–0.2

–1

0 2048 4096 6144 8192 10240

DNL – Differential Nonlinearity – LSB

0.6

0.8

Samples

DIFFERENTIAL NONLINEARITY

1

12288 14336 16384

0.4

0.2
0

–0.4
–0.6

–0.8

fs = 3 MSPS

Figure 13

–0.2

–1

0 2048 4096 6144 8192 10240

DNL – Differential Nonlinearity – LSB

0.6

0.8

Samples

DIFFERENTIAL NONLINEARITY

1

12288 14336 16384

0.4

0.2
0

–0.4
–0.6

–0.8

fs = 8 MSPS

Figure 14

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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TYPICAL CHARACTERISTICS

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

10

100 1000

1500

THD – Total Harmonic Distortion – dB

f – Frequency – Hz

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

fs = 3 MSPS,
fI at –1 dB

Figure 15

–90

–88

–86

–84

–82

–80

–78

–76

–74

–72

–70

10 100

1000

4000

THD – Total Harmonic Distortion – dB

f – Frequency – Hz

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

fs = 8 MSPS,
fI at –1 dB

Figure 16

60

62

64

66

68

70

72

74

76

78

80

10

100

1000

1500

SNR – Signal-to-Noise Ratio – dB

f – Frequency – Hz

SIGNAL-TO-NOISE RATIO

vs

FREQUENCY

fs = 3 MSPS,
fI at –1 dB

Figure 17

60

62

64

66

68

70

72

74

76

78

80

10

100

1000

4000

SNR – Signal-to-Noise Ratio – dB

f – Frequency – Hz

SIGNAL-TO-NOISE RATIO

vs

FREQUENCY

fs = 8 MSPS,
fI at –1 dB

Figure 18

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

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PRINCIPLES OF OPERATION

registers

The device contains several registers. The A register is selected by the values of bits A1 and A0:

A1 A0 Register

0 0 Conversion result
0 1 PGA
1 0 Offset
1 1 Control

T ables 1 and 2 describe how to read the conversion results and how to configure the data converter . The default
values (were applicable) show the state after a power-on reset.

Table 1. Conversion Result Register, Address 0, Read

BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Function MSB ... … … … … … … … … … … … LSB

The output can be configured for two’s complement or straight binary format (see D11/control register).
The output code is given by:

2s complement: Straight binary:
–8192 at ∆IN = –∆REF 0 at ∆IN = –∆REF
0 at ∆IN = 0 8192 at ∆IN = 0
8191 ∆IN = –∆REF – 1 LSB 16383 at ∆IN = –∆REF – 1 LSB

1LSB

+

2DREF

16384

Table 2. PGA Gain Register, Address 1, Read/Write

BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X X X X X X X X X X G2 G1 G0

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0

The PGA gain is determined by writing to G2–0.
Gain (dB) = 1dB × G2–0. max = 7dB. The range of G2–0 is 0 to 7.

Table 3. Offset Register, Address 2, Read/Write

BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X X X X X MSB … … … … … … LSB

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0

The offset correction range is from –128 to 127 LSB. This value is added to the conversion results from the ADC.

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

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PRINCIPLES OF OPERATION

Table 4. Control Register, Address 3, Read

BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES

Table 5. Control Register, Address 3, Write

BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWD: Power down 0 = normal operation 1 = power down
REF: Reference select 0 = internal reference 1 = external reference
FOR: Output format 0 = straight binary 1 = 2s complement
TM2–0: Test mode 000 = normal operation

001 = both inputs = REF–
010 = IN+ at V

ref

/2, IN– at REF–
011 = IN+ at REF+, IN– at REF–
100 = normal operation
101 = both inputs = REF+
110 = IN+ at REF–, IN– at V

ref

/2

111 = IN+ at REF–, IN– at REF+

OF: Offset correction 0 = enable 1 = disable
RES Reserved Must be set to 0.

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

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APPLICATION INFORMATION

driving the analog input

The THS1401/3/8 ADCs have a fully differential input. A differential input is advantageous with respect to SNR,
SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended
input.

There are three basic input configurations:

D

Fully differential

D

Transformer coupled single-ended to differential

D

Single-ended

fully differential configuration

In this configuration, the ADC converts the difference (∆IN) of the two input signals on IN+ and IN–.

100 pF

IN+

IN–

THS1401/3/8

22 Ω

100 pF

22 Ω

Figure 19. Differential Input

The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve
as first order low pass filters to attenuate out of band noise.

The input range on both inputs is 0 V to A VDD. The full-scale value is determined by the voltage reference. The
positive full-scale output is reached, if ∆IN equals ∆REF , the negative full-scale output is reached, if ∆IN equals
–∆REF.

∆IN [V] OUTPUT

–∆REF – full scale

0 0

∆REF + full scale

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

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APPLICATION INFORMATION

transformer coupled single-ended to differential configuration

If the application requires the best SNR, SFDR, and THD performance, the input should be transformer coupled.
The signal amplitude on both inputs of the ADC is one half as high as in a single-ended configuration thus

increasing the ADC ac performance.

100 pF

IN+

IN–

THS1401/3/8

CML

R

100 pF

22 Ω

22 Ω

+

1 µF 0.1 µF

Figure 20. Transformer Coupled

IN [V

PEAK

] OUTPUT [

PEAK

]

–∆REF – full scale

†

0 0

∆REF + full scale

†

†

n = 1 (winding ratio)

The resistor R of the transformer coupled input configuration must be set to match the signal source impedance
R = n2 Rs, where Rs is the source impedance and n is the transformer winding ratio.

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

single-ended configuration

In this configuration, the input signal is level shifted by ∆REF/2.

IN+

IN–

THS1401/3/8

REF+

REF–

+

–

10 kΩ

100 pF

100 pF

10 kΩ

22 Ω

10 kΩ 10 kΩ

10 kΩ + 10 kΩ

Figure 21. Single-Ended With Level Shift

The following table shows the input voltages for negative full-scale output, zero output, and positive full-scale
output:

∆IN+ [V] OUTPUT

–∆REF – full scale

0 0

∆REF + full scale

Note that the resistors of the op-amp and the op-amp all introduce gain and offset errors. Those errors can be
trimmed by varying the values of the resistors.

Because of the added offset, the op-amp does not necessarily operate in the best region of its transfer curve
(best linearity around zero) and therefore may introduce unacceptable distortion. For ac signals, an alternative
is described in the following section.

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

AC-coupled single-ended configuration

If the application does not require the signal bandwidth to include dc, the level shift shown in Figure 4 is not
necessary.

IN+

IN–

THS1401/3/8

REF+

REF–

+

–

10 nF

10 kΩ
10 kΩ

10 kΩ
10 kΩ

100 pF

100 pF

22 Ω

10 kΩ 10 kΩ

Figure 22. Single-Ended With Level Shift

Because the signal swing on the op-amp is centered around ground, it is more likely that the signal stays within
the linear region of the op-amp transfer function, thus increasing the overall ac performance.

IN [V

PEAK

] OUTPUT [

PEAK

]

–∆REF – full scale

0 0

∆REF + full scale

Compared to the transformer-coupled configuration, the swing on IN– is twice as big, which can decrease the
ac performance (SNR, SFD, and THD).

THS1401, THS1403, THS1408
14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

internal/external reference operation

The THS1401/3/8 ADC can either be operated using the built-in band gap reference or using an external
precision reference in case very high dc accuracy is needed.

The REF+ and REF+ outputs are given by:

REF

)+

VBG

ǒ

1

)

2
3

Ǔ

and REF–+VBGǒ1–

2
3

Ǔ

If the built-in reference is used, VBG equals 1.5 V which results in REF+ = 2.5 V, REF– = 0.5 V and ∆REF =
2V.

The internal reference can be disabled by writing 1 to D12 (REF) in the control register (address 3). The band
gap reference is then disconnected and can be substituted by a voltage on the VBG pin.

programmable gain amplifier

The on-chip programmable gain amplifier (PGA) has eight gain settings. The gain can be changed by writing
to the PGA gain register (address 1). The range is 0 to 7dB in steps of one dB.

out of range indication

The OV output of the ADC indicates an out of range condition. Every time the difference on the analog inputs
exceeds the differential reference, this signal is asserted. This signal is updated the same way as the digital data
outputs and therefore subject to the same pipeline delay.

offset compensation

With the offset register it is possible to automatically compensate system offset errors, including errors caused
by additional signal conditioning circuitry . If the offset compensation is enabled (D7 (OFF) in the control register),
the value in the offset register (address 2) is automatically subtracted from the output of the ADC.

In order to set the correct value of the offset compensation register , the ADC result when the input signal is 0
must be read by the host processor and written to the offset register (address 2).

test modes

The ADC core operation can be tested by selecting one of the available test modes (see control register
description). The test modes apply various voltages to the differential input depending on the setting in the
control register.

digital I/O

The digital inputs and outputs of the THS1401/3/8 ADC are 3-V CMOS compatible. In order to avoid current
feed back errors, the capacitive load on the digital outputs should be as low as possible (50 pF max). Series
resistors (100 Ω) on the digital outputs can improve the performance by limiting the current during output
transitions.

The parallel interface of the THS1401/3/8 ADC features 3-state buffers, making it possible to directly connect
it to a data bus. The output buffers are enabled by driving the OE

input low.

Refer to the read and write timing diagrams in the parameter measurement information section for information
on read and write access.

THS1401, THS1403, THS1408

14-BIT, 1/3/8 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS

WITH INTERNAL REFERENCE AND PGA

SLAS248 – DECEMBER 1999

21

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

4073176/B 10/96

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,17

0,27

24

25

13

12

SQ

36

37

7,20
6,80

48

1

5,50 TYP

SQ

8,80

9,20

1,05
0,95

1,20 MAX

0,08

0,50

M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026

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Copyright  1999, Texas Instruments Incorporated