Datasheet TH8060JDF Datasheet (MELEXIS)

Features and Benefits

 LIN-Bus Transceiver:

 PNP-open emitter driver with slew rate control and current limita-

tion

 BUS input voltage -24V ... 30V (independently of V

SUP

)

 Possibility of BUS wake up  Baud rate up to 20 kBaud

 Operating v oltage V

SUP

= 5.5 ... 18 V

 Very low standby current consumption < 110 µA in normal mode

(< 50 µA in sleep mode)

 Linear low drop voltage regulator:

 Output voltage 5V± 1%  Output current max. 100mA  Output current limitation

 Overtemperature shutdown

 Configurable reset time (15ms/100ms) and reset threshold voltage (3.15V / 4.65V)

 Low voltage detection at VSUP

 Wake-up by LIN BUS traffic and start-up capable independent of EN voltage level

 Universal comparator with an input voltage range –24V … 30V

and digital output

 Load dump protected (40V)

Ordering Information

Part No. Temperature Rang e Package

TH8060 JDF -40ºC...125ºC SOIC16, 300mil

General Descri ption

The RELIN TH8060 consists a low drop voltage regulator

5V/100mA and a LIN Bus transceiver. The LIN-

transceiver is suitable for LIN-Bus systems conform to

“LIN-Protocol Specification” Rev.1.1. from 04/17/2000.

The combination of voltage regulator and bus transceiver

in combination with the monitoring functions make it

TH8060

1

EN SENSE

GND

VTR

GND

RESET

BUS

SO

SI

n.c.

RxD

TxD

16

15

14

13

12

11

10

98

7

6

5

4

2

3

VSUP VCC

SOIC16

TH8060

LIN Bus Transceiver with integrated Voltage Regulator

Pin Diagram

www.melexis.com

Page 1 Datasheet Rev 1.1 March 2001

possible to develop simple, but powerful and cheap

slave nodes in LIN Bus systems.

The wide output current area and the configurable reset

time and reset voltage works together with many differ-

ent microcontrollers.

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 2 Datasheet Rev 1.1 March 2001

Functional Diagram

Wake-up

pnp Control



slew rate



foldback

OSC

Over Temp

V

THSI _H

V

THSI _L

V

thH

V

thL

+5V

7.8V

6.8V

+5V

VSUP

EN

VTR

BUS

SI

SO

RxD

TxD

RESET

SENSE

VCC

30k

MR TSHD

Power Supply

+5V

Reset-Logic

VTR-Logic

Figure 1 - Block Diagram

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 3 Datasheet Rev 1.1 March 2001

Functional Description

TxD

BUS

V

BAT

V

SUP

0.8 V

BAT

V

Diode

recessive

0.2 V

BAT

dominant

Figure 3 - Transmit Mode Pulse Diagram

The TH8060 consists a voltage regulator 5V/100mA and a LIN Bus transceiver, which is a bi-directional bus interface device for data transfer between LIN-Bus and the LIN protocol controller.

Also integrated into the transceiver are a voltage and time controlled reset management, power down, wake up function and a universal comparator for extended applications.

LIN-BUS Transceiver

The TH8060 is a bi-directional bus interface device for data transfer between LIN-Bus and the LIN protocol controller. The transceiver consists a pnp-driver (1.2V@40mA) with slew rate control and fold-back characteristic and con-

sists as well in the receiver a high voltage comparator followed by a debouncing unit. The BUS pin has an integrated 30k pull up resistor with a diode, which prevent the reverse current of VBUS during differential voltage between VSUP and BUS (V

BUS>VSUP

).

Transmit Mode

During the transmission the data at the pin TxD will be

transferred to the pin BUS. To minimize the electromag-

netic emission of the bus line, the TH8060 has an integrated sl ew rate control.

pnpControl



slew rate



I

B



foldback

+5V

BUS

RxD

TxD

t

debBUS

t

debW AKE

BIAS

to wake up logic

V

thH

V

thL

ESD

MR

TSHD

VSUP

30k

Figure 2 - Block Diagram LIN Bus Transceiver

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 4 Datasheet Rev 1.1 March 2001

BUS

RxD

t

debL

t < t

debL

t < t

debH

t

debH

Figure 4 - Block Diagram LIN Bus Transceiver

VS

VCC

t

Res

V

RESEIN

t

rr

V

RES1/2

RESET

Figure 5 - Init ia liz a tion

Receive Mode

The data at the pin BUS will be transferred to the pin

RxD. Short spikes on the bus signal are suppressed by

the implemented debouncing circuit.

Linear Regulator and Controlling Functions

Regulator

The TH8060 has an integrated linear regulator with an output voltage of 5V ±2% and an output current of

≤100mA. The regulator is switched on or off with a signal

on the EN pin or wake up with a BUS signal.

Initialization

The initialization is started if the power supply is switched on, or after the temperature limitation has switched off the regulator or in case of BUS traffic (wake up).

If the V

CC

voltage level is higher than V

RESEIN

, the reset

time t

RES

is started. This reset time is determined by the voltage level on the VTR pin (see table VTR Programming). After t

RES

a rising edge on the RESET output is

generated (see figure 10 - Initialization).

The regulator is active and can only switched off with a falling edge on EN. The regulator remain with EN=high in active mode and therefore also the V

CC

voltage is active.

The input EN has an internal pull down resistor. If EN=high, the internal pull down current is switched off to minimize the quiescent current.

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 5 Datasheet Rev 1.1 March 2001

RESET Output

The RESET output is switched from low to high if V

SUP

is

switched on and V

CC>VRESE IN

after the time t

RES.

If the voltage VCC drop below V

RES1

or V

RES2

then the RESET

output is switched from high to low after the time t

rr

has been

reached.

The voltage level for V

RES1

and V

RES2

or the correspond-

ing times t

RES

can be programmed via the analogue input

VTR.

Wake up with BUS traffic

If the regulator is put in standby mode it can be wake up with the BUS interface. Every pulse on the BUS (high

pulse or low pulse) with a pulse width of min. 45µs will

switch on the regulator.

After the BUS has wake up the regulator, it can only be switched off with a high level followed by a low level on the EN pin.

Reset Programming on VTR

With the VTR pin the reset switch off levels and delay time can be programmed.

The voltage on VCC influences the reset function.

VTR-Programming

The voltage on VTR input is read out if the voltage at this pin is higher than V

RESEIN

. This value defines the reset

switch off voltage V

RES

and switches on with the next oscillator cycle the pull up current source if VTR=low or the pull down current source if VTR=high. The sources are active for one oscillator cycle. The level changes during this procedures on VTR, wich depends on the external pull up or pull down resistors control the reset tim e t

RR

Temperature Limitation

If the junction temperature 150ºC < Tj < 170ºC the over temperture recognition will be active and the regulator voltage will be switched off. After T

j

fall below 140ºC the TH8060 will be initialized, not depending on of the voltage levels on EN and BUS.

Low Voltage Detectio n V

SUP

Low voltage on V

SUP

is monitored on SENSE output.

If V

SUP

has reached the level of V

SUP

=6.8V then the

SENSE output generates low level. In the normal

Universal Comparat or

The TH8060 consist a universal comparator for general use. The positiv input of this comparator is connected with the pin SI. The input voltage range of SI is 0V...V

SUP.

The function of the TH8060 is possible between T

Ama x

and the switch off temperature, but small parameter differences can appear.

operating range is V

SUP

> 7.8V and the SENSE output

generates a high level.

The input voltage is compared with a fixed reference voltage at high or low level and the comparator output SO drives a 5V digital signal.

VTR-Mode V

RES

t

Res

VTR = GND V

RES

= V

RES1

= 3.15V 100ms

VTR = VCC V

RES

= V

RES2

= 4.65V 100ms

VTR with R ≥ 50kΩ to GND

V

RES

= V

RES1

= 3.15V 15ms

VTR with R ≥ 50kΩ to VCC

V

RES

= V

RES2

= 4.65V 15ms

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 6 Datasheet Rev 1.1 March 2001

Application H ints

Operating during Disturbances

The absence of V

SUP

,VCC or GND connection or ground

shift either alone or in any combination, do not influence

or disturb the communication between other bus nodes.

Undervoltage

The reset unit secures the correct behavior of the driver during undervoltage. The BUS pin generates the recessive state if V

CC

< V

RES1

. The inputs have pull-up or pull-

down characteristics.

With 4.5V ≤ V

CC

≤ 5.25V the bus connection operates

within the correct parameters .

If V

CC

≤4.5V the TxD signal is transmitted to the bus. The

receive mode is also activ.

SENSE and SO output the correct signal if V

CC

> V

RES

. The specificated values of the input voltages on SO can’t guaranteed.

Regulator Circuitry

The choice and dimension of the capacitor on VCC is determined by application point of view. Important parameters are the current difference on load changes and the maximum short time voltage drop.

The VCC pin must be connected to a min. 2µF capacitor

for stable operating of the regulator in the whole operating range.

Short Circuit Proof

All in- and outputs are short circuit proof to battery and ground. A thermal shut down circuit prevent VCC and BUS from any damage

Baud Rate

The TH8060 has a maximum Baud rate of 20 kBaud

(C

BUS

<10nF). This baud rate is supported by the

typically value for the slew rate at BUS of ± 2V/µs.

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 7 Datasheet Rev 1.1 March 2001

Application Circuitry

Figure 6 - Application Circuit

There should be used an LC- or RC-Filter to minimize the influence of EMI on the BUS lines.

Figure 7 - Application Circuit for LIN Subbus

TH8060

VSUP

GND

VTR

EN

GND

SO

SI

BUS

VCC

GND

RESET

SENSE

GND

RxD

TxD

V

Bat

82p

33uH

47n

100u

+5V

100u

µµµµ

C

BUS

battery reverse diode

n.c.

47n

Control Unit incl.

LIN-Protokoll

100p

10

opti onal

V

Bat

100n

+5V

100u

µµµµ

C

100n

1k

V

IN

V

OUT

GND

TH8060

VSUP

GND

VTR

EN

GND

SO

SI

BUS

VCC

GND

RESET

SENSE

GND

RxD

TxD

100n

100u

n.c.

100n

LC-L P

LC-LP

Master-Node

Slave-Node

LIN-BUS

TH8080

RxD

TxD

VCC

n.c.

GND

BUS

VS

n.c.

+5V

µµµµ

C

100n

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 8 Datasheet Rev 1.1 March 2001

Operating Conditions

Electrical Specification

All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding

any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Reliable operation of the TH8060 is only specified within the limits shown in ”Operating conditions”.

Absolute Maximum Ratings

Parameter Symbol Min Max Unit

Battery voltage V

SUP

5.25 18 V

Supply voltage V

CC

4.75 5.25 V

Operating ambient temperature T

A

-40 +125 °C

Junction temperature

[1]

T

Jc

+150 °C

______________________________

[1]

Junction temperature is defined in IEC 747-1

[2]

The current and voltage values ar e valid independent from each other.

[3]

The maximum power dissipation is defined by the ambient temperature and the thermal resistance. It can be calculated wit h

P

0

=(V

SUP-VCC

)*I

VCC+PBUS

. P

BUS

is the BUS driver output with nor mally ≤25 mW

[4]

see over temperature protection

Parameter

Symbol Condition Min Max Unit

Supply voltage at VSUP

[2]

V

SUP

-1.0 18

V

T

≤ 60 s

- 30

T

≤ 500 ms

- 40

Input voltage at pin SI, BUS

[2]

V

BUS

-24 30

V

T ≤ 500 ms

- 40

Difference VSUP-VCC V

SUP-VCC

-0.3 40 V

Input voltage at pin EN and SI V

INENS I

-0.3 V

SUP

+0.3 V

Input voltage at pin VTR, TxD, RxD, SO, RESET, SENSE V

IN

-0.3 V

CC

+0.3 V

Input current at pin EN, VTR, SI, SO, TxD, RxD,RESET,SENSE I

IN

-25 25 mA

Input current for short circuit of pin VSUP and VCC I

Short

-500 500 mA

Power dissipation T

A

= 85 °C

[3]

P0 600 mW

Therm al resistance from junction to ambient R

THJA

50 K/W

Junction temperature

[4]

TJ 150 °C

Storage temperature T

STG

-55 150 °C

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 9 Datasheet Rev 1.1 March 2001

Static Characteristics

(V

SUP

= 5.25 to 18V, VCC= 4.75 to 5.25V, T

A

= -40 to +125°C, unless otherwise specified)

Parameter

Symbol Condition Min Typ Max Unit

Linear Regulator

Output voltage VCC

V

CCn

5.5V ≤ V

SUP

≤ 18V

T

A

= 25°C

4.95 5.0 5.05 V

V

CCt

5.5V ≤ V

SUP

≤ 18V

4.90 5.0 5.10 V

V

CCh

V

SUP

> 18V 4.95 5.0 5.25 V

V

CCI

3.3 V< V

SUP

< 5.5 V VS-VD 5.1 V

Supply current, „normal mode“

[2]

I

Snl

V

EN

= V

SUP

= 12V, Pins 8, 10,

11, 14-16 open

110

µA

V

EN

= 0V 35 50

Drop-out voltage V

D

V

SUP

≥ 4.0V, I

VCC

= 25mA

200 mV

V

SUP

≥ 4.0V, I

VCC

= 100mA

400 mV

V

SUP

≥ 3.3V, I

VCC

= 20mA

600 mV

Output current VCC I

VCC

V

SUP

≥ 3.0V

100 mA

Current limitation VCC I

LVCC

V

SUP

> 0V 300 mA

Power-on-reset threshold “V

CC

on” V

RESEIN

refered to VCC, V

SUP

> 4.6V 4.5 4.65 4.8 V

Power-on-reset threshold “V

CC

off”

V

RES2

VTR=H,V

SUP

> 0V

4.5 4.65 4.8 V

V

RES1

3.0 3.15 3.3

SENSE-Output

VSUP - threshold low at SENSE V

SENL

6.8 V

VSUP - threshold high an SENSE V

SENH

7.8 V

Hysteresis SENSE

V

SENHYS

100 mV

Output voltage low V

OL

I

OUT

= 1mA 0.8 V

Output voltage high V

OH

I

OUT

= -1mA VCC-0.8 V

Enable-Input EN

Input voltage low V

ENL

-0.3 1.75 V

Input voltage high V

ENH

2.5

V

SUP

+0.3

V

Hysteresis

V

ENHYS

100 mV

Pull-down current EN

I

pdEN

V

EN

> V

ENH

1.8 4.0 7.5

µA

V

EN

< V

ENL

70 100 130

µA

Output RESET

Output voltage low VOL

I

OUT

= 1 mA, V

SUP

> 5.5 V 0.8 V

10 kΩ RESET to VCC

V

SUP

= VCC = 0.8 V

0.2 V

Pull-up current Ipu -500 -375 -250

µA

I

Ssleep

Supply current, „sleep mode“

µA

Load capacity C

load

ESR ≤ 5Ω

2

µF

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 10 Datasheet Rev 1.1 March 2001

Static Characteristics (continued)

______________________________

[1] The recessive voltage at pin BUS don’t should be less than 80% of voltage at KL30 V

BAT.

The voltage at V

SUP

results with consideration of

reverse diode V

SUP

= V

BAT

- 0,7V

[2] See t est circuit for dynamic characteristics on page 12

Parameter

Symbol Condition Min Typ Max Unit

Comparator SI, SO

Input Current SI I

INSI

0V ≤ V

SI

≤ 18V

-20 20

µA

Threshold High SI V

IH

1.21 1.4 V

Hysteresis

V

HYS

30 mV

Output voltage low at SO V

OL

I

OUT

= 1 mA, V

SUP

> 5.5 V 0.8 V

10 kΩ SO to VCC, V

CC

> 3.3V

0.4 V

Pull-up current at SO Ipu -500 -375 -250

µA

Input VTR

Threshold low V

TRL

0.15 0.25

VCC

Threshold high V

TRH

0.75 0.85 VCC

Output current low I

OL

VCC > 3.3 V 160 230 300

µA

Output current high I

OH

-300 -230 -160

µA

Power-on-reset threshold V

POR

V

POR

=V

RES1

3.0 3.15 3.3 V

Pull-up current TxD I

pu

-500 -375 -250

µA

Input voltage low TxD V

IL

0.25 VCC

Input voltage high TxD V

IH

0.75

VCC

Input voltage low BUS dominant V

IL

0.45 V

SUP

Input voltage high BUS recessive V

IH

0.55

V

SUP

Hysteresis BUS

V

HYS

50

mV

Input current BUS recessive

[2]

I

INBUS R

8 ≤ V

BUS

≤ 18 V,

V

SUP

= V

BUS

- 0.7V, TxD = high

20

µA

Input current BUS dominant I

INBUS D

V

BUS

= 0V, TxD = high -1

mA

Pull up resistor BUS R

BUSpu

20 30 47

kΩ

Output voltage BUS dominant V

BUSD

V

SUP

= 12V, TxD = low

I

BUS

= 40 mA

1.2 V

Output voltage BUS recessive

[1] [2]

V

BUSR

8 ≤ V

SUP

≤ 18 V, TxD = high

0.8 V

BAT

Current limitation BUS I

LIM

V

BUS

> 2.5V, TxD = low 40

100 mA

Output voltage low RxD V

OL

I

OUT

= 1 mA

0.8 V

Output voltage high RxD V

OH

I

OUT

= -1 mA VCC-0.8

V

LIN -Bus-Interf ace

Input Current SI -I

INSI

VSI = -12V -1 mA

Threshold low SI V

IL

1.05 1.16 V

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 11 Datasheet Rev 1.1 March 2001

Dyna mic Characteristics

All dynamic values of the table below refer to the test-schematic schown in Figure 3 - Test Circuit for Dynamic Characteristics For the definition of delay and transitions times see Figure 2 - TH8060 Timing Diagram.

(7V ≤ V

SUP

≤ 18V, 4.75V ≤ VCC ≤ 5.25V, -40°C ≤ TA ≤ 125°C, unless otherwise specified)

Parameter

Symbol Condition Min Typ Max Unit

RESET

Reset time t

Res

R

VTR

< 1 kΩ

70 100 140 ms

R

VTR

> 45 kΩ

10 15 20 ms

Reset rising time

trr

3.0 6.5 10

µs

LIN-Bus-Interface

Slew rate BUS falling edge

[2]

dV/dT

fall

-2.5 -2.0 -1.0

V/µs

dV/d

Trise

1.0 2.0 2.5

V/µs

Symmetry of Slew rate BUS dV/dT

sym

dV/dT

rise

- dV/dT

fall

C

BUS

= 100 pF

-0.3

0.3

V/µs

Debouncing time BUS t

debBUS

High pulse or low pulse 1.5 2.8 4.0

µs

Symmetry of debouncing BUS t

debsym

-0.5

0.5

µs

Propagation delay TxD -> BUS

[1] [2]

t

trans_pdr

,

t

trans_pdf

4

µs

Symmetry of propagation delay TxD -> BUS

[1]

t

trans_sym

t

trans_pdr

- t

trans_pdf

-2

2

µs

Propagation delay BUS -> RxD

[1] [2]

t

rec_pdr

t

trec_pd f

6

µs

Symmetry of propagation delay BUS -> RxD

[1]

t

rec_sym

t

rec_pdr

- t

rec_pdf

-2

2

µs

Debouncing time TxD

[1]

t

deb

0.6 1.0 1.5

µs

Debouncing time EN

[1]

t

deb

200

ns

Wake-up-debouncing BUS t

debWake

25 45 90

µs

Propagation delay SI -> SO t

pdcomp

4

11

µs

VSUP-SENSE debouncing

[1]

t

deb

10 17 25

µs

20% ≤ V

BUS

 ≤ 80%

100pF ≤ C

BUS

≤ 10nF

20% ≤ V

BUS

 ≤ 80%

C

BUS

= 100 pF

Slew rate BUS rising edge

[2]

______________________________

[1] See timing diagram [2] See t est circuit for dynamic characteristics on page 12

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 12 Datasheet Rev 1.1 March 2001

Timing Diagram

TxD

BUS

t

trans_pdf

RxD

V

BAT

95%

40%

t

trans_pdr

V

BUSD

+0.5V

60%

t

rec_pdf

t

rec_pdr

Test Circuit for Dynamic Characteristics

VSUP

GND

VTR

EN

GND

SO

SI

BUS

VCC

GND

RESET

SENSE

GND

RxD

TxD

TH8060

900

10u

100n

V

SUP

51k

100p

n.c.

Figure 8 - Timing Diagram

Figure 9 - Test Circuit for Delay Time and Slope Control

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 13 Datasheet Rev 1.1 March 2001

VSUP

GND

VTR

EN

GND

SO

SI

BUS

VCC

GND

RESET

SENSE

GND

RxD

TxD

10u

TH8060

100n

IS1

12V

51k

n.c.

Figure 10 - Test Circuit for Supply Current IS1

VSUP

GND

VTR

EN

GND

SO

SI

BUS

VCC

GND

RESET

SENSE

GND

RxD

TxD

10u

TH8060

100n

V

BUSR

VBAT

51k

n.c.

Figure 11 - Test Circuit for Bus Voltage “recessiv” V

BUSR

VSUP

GND

VTR

EN

GND

SO

SI

BUS

VCC

GND

RESET

SENSE

GND

RxD

TxD

10u

TH8060

100n

I

INBUSR

VBAT

51k

n.c.

Figure 12 - Test Circuit for Bus Current “recessiv” I

BUSR

Test Circuit for Dynamic Characteristics (continued)

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

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Page 14 Datasheet Rev 1.1 March 2001

Pin Description

TH8060

1

EN SENSE

GND

VTR

GND

RESET

BUS

SO

SI

n.c.

RxD

TxD

16

15

14

13

12

11

10

98

7

6

5

4

2

3

VSUP VCC

Pin Name I/O Function

1 VSUP Supply voltage

2 EN I Enable Input voltage regulator, HV-pull-down-Input, High-active

3 VTR I Analogue Input - definition of reset time und Reset voltage level

4 GND Ground

5 GND Ground

6 BUS I/O Bi-directional bus line

7 SI I Comparator Input, HV-Input

8 SO O 5V-Comparator Output

9 n.c. not connected

10 RxD O Receive Output, 5V-push-pull

11 TxD I 5V-Transmit Input, pull-up-Input

12 GND Ground

13 GND Ground

14 RESET O 5V-output reset, active low

15 SENSE O 5V-output of VSUP-Monitoring

16 VCC O Regulator output 5V/100mA

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

www.melexis.com

Page 15 Datasheet Rev 1.1 March 2001

Mechanical Specifications

SOIC16 Package Dimensions

123

D

EH

be

A1 A

L

α

Small Out li ne Int egrate d C ir ciut (SOIC ), SOIC 16, 300 mil

All Dimension in mm, coplanarity < 0.1 mm

D E H A A1 e b L

αααα

min

max

10.1

10.5

7.40

7.60

10.00

10.65

2.35

2.65

0.10

0.30

1.27

0.33

0.51

0.40

1.27

0°

8°

All Dimension in inch, coplanarity < 0.004”

min

max

0.398

0.413

0.291

0.299

0.394

0.419

0.093

0.104

0.004

0.012

0.050

0.013

0.020

0.016

0.050

0°

8°

TH8060

LIN Bus Transcei ver w ith integrated Voltage Regulat or

www.melexis.com

Page 16 Datasheet Rev 1.1 March 2001

Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutor y, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right t o change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by Melexis for each application. The inform ation furnished b y Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third part y for an y damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential dam ages, of any kind, in connection with or arising out of the fu rnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third part y shall arise or flow out of Melexis’ rendering of technical or other services. © 2000 Melexis GmbH. All rights reserved.

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