Page 1
TH7111
868/915MHz
FSK/FM/ASK Receiver
Features
! Double superhet architecture for high degree of image rejection
! FSK for digital data and FM reception for analog signal transmission
! FM/FSK demodulation either with phase-coincidence or PLL demodulator
! Low current consumption in active mode and very low standby current
! Switchable LNA gain for improved dynamic range
! AFC feature allows wide carrier frequency acceptance range
! RSSI allows signal strength indication and ASK detection
! Surface mount package LQFP44
Ordering Information
Part No. Temperature Range Package
TH7111 -40 °C to 85 °C LQFP44
Application Examples
! General digital and analog 868 MHz or 915 MHz ISM band usage
! Low-power telemetry
! Alarm and security systems
! Keyless car and central locking
! Pagers
Technical Data Overview
! Input frequency range: 800 MHz to 930 MHz
! Power supply range: 2.5 V to 5.5 V for double conversion and 3.3 V to 5.5 V for single conversion
! Temperature range: -40 °C to +85 °C
! Operating current: 7.5 mA at low gain and 9.2 mA at high gain mode
! Standby current: < 100 nA
! Sensitivity: -109 dBm
! Sensitivity: -102 dBm
! Range of first IF: 10 MHz to 80 MHz
! Range of second IF: 455 kHz to 21.4 MHz
! Maximum input level: –10 dBm at ASK and 0 dBm at FSK
! Image rejection: > 65 dB (e.g. with SAW front-end filter and at 10.7 MHz 2
! Spurious emission: < -70 dBm
! Input frequency acceptance: ±50 kHz (with AFC option)
! RSSI range: 70 dB
! Frequency deviation range: ±5 kHz to ±120 kHz
! Maximum data rate: 80 kbit/s NRZ
! Maximum analog modulation frequency: 15 kHz
1)
at ± 8 kHz FSK deviation, BER = 3⋅10-3 and phase-coincidence demodulation
2)
at ± 50 kHz FSK deviation, BER = 3⋅10-3 and phase-coincidence demodulation
1)
with 40 kHz second IF filter BW (incl. SAW front-end filter loss)
2)
with 150 kHz second IF filter BW (incl. SAW front-end filter loss)
nd
IF)
TH7111 Data Sheet Page 1 of 20 Nov. 2001
3901007111 Rev. 005
Page 2
TH7111
868/915MHz
FSK/FM/ASK Receiver
General Description
The TH7111 receiver IC consists of the following building blocks:
" PLL synthesizer (PLL SYNTH) for generation of the first and second local oscillator signals LO1 and LO2
" Parts of the PLL SYNTH are the high-frequency VCO1, the feedback dividers DIV_16 and DIV_2,
a phase-frequency detector (PFD) with charge pump (CP) and a crystal-based reference oscillator (RO)
" Low-noise amplifier (LNA) for high-sensitivity RF signal reception
" First mixer (MIX1) for down-conversion of the RF signal to the first IF (IF1)
" second mixer (MIX2) for down-conversion of the IF1 to the second IF (IF2)
" IF amplifier (IFA) to amplify and limit the IF2 signal and for RSSI generation
" Phase coincidence demodulator (DEMOD) with third mixer (MIX3) to demodulate the IF signal
" Operational amplifier (OA) for data slicing, filtering, ASK detection and automatic-frequency control (AFC)
" Bias circuitry for bandgap biasing and circuit shutdown
With the T H7111 receiver chip, various circuit c onfigurations can be arranged in order to m eet a number of
different custom er requirements . For FM/FSK reception the IF tank used in the phase coincidence dem odulator can be constituted either by a ceramic resonator or an LC tank (optionally with varactor to create an AFC
circuit). In PLL demodulator configuration, the multiplier MIX3 f orms a phase com parator. In ASK c onfiguration, the RSSI signal is feed to an ASK detector, which is c onstituted by the operational amplif ier. T he sec ond
VCO (VCO2) can be used either as the VCO of a PLL demodulator or as the LO 2 source of a second external PLL in a multi-channel system. The following table briefly summarizes the various configurations.
Single-conversion configuration Double-conversion configuration
FM/FSK
FM/FSK
FM/FSK
FM/FSK
ASK
ASK
The preferred superheter odyne configuration is double conversion where MIX1 and MIX2 are driven by the
internal local oscillator signals LO1 and LO 2, respectively. This allows a high degree of image rejection,
achieved in conjunction with an RF front-end filter. Eff icient RF front- end filtering is r ealized by using a SAW,
ceramic or helix filter in front of the LNA and by adding a LC filter at the LNA output.
It is also possible to use the T H7111 in single-conversion configur ation. This can be ac hieved by switching
the LO2 input of MIX2 from the on-chip PLL synthesizer to the pin IN_MIX2 by means of an internal switch
(done via pin SW_MIX2). Now MIX2 operates as an amplifier f or the IF1 signal if an external pull-down resistor at pin IN_MIX2 is added.
The same setting of MIX2 can be used for multi-channel applications. In this situation IN_MIX2 mus t be
driven by an external LO2 signal. This signal can be generated by the VCO2, which is mainly a bipolar transistor that can be configured as a varactor-tuned VCO. Furthermore, a second external PLL for channel
selection via LO2 tuning is required. This may be arranged by using a PLL synthesizer chip that can be controlled through a 3-wire bus serial interface. The reference signal for the external PLL synthesizer can be
directly taken from the crystal-based reference oscillator RO.
narrow-band RX with ceramic demodulation
tank
wide-band RX with LC demod. tank and AFC wide-band RX with LC demod. tank and AFC
extended sensitivity RX with PLL demodulator extended sensitivity RX with PLL demodulator
RX with RSSI-based demodulation RX with RSSI-based demodulation
narrow-band RX with ceramic demodulation
tank
multi-channel RX with ceramic demodulation
tank and external channel synthesizer
RX with RSSI-based demodulation and external channel synthesizer
TH7111 Data Sheet Page 2 of 20 Nov. 2001
3901007111 Rev. 005
Page 3
Block Diagram
TH7111
868/915MHz
FSK/FM/ASK Receiver
IN_DEM
OUT_IFA
19 20
18
RSSI
29
17
FBC1
16
IN_IFA
151413
VEE_IF
OUT_MIX2
VCC_MIX2
12
VCC_MIX1
11
IF1N
10
IF1P
9
VEE_MIX1
8
CAP_MIX1
7
VEE_LNA
5
IN_MIX1
6
OUT_LNA
43
31
32
OUTP
OUTN
28
27
OAP
OAN
26
OUT_OA
23
24
VCO2_E
VCO2_B
OA
VCO2
VCC_BIAS
25
VEE_BIAS
MIX3
BIAS
VREF
ENRO
ENRX
VCC_PLL
VEE_RO
VEE_PLL
30
37 144
36
34
IFA
RO
ROLF2 SW_MIX2
35
LF1
PFD
IF2
CP
LO2
MIX2MIX1
IF1
LO1
DIV_2
IN_MIX2
switch
DIV_16
VCO1
39 332221 38
GAIN_LNA
VEE_LNAC
2
LNA
IN_LNA
42
VCC_LNA41VEE_LNA
VEE_VCO1
43
40
Fig. 1: TH7111 block diagram
TH7111 Data Sheet Page 3 of 20 Nov. 2001
3901007111 Rev. 005
Page 4
TH7111
868/915MHz
FSK/FM/ASK Receiver
Frequency Planning
Frequency planning is straightforward for single-conversion applications because there is only one IF that
might be chosen, and then the only possible choice is low-side or high-side injection of the LO1 s ignal (which
is now the one and only LO signal in the receiver).
The receiver’s double-conver sion architecture requires careful frequenc y planning. Besides the desired RF
input signal, there are a number of s purious signals that may cause an undesired response at the output.
Among them are the image of the RF signal (that must be suppressed by the RF front-end f ilter), spurious
signals injected to the first IF ( IF1) and their im ages which could be m ixed down to the sam e sec ond IF (IF2)
as the desired RF signal (they must be suppressed by the LC filter at IF1 and/or by low-crosstalk design).
By configuring the TH7111 for double conversion and using its internal PLL synthesizer with fixed feedback
divider ratios of N1 = 16 (DIV_16) and N2 = 2 (DIV_2) , four types of down-conversion ar e possible: low-s ide
injection of LO1 and LO2 (low - low), LO1 low-side and LO2 high-side (low-high), LO1 high-side and LO2
low-side (high-low) or LO1 and LO2 high-s ide (high-high). T he following table sum m arizes som e equations
that are useful to calculate the crystal reference frequency (REF), the firs t IF (IF1) and the VCO1 or firs t LO
frequency (LO1), respectively, for a given RF and second IF (IF2).
Injection type high-high low-low high-low low-high
REF (RF – IF2)/30 (RF – IF2)/34 (RF + IF2)/30 (RF + IF2)/34
LO1
32•REF 32•REF 32•REF 32•REF
IF1 LO1 – RF RF – LO1 LO1 – RF RF – LO1
LO2
2•REF 2•REF 2•REF 2•REF
IF2 LO2 – IF1 IF1 – LO2 IF1 – LO2 LO2 – IF1
The following table depicts generated, desired, pos sible images and som e undesired s ignals cons idering the
examples of 868.3 MHz and 915 MHz RF reception at IF2 = 10.7 MHz.
Signal type RF =
868.3 MHz
Injection type high-high
REF / MHz 28.58667
LO1 / MHz 914.77333
IF1 / MHz 46.47333
LO2 / MHz 57.17333
RF image/MHz 961.24667
IF1 image/MHz 67.87333
RF =
868.3 MHz
low-low
25.22353
807.15294
61.14706
50.44706
746.00588
39.74706
RF =
868.3 MHz
high-low low-high high-high
29.3 25.85294 30.14333
937.6 827.29412 964.58667
69.3 41.00588 49.58667
58.6 51.70588 60.28667
1006.9 786.28824 1014.17
47.9 62.40588 70.98667
RF =
868.3 MHz
RF = 915
MHz
RF = 915
MHz
low-low
26.59706
851.10588
63.89412
53.19412
787.21176
42.49412
RF = 915
MHz
high-low low-high
30.85667 27.22647
987.41333 871.24706
72.41333 43.75294
61.71333 54.45294
1059.83 827.49412
51.01333 65.15294
RF = 915
MHz
The selection of the ref erence crystal frequency is based on som e assumptions. As for example: the f irst IF
and the image frequencies should not be in a radio band where strong interfering signals might occur
(because they could represent parasitic receiving s ignals), the LO1 s ignal should be in the range of 800 MHz
to 915 MHz (because this is the optimum frequency range of the VCO1). Furtherm ore the first IF should be
as high as possible to achieve highest RF image rejection. The colum ns in bold depict the selec ted f r equenc y
plans to receive at 868.3 MHz and 915 MHz, respectively.
TH7111 Data Sheet Page 4 of 20 Nov. 2001
3901007111 Rev. 005
Page 5
TH7111
868/915MHz
FSK/FM/ASK Receiver
Pin Definition and Descripti on
Pin No. Name I/O Type Functional Schematic Description
1 VREF analog
output
VREF
1
60k
reference voltage output,
approx. 1.23V
4 OUT_LNA analog
output
42 IN_LNA analog
input
2 VEE_LNAC ground
IN_LNA
42
5k
OUT_LNA
4
VEE_LNAC
2
LNA open-collector output,
to be connected to external
LC tank that resonates at RF
LNA input,
approx. 26Ω single-ended
ground of LNA core
(cascode)
3 GAIN_LNA analog
input
GAIN_LNA
3
400
Ω
LNA gain control (CMOS
input with hysteresis)
5 VEE_LNA ground LNA biasing ground
6 IN_MIX1 analog
input
7 CAP_MIX1 analog I/O
IN_MIX1
6
CAP_MIX1
7
Ω
13
Ω
13
500µA
40µA
Ω
330
MIX1 input, approx. 33Ω
single-ended
connection for MIX1
blocking capacitor
8 VEE_MIX1 ground MIX1 ground
20p
VCC
20p
IF1N
10
connected to external LC
tank that resonates at first IF
open-collector output, to be
9 IF1P analog I/O open-collector output, to be
IF1P
9
10 IF1N analog I/O
connected to external LC
VEE
2x500µA
VEE
tank that resonates at first IF
TH7111 Data Sheet Page 5 of 20 Nov. 2001
3901007111 Rev. 005
Page 6
TH7111
868/915MHz
FSK/FM/ASK Receiver
Pin No. Name I/O Type Functional Schematic Description
11 VCC_MIX1 supply MIX1 positive supply
12 VCC_MIX2 supply MIX2 positive supply
13 OUT_MIX2 analog
output
OUT_MIX2
13
130
6.8k
Ω
230µA
MIX2 output, approx. 330Ω
output impedance
14 VEE_IF ground ground of MIX2, IFA and
DEMOD
2.2k
200µA
VCC
IFA input, approx. 2.2kΩ
input impedance
FBC1
16
IFA feedback capacitor
VEE
to be connected to external
IFA feedback capacitor
15 IN_IFA analog
VCC
input
IN_IFA
15
VEE
FBC2
17
VCC
2.2k
VEE
VEE
16 FBC1 analog I/O to be connected to external
17 FBC2 analog I/O
18 VCC_IF supply positive supply for IFA,
DEMOD and VCO2
19 OUT_IFA analog I/O
IFA output and MIX3 input
(of DEMOD)
OUT_IFA
19
40µA
20 IN_DEM analog
input
IN_DEM
20
47k
DEMOD input, to MIX3 core
21 SW_MIX2 digital
input
SW_MIX2
21
400
Ω
input selection for LO2 input
port of MIX2
TH7111 Data Sheet Page 6 of 20 Nov. 2001
3901007111 Rev. 005
Page 7
TH7111
868/915MHz
FSK/FM/ASK Receiver
Pin No. Name I/O Type Functional Schematic Description
22 IN_MIX2 analog
input
24 VCO2_B analog
input
IN_MIX2
22
VCO2_B
Ω
840
Ω
840
20µA
VCC VCC
47k
external LO2 input port of
MIX2, approx. 1kΩ singleended
VCO2 input, base of
a bipolar transistor
24
VEE
23 VCO2_E analog
output
VCC
VCO2 output, emitter of
a bipolar transistor
VCO2_E
23
VEE
25 VCC_BIAS supply positive supply of general
bias system and OA
26 OUT_OA analog
output
OUT_OA
Ω
50
OA output, 40uA current
drive capability
26
27 OAN analog
input
28 OAP analog
input
29 RSSI analog
output
OAN
27
50
RSSI
29
20µA
Ω
Ω
50
50
I (Pi)
36k
Ω
negative OA input, input
voltage limited to approx.
between pins OAP
pp
OAP
0.7 V
and OAN
positive OA input, input
28
voltage limited to approx.
0.7 V
between pins OAP
pp
and OAN
RSSI output, for RSSI and
ASK detection, approx.
36kΩ output impedance
30 VEE_BIAS ground ground for general bias
system and OA
TH7111 Data Sheet Page 7 of 20 Nov. 2001
3901007111 Rev. 005
Page 8
TH7111
868/915MHz
FSK/FM/ASK Receiver
Pin No. Name I/O Type Functional Schematic Description
31 OUTP analog
output
32 OUTN analog
output
OUTP
OUTN
31
32
Ω
50
20µA
20µA
FSK/FM positive output,
output impedance of
100kΩ to 300kΩ
FSK/FM negative output,
output impedance of
100kΩ to 300kΩ
33 VEE_PLL ground ground of dividers and PFD
34 VEE_RO ground RO ground
35 RO analog
input
RO
35
50k
30p
30p
RO input, Colpitts type
oscillator with internal feedback capacitors
36 VCC_PLL supply positive supply of RO, DIV,
PFD and charge pump
37 ENRX digital
input
ENRX
ENRO
1.5k
mode control input
(CMOS input)
44 ENRO digital
input
37
44
mode control input
(CMOS input)
38 LF1 analog
charge pump output
output
LF1
38
200
Ω
39 LF2 analog
VCO1 control input
input
LF2
39
400
Ω
4p
40 VEE_VCO1 ground ground of VCO1 and charge
pump
41 VEE_LNA ground ground of LNA biasing
43 VCC_LNA supply positive supply of LNA
biasing
TH7111 Data Sheet Page 8 of 20 Nov. 2001
3901007111 Rev. 005
Page 9
FSK/FM/ASK Receiver
Technical Data
Mode Configurations
ENRX ENRO Mode Description
0 0 SBY standby mode
0 1 RO only only reference oscillator active
1 0 ON entire chip active
1 1 ON entire chip active
Note: ENRX and ENRO are pulled down internally
Second Mixer Input
IN_MIX2V SW_MIX2 Mode
External LO2 0 double conversion with external LO2
Ext. pull-down res. (15 kΩ)
N/C 1 double conversion with internal LO2
0 single conversion
TH7111
868/915MHz
LNA Gain Control
V
GAIN_LNA
Mode Description
< 0.8 V HIGH GAIN LNA set to high gain by voltage at GAIN_LNA
> 1.4 V LOW GAIN LNA set to low gain by voltage at GAIN_LNA
Note: hysteresis between gain modes to ensure stability
Absolute Maximum Ratings
Parameter Symbol Condition / Note Min Max
Supply voltage V
Input voltage V
Input RF level P
Storage temperature T
cc
IN
imax
STG
Electrostatic discharge ESD
0 7.0 V
- 0.3 VCC+0.3 V
no damage 10 dBm
-40 +125 °C
human body model,
MIL STD 833D
method 3015.7, all pins
except OUT_IFA
pin OUT_IFA -500 +250 V
Normal Operating Conditions
-500
+500
Unit
V
Parameter Symbol Condition Min Max Unit
Supply voltage for double conv. V
Supply voltage for single conv. V
Operating temperature T
Input frequency f
Frequency deviation
FSK data rate R
FM bandwidth f
ASK data rate R
cc, DC
cc, SC
a
i
∆f
FSK
m
ASK
2.5 5.5 V
3.3 5.5 V
-40 +85 ºC
800 930 MHz
at FM or FSK
±5 ±120
kHz
NRZ 40 kbit/s
15 kHz
NRZ 80 kbit/s
TH7111 Data Sheet Page 9 of 20 Nov. 2001
3901007111 Rev. 005
Page 10
DC Characteristics
all parameters under normal operating conditions, unless otherwise stated;
typical values at T
= 23 °C and V
a
cc
= 3 V
Parameter Symbol Condition Min Typ Max Unit
Standby current I
Total supply current at low gain I
SBY
cc, low
ENRX=0 100 nA
ENRX=1,
LNA at LOW GAIN
Total supply current at high gain I
cc, high
ENRX=1,
LNA at HIGH GAIN
Opamp input offset voltage V
Opamp input offset current I
Opamp input bias current I
RSSI voltage at low input level V
offs
offs
bias
RSSI, low
I
– I
OAP
OAN
0.5 * (I
OAP
+ I
Pi = -65 dBm,
) -100 100 nA
OAN
LNA at LOW GAIN
RSSI voltage at high input level V
RSSI, high
Pi = -35 dBm,
LNA at LOW GAIN
TH7111
868/915MHz
FSK/FM/ASK Receiver
6.0 7.5 9.0 mA
7.5 9.2 11.0 mA
-20 20 mV
-50 50 nA
0.5 1.0 1.5 V
1.25 1.9 2.45 V
AC System Characteristics
all parameters under normal operating conditions, unless otherwise stated;
all parameters based on test circuits for FSK (Fig. 2), FM (Fig. 4) and ASK (Fig. 5), respectively;
typical values at T
= 23 °C and V
a
= 3 V, RF at 868.3MHz, second IF at 10.7 MHz
cc
Parameter Symbol Condition Min Typ Max Unit
Start-up time – fast mode
FSK/FM
T
fast
ENRX from 0 to 1,
0.4 ms
ENRO = 1,
valid data at output
Start-up time – slow mode
FSK/FM
T
slow
ENRX from 0 to 1,
0.9 ms
ENRO = 0,
valid data at output
Start-up time – ASK T
ASK
depends on ASK de-
R3•C13
tector time constant
Input sensitivity – FSK
(narrow band)
Input sensitivity – FSK
(wide band)
Input sensitivity – ASK
(narrow band)
Input sensitivity – ASK
(wide band)
Maximum input signal – FSK/FM P
Maximum input signal – ASK P
P
min, n
P
min, w
P
minA, n
P
minA, w
max, FM
max, ASK
and start-up mode,
valid data at output
B
= 40kHz
IF2
∆f = ±15kHz (FSK/FM)
BER ≤ 3⋅10
B
= 150kHz
IF2
∆f = ±50kHz (FSK/FM)
BER ≤ 3⋅10
B
= 40kHz
IF2
BER ≤ 3⋅10
B
= 150kHz
IF2
BER ≤ 3⋅10
BER ≤ 3⋅10
LNA at LOW GAIN
BER ≤ 3⋅10
-3
-3
-3
-3
-3
-3
-109 dBm
-102 dBm
-108 dBm
-104 dBm
0dBm
-10 dBm
T
(or T
LNA at LOW GAIN
Spurious emission P
Image rejection
Blocking immunity
VCO gain K
Charge pump current I
∆P
∆P
CP
spur
VCO
imag
block
∆f
> ±2MHz, note 1
block
65 dB
57 dB
250 MHz/V
60 µA
-70 dBm
Notes: 1. desired signal with FSK/FM or ASK modulation, CW blocking signal
+
fast
slow
ms
)
TH7111 Data Sheet Page 10 of 20 Nov. 2001
3901007111 Rev. 005
Page 11
Test Circuits
FSK Reception
TH7111
868/915MHz
FSK/FM/ASK Receiver
L2
XTAL
R1
C5
VCC
C3
C1
VCC
VEE
VEE
RO
VCC
ENRX
LF1
LF2
VEE
VEE
IN_LNA
VCC
ENRO
C15
OUTN
VEE
OUTP
GAIN_LNA
C17C16
VEE
RSSI
LQFP44
VEE
OUT_LNA
VCC
OUT_OA
VEE
VCC
IF1P
VCO2_B
SW_MIX2
IN_DEM
OUT_IFA
OUT_MIX2
IF1N
OAN
OAP
IN_MIX1
CAP_MIX1
VCO2_E
VCC
FBC2
FBC1
IN_IFA
VEE
VCC
IN_MIX2
VCC
C14
C13
CP
CERRES
VCC
C12
C10
C11
CERFIL
VCC
L5
VCC
CB*
L1
SAWFIL
C4
VREF
L3
C8
C7
C6
C9
L4
LCFIL
VCC
Fig. 2: Test circuit for FSK reception
TH7111 Data Sheet Page 11 of 20 Nov. 2001
3901007111 Rev. 005
Page 12
FSK/FM/ASK Receiver
FSK test circuit component list to Fig. 2
Part Size Value / Type Tolerance Description
C1 0805 15 pF
C3 0805 1 nF
C4 0603 4.7 pF
C5 0603 2.7 pF
C6 0603 NIP
C7 0603 1.2 pF
C8 0603 330 pF
C9 0603 22 pF
C10 0805 33 nF
C11 0603 1 nF
C12 0603 1 nF
C13 0603 1.5 pF
C14 0603 680 pF
CP 0805 10 – 12 pF
C15 0805 10 – 47 pF
C16 0805 10 – 47 pF
C17 0603 330 pF
R1 0805
L1 0603 12 nH
L2 0603 12 nH
L3 0603 6.8 nH
L4 0805 100 nH
L5 0805 100 nH
XTAL HC49-
SAWFIL QCC8C
CERFIL
CERRES SMD type CDA CV10.7MG18-A
SMD
leaded
type
SMD type SFECV10.7MJS-A
10 kΩ±10%
25.22353 MHz
@ RF = 868.3 MHz
B3570
@ RF = 868.3 MHz
SFE10.7MFP
= 40 kHz
@ B
IF2
= 150 kHz
@ B
IF2
NIP – not in place, may be used optionally
±10%
±10%
±5%
±5%
±5%
±5%
±10%
±5%
±10%
±10%
±10%
±5%
±10%
±5%
±5%
±5%
±10%
±5%
±5%
±5%
±5%
±5%
±25ppm calibra-
tion
±30ppm temp.
B
= 1.7 MHz
3dB
TBD
±40 kHz
crystal series capacitor
loop filter capacitor
capacitor to match to SAW filter input
capacitor to match to SAW filter output
LNA output tank capacitor
MIX1 input matching capacitor
MIX1 blocking capacitor
IF1 tank capacitor
IFA feedback capacitor
IFA feedback capacitor
IFA feedback capacitor
DEMOD phase-shift capacitor
DEMOD coupling capacitor
CERRES parallel capacitor
demodulator output low-pass capacitor, depending on
data rate
demodulator output low-pass capacitor, depending on
data rate
RSSI output low-pass capacitor
loop filter resistor
inductor to match SAW filter
inductor to match SAW filter
LNA output tank inductor
IF1 tank inductor
IF1 tank inductor
fundamental-mode crystal, C
C
0, max
= 7 pF, R
m, max
= 50 Ω
low-loss SAW filter from EPCOS
ceramic filter from Murata
ceramic demodulator tank from Murata
TH7111
868/915MHz
= 10 pF to 15pF,
load
TH7111 Data Sheet Page 12 of 20 Nov. 2001
3901007111 Rev. 005
Page 13
FSK Circuit with AFC and Ceramic Resonator Tolerance Compensation
C17C16
C18
C19
VCC
OAN
OAP
RSSI
VCC
OUT_OA
VCO2_B
SW_MIX2
IN_DEM
OUT_IFA
XTAL
VCC
C1
VEE
VEE
RO
VCC
ENRX
C15
OUTN
R4
OUTP
R5
VEE
TH7111
868/915MHz
FSK/FM/ASK Receiver
R3
IN_MIX2
CP
VCO2_E
VCC
C14
C13
VD
CERRES
L2
L1
C3
R1
C5
VCC
SAWFIL
C4
LF1
LF2
VEE
VEE
IN_LNA
VCC
ENRO
VREF
LQFP44
VEE
GAIN_LNA
L3
VEE
OUT_LNA
C6
IN_MIX1
C8
C7
VEE
CAP_MIX1
IF1P
C9
L4
VCC
FBC2
FBC1
IN_IFA
VEE
OUT_MIX2
VCC
IF1N
VCC
L5
LCFIL
VCC
C12
C10
C11
CERFIL
VCC
CB*
VCC
Fig. 3: Test circuit for FSK with AFC and resonator compensation
Circuit Feature
! Improves input frequency acceptance range up to RF
±50 kHz
nom
! Eliminates calibration tolerances of ceramic resonator
! Eliminates temperature tolerances of ceramic resonator
! Non-inverted and inverted CMOS-compatible outputs
TH7111 Data Sheet Page 13 of 20 Nov. 2001
3901007111 Rev. 005
Page 14
FSK/FM/ASK Receiver
FSK test circuit with AFC component list to Fig. 3
Part Size Value / Type Tolerance Description
C1 0805 15 pF
C3 0805 1 nF
C4 0603 4.7 pF
C5 0603 2.7 pF
C6 0603 NIP
C7 0603 1.2 pF
C8 0603 330 pF
C9 0603 22 pF
C10 0805 33 nF
C11 0603 1 nF
C12 0603 1 nF
C13 0603 1.5 pF
C14 0603 680 pF
CP 0805 27 pF
C15 0805 10 – 47 pF
C16 0805 10 – 47 pF
C17 0603 330 pF
C18 33 nF
C19 0805
R1 0805
R3
R4
R5
L1 0603 12 nH
L2 0603 12 nH
L3 0603 6.8 nH
L4 0805 100 nH
L5 0805 100 nH
VD SOD-323 BB535
XTAL HC49-
SAWFIL QCC8C
CERFIL
CERRES SMD type CDA CV10.7MG18-A
0805
0805
0805
SMD
leaded
type
SMD type SFECV10.7MJS-A
33 nF
10 nF
1 nF
10 kΩ±10%
100 kΩ
680 kΩ±10%
680 kΩ±10%
25.22353 MHz
@ RF = 868.3 MHz
B3570
@ RF = 868.3 MHz
SFE10.7MFP
= 40 kHz
@ B
IF2
= 150 kHz
@ B
IF2
NIP – not in place, may be used optionally
±10%
±10%
±5%
±5%
±5%
±5%
±10%
±5%
±10%
±10%
±10%
±5%
±10%
±5%
±5%
±5%
±10%
±10%
±10%
±10%
±5%
±5%
±5%
±5%
±5%
±25ppm calibra-
tion
±30ppm temp.
B
= 1.7 MHz
3dB
TBD
±40 kHz
crystal series capacitor
loop filter capacitor
capacitor to match to SAW filter input
capacitor to match to SAW filter output
LNA output tank capacitor
MIX1 input matching capacitor
MIX1 blocking capacitor
IF1 tank capacitor
IFA feedback capacitor
IFA feedback capacitor
IFA feedback capacitor
DEMOD phase-shift capacitor
DEMOD coupling capacitor
ceramic resonator loading capacitor
demodulator output low-pass capacitor, depending on
data rate
demodulator output low-pass capacitor, depending on
data rate
RSSI output low-pass capacitor
integrator capacitor, fixed
integrator capacitor, @ 0.5 to 2 kbit/s NRZ
integrator capacitor, @ 2 to 20 kbit/s NRZ
integrator capacitor, @ 20 to 40 kbit/s NRZ
loop filter resistor
varactor diode biasing resistor
integrator resistor
integrator resistor
inductor to match SAW filter
inductor to match SAW filter
LNA output tank inductor
IF1 tank inductor
IF1 tank inductor
varactor diode from Infineon
fundamental-mode crystal, C
C
0, max
= 7 pF, R
m, max
= 50 Ω
low-loss SAW filter from EPCOS
ceramic filter from Murata
ceramic demodulator tank from Murata
TH7111
868/915MHz
= 10 pF to 15pF,
load
TH7111 Data Sheet Page 14 of 20 Nov. 2001
3901007111 Rev. 005
Page 15
FM Reception
TH7111
868/915MHz
FSK/FM/ASK Receiver
L2
XTAL
R1
C5
VCC
C3
C1
VCC
VEE
VEE
RO
VCC
ENRX
LF1
LF2
VEE
VEE
IN_LNA
VCC
ENRO
OUTN
VEE
C17
OUTP
GAIN_LNA
R6
R5
C16
VEE
RSSI
LQFP44
VEE
OUT_LNA
C15
R4
OAP
IN_MIX1
VCC
R3
OUT_OA
VEE
VCC
IF1P
VCO2_B
SW_MIX2
IN_DEM
OUT_IFA
OUT_MIX2
IF1N
OAN
CAP_MIX1
VCO2_E
VCC
FBC2
FBC1
IN_IFA
VEE
VCC
IN_MIX2
VCC
C14
C13
CP
CERRES
VCC
C12
C10
C11
CERFIL
VCC
L5
VCC
CB*
L1
SAWFIL
C4
VREF
L3
C8
C7
C6
C9
L4
LCFIL
VCC
Fig. 4: Test circuit for FM reception
TH7111 Data Sheet Page 15 of 20 Nov. 2001
3901007111 Rev. 005
Page 16
FSK/FM/ASK Receiver
FM test circuit component list to Fig. 4
Part Size Value / Type Tolerance Description
C1 0805 15 pF
C3 0805 1 nF
C4 0603 4.7 pF
C5 0603 2.7 pF
C6 0603 NIP
C7 0603 1.2 pF
C8 0603 330 pF
C9 0603 22 pF
C10 0805 33 nF
C11 0603 1 nF
C12 0603 1 nF
C13 0603 1.5pF
C14 0603 680 pF
CP 0805 10 –12 pF
C15 0805 100 pF
C16 0805 100 pF
C17 0603 330 pF
R1 0805
R3 0805
R4 0805
R5 0805
R6 0805
L1 0603 12 nH
L2 0603 12 nH
L3 0603 6.8 nH
L4 0603 100 nH
L5 0603 100 nH
XTAL HC49-
SAWFIL QCC8C
CERFIL
CERRES SMD type CDA CV10.7MG18-A
SMD
leaded
type
SMD type SFECV10.7MJS-A
10 kΩ±10%
12 kΩ±5%
6.8 kΩ±5%
33 kΩ±5%
33 kΩ±5%
25.22353 MHz
@ RF = 868.3 MHz
B3570
@ RF = 868.3 MHz
SFE10.7MFP
= 40 kHz
@ B
IF2
= 150 kHz
@ B
IF2
NIP – not in place, may be used optionally
±10%
±10%
±5%
±5%
±5%
±5%
±10%
±5%
±10%
±10%
±10%
±5%
±10%
±5%
±5%
±5%
±10%
±5%
±5%
±5%
±5%
±5%
±25ppm calibra-
tion
±30ppm temp.
B
= 1.7 MHz
3dB
TBD
±40 kHz
crystal series capacitor
loop filter capacitor
capacitor to match to SAW filter input
capacitor to match to SAW filter output
LNA output tank capacitor
MIX1 input matching capacitor
MIX1 blocking capacitor
IF1 tank capacitor
IFA feedback capacitor
IFA feedback capacitor
IFA feedback capacitor
DEMOD phase-shift capacitor
DEMOD coupling capacitor
CERRES parallel capacitor
sallen-key low-pass filter capacitor, to set cut-off fre-
quency
sallen-key low-pass filter capacitor, to set cut-off fre-
quency
RSSI output low-pass capacitor
loop filter resistor
sallen-key filter resistor, to set desired filter characteristic
sallen-key filter resistor, to set desired filter characteristic
sallen-key filter resistor, to set cut-off frequency
sallen-key filter resistor, to set cut-off frequency
inductor to match SAW filter
inductor to match SAW filter
LNA output tank inductor
IF1 tank inductor
IF1 tank inductor
fundamental-mode crystal, C
C
0, max
= 7 pF, R
m, max
= 50 Ω
low-loss SAW filter from EPCOS
ceramic filter from Murata
ceramic demodulator tank from Murata
TH7111
868/915MHz
= 10 pF to 15pF,
load
TH7111 Data Sheet Page 16 of 20 Nov. 2001
3901007111 Rev. 005
Page 17
ASK Reception
XTAL
C1
VEE
VEE
RO
TH7111
868/915MHz
FSK/FM/ASK Receiver
R3
C14
OUT_OA
VCC
VCC
VCO2_E
VCO2_B
SW_MIX2
IN_MIX2
VCC
C13
VEE
OUTP
OUTN
RSSI
OAN
OAP
L2
L1
IF1P
C9
LCFIL
IN_DEM
OUT_IFA
VCC
FBC2
FBC1
IN_IFA
VEE
OUT_MIX2
VCC
IF1N
L5
VCC
C12
C10
C11
CERFIL
VCC
VCC
CB*
VCC
C3
R1
C5
VCC
SAWFIL
C4
ENRO
VCC
ENRX
LF1
LF2
VEE
VEE
IN_LNA
VCC
R4
LQFP44
VREF
VEE
GAIN_LNA
L3
VEE
OUT_LNA
C6
IN_MIX1
C8
C7
CAP_MIX1
VEE
L4
VCC
Fig. 5: Test circuit for ASK reception
TH7111 Data Sheet Page 17 of 20 Nov. 2001
3901007111 Rev. 005
Page 18
FSK/FM/ASK Receiver
ASK test circuit component list to Fig. 5
Part Size Value / Type Tolerance Description
C1 0805 15 pF
C3 0805 1 nF
C4 0603 4.7 pF
C5 0603 2.7 pF
C6 0603 NIP
C7 0603 1.2 pF
C8 0603 330 pF
C9 0805 22 pF
C10 0805 33 nF
C11 0603 1 nF
C12 0603 1 nF
C13 0805 1 nF to 10 nF
C14 0603 330 pF
R1 0805
R3 0603
L1 0603 12 nH
L2 0603 12 nH
L3 0603 6.8 nH
L4 0603 100 nH
L5 0603 100 nH
XTAL HC49-
SAWFIL QCC8C
CERFIL
SMD
leaded
type
SMD type SFECV10.7MJS-A
10 kΩ±10%
100 kΩ±5%
25.22353 MHz
@ RF = 868.3 MHz
B3570
@ RF = 868.3 MHz
SFE10.7MFP
= 40 kHz
@ B
IF2
= 150 kHz
@ B
IF2
NIP – not in place, may be used optionally
±10%
±10%
±5%
±5%
±5%
±5%
±10%
±5%
±10%
±10%
±10%
±10%
±10%
±5%
±5%
±5%
±5%
±5%
±25ppm calibra-
tion
±30ppm temp.
B
= 1.7 MHz
3dB
TBD
±40 kHz
crystal series capacitor
loop filter capacitor
capacitor to match to SAW filter input
capacitor to match to SAW filter output
LNA output tank capacitor
MIX1 input matching capacitor
MIX1 blocking capacitor
IF1 tank capacitor
IFA feedback capacitor
IFA feedback capacitor
IFA feedback capacitor
ASK data slicer capacitor, depending on data rate
RSSI output low-pass capacitor
loop filter resistor
ASK data slicer resistor, depending on data rate
inductor to match SAW filter
inductor to match SAW filter
LNA output tank inductor
IF1 tank inductor
IF1 tank inductor
fundamental-mode crystal, C
C
0, max
= 7 pF, R
m, max
= 50 Ω
low-loss SAW filter from EPCOS
ceramic filter from Murata
TH7111
868/915MHz
= 10 pF to 15pF,
load
TH7111 Data Sheet Page 18 of 20 Nov. 2001
3901007111 Rev. 005
Page 19
Package Dimensions
TH7111
868/915MHz
FSK/FM/ASK Receiver
D
D1
33
23
34
E
E1
44
1
A1A2A
11
L
b
22
e
12
Fig. 6: LQFP44 (Low Quad Flat Package)
All Dimension in mm, coplanaríty < 0.1mm
E1, D1 A A1 A2 e b L E, D
min 0.05 1.35 0.30 0.45 0°
10.00 0.8 12.00
max 1.60 0.15 1.45 0.45 0.75 7°
All Dimension in inch, coplanaríty < 0.004”
min 0.002 0.053 0.012 0.018 0°
0.394 0.031 0.472
max 0.630 0.006 0.057 0.018 0.030 7°
αααα
TH7111 Data Sheet Page 19 of 20 Nov. 2001
3901007111 Rev. 005
Page 20
Your Notes
TH7111
868/915MHz
FSK/FM/ASK Receiver
Important Notice
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of S ale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it
is necessary to check with Melexis for current information. This product is intended for use in normal com mercial applications. Applications requi ring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life- support or life-sustaining equi pment are specifically not recommended without additional processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to
recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services.
© 2000 Melexis GmbH. All rights reserved.
For the latest version of thi s document. Go to our website at
www.melexis.com
Or for additional informat i on contact Melexis Direct:
Europe and Japan: All other locations:
Phone: +32 1361 1631 Phone: +1 603 223 2362
QS9000, VDA6.1 and ISO14001 Certified
TH7111 Data Sheet Page 20 of 20 Nov. 2001
3901007111 Rev. 005
Loading...