Datasheet TP28F010-90, TP28F010-150, TP28F010-120, TN28F010-150, TN28F010-120 Datasheet (Intel Corporation)

E

December 1997

28F010 1024K (128K X 8) CMOS

FLASH MEMORY

8

n

Flash Electrical Chip-Erase

 1 Second Typical Chip-Erase

n

Quick-Pulse Programming Algorithm

 10 µs Typical Byte-Program
 2 Second Chip-Program

n

100,000 Erase/Program Cycles

n

12.0 V ±5% V

n

High-Performance Read

 90 ns Maximum Access Time

n

CMOS Low Power Consumption

 10 mA Typical Active Current
 50 µA Typical Standby Current
 0 Watts Data Retention Power

n

Integrated Program/Erase Stop Timer

Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory content s can be rewrit ten: in a t est s ocket ; in a PROM-program mer sock et; on­board during subassembly test; in-system during final test; and in-system after sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.

PP

n

Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface

n

Noise Immunity Features

 ±10% V
 Maximum Latch-Up Immunity

through EPI Processing

n

ETOX™ Nonvolatile Flash Technology

 EPROM-Compatible Process Base
 High-Volume Manufacturing

Experience

n

JEDEC-Standard Pinouts

 32-Pin Plastic Dip
 32-Lead PLCC
 32-Lead TSOP

(See Packaging Spec., Order #231369)

n

Extended Temperature Options

Tolerance

CC

The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 byt es of eight bits. Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.

Extended erase and program cycling capability is designed into Intel's ETOX™ (EPROM Tunnel Oxide)
process technology. A dvanced oxide processing, an optimized t unneling structure, and lower elect ric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V V
28F010 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.

Intel's 28F010 employs adv anced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to nois e. Its 90 ns acc ess time provides z ero wait-state performanc e
for a wide range of microprocessors and microcontrol lers. Max imum st andby c urrent of 100 µA t ranslat es i nto
power savings when the device is deselected. Finall y, the highest degree of latc h-up protection is achieved
through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on
address and data pins, from –1 V to V

With Intel's ETOX process technology bas e, the 28F010 builds on years of EPROM experience to yield t he
highest levels of quality, reliability, and cost-effectiveness.

CC

+ 1 V.

Order Number: 290207-012

supply, the

PP

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F010 may contain design defects or errors known as errata. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:
Intel Corporation

P.O. Box 5937
Denver, CO 80217-9808

or call 1-800-548-4725

or visit Intel’s website at http://www.intel.com
Copyright © Intel Corporation 1996, 1997.

* Third-party brands and names are the property of their respective owners.

E 28F010

CONTENTS

PAGE PAGE

1.0 APPLICATIONS..............................................5

2.0 PRINCIPLES OF OPERATION .......................8

2.1 Integrated Stop Timer ..................................8

2.2 Write Protection ...........................................9

2.2.1 Bus Operations......................................9

2.2.1.1 Read...............................................9

2.2.1.2 Output Disable................................9

2.2.1.3 Standby ........................................10

2.2.1.4 Intelligent Identifier Operation.......10

2.2.1.5 Write.............................................10

2.2.2 Command Definitions..........................10

2.2.2.1 Read Command............................11

2.2.2.2 Intelligent Identifier Command ......11

2.2.2.3 Set-Up Erase/Erase Commands...12

2.2.2.4 Erase Verify Command.................12

2.2.2.5 Set-Up Program/Program

Commands ..................................12

2.2.2.6 Program Verify Command ............12

2.2.2.7 Reset Command...........................13

2.2.3 Extended Erase/Program Cycling........13

2.2.4 Quick-Pulse Programming Algorithm...13

2.2.5 Quick-Erase Algorithm.........................13

3.0 DESIGN CONSIDERATIONS........................16

3.1 Two-Line Output Control............................16

3.2 Power Supply Decoupling..........................16

Trace on Printed Circuit Boards...........16

3.3 V

PP

3.4 Power-Up/Down Protection........................16

3.5 28F010 Power Dissipation .........................16

4.0 ELECTRICAL SPECIFICATIONS..................18

4.1 Absolute Maximum Ratings........................18

4.2 Operating Conditions..................................18

4.3 Capacitance...............................................18

4.4 DC Characteristics—TTL/NMOS

Compatible—Commercial Products...........19

4.5 DC Characteristics—CMOS Compatible—

Commercial Products................................20

4.6 DC Characteristics—TTL/NMOS
Compatible—Extended Temperature

Products....................................................22

4.7 DC Characteristics—CMOS Compatible—

Extended Temperature Products...............23

4.8 AC Characteristics—Read-Only
Operations—Commercial and Extended

Temperature Products...............................25

4.9 AC Characteristics—Write/Erase/Program
Only Operations —Commercial and

Extended Temperature Products...............27

4.10 AC Characteristics—Alternative CE#­Controlled Writes— Commercial and

Extended Temperature..............................31

4.11 Erase and Programming Performance......32

5.0 ORDERING INFORMATION..........................33

6.0 ADDITIONAL INFORMATION.......................33

3

28F010 E

REVISION HISTORY

Number Description

-007 Removed 200 ns Speed Bin

-008 Corrected AC Waveforms

-009 Added 28F010-65 and 28F010-90 speeds

Revised Erase Maximum Pulse Count for Figure 4 from 3000 to 1000
Clarified AC and DC Test Conditions
Added “dimple” to F TSOP Package

Corrected Serpentine Layout

Added Extended Temperature Options

———— ———

Revised Symbols, i.e., CE, OE, etc. to CE#, OE#, etc.

-010 Completion of Read Operation Table
Labelling of Program Time in Erase/Program Table
Textual Changes or Edits
Corrected Erase/Program Times

-011 Minor changes throughout document

-012 Removed 65 ns speed bin
Removed TSOP package
Added Extended Temperature options
Modified
Modified

AC Test Conditions
AC Characteristics

4

E 28F010

1.0 APPLICATIONS

The 28F010 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These
features make the 28F010 an innovat ive alt ernative
to disk, EEPROM, and battery-backed st atic RAM.
Where periodic updates of code and data tables are
required, the 28F010’s reprogrammability and
nonvolatility make it the obvious and ideal
replacement for EPROM.

Primary applications and operat ing systems stored
in flash eliminate the s low disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption—a considerat i on particularly important

in portable equipment. Flash memory increases
flexibility with electrical chip eras ure and in-system
update capability of operating systems and
application code. With updatable code, system
manufacturers can easil y ac commodat e last -minute
changes as revisions are made.

In diskless workstations and terminals, network
traffic reduces to a minimum and systems are
instant-on. Reliability exceeds that of electro­mechanical media. Often in these environments,
power interruptions force ext ended re-boot periods
for all networked terminals. This mishap is no
longer an issue if boot code, operating systems,
communication protocols and primary applications
are flash resident in each terminal.

For embedded systems that rely on dynamic
RAM/disk for main system memory or nonvolatile
backup storage, the 28F010 flas h memory offers a
solid state alternati ve in a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
“eXecute in place” (XIP) m emory hierarc hy for code
and data table reading. Additionally, the flash
memory is more rugged and reliable in harsh
environments where extreme temperatures and
shock can cause disk-based systems to fail.

The need for code updates pervades all phases of
a system's life—from prototyping to system
manufacture to after sale service. The electrical
chip-erasure and reprogramming ability of the
28F010 allows in-circuit alterability; this eliminates
unnecessary handling and less reliable socketed

connections, while adding greater test,
manufacture, and update flexibility.

Material and labor costs associated with code
changes increases at higher levels of system
integration—the most costly being code updates
after sale. Code “bugs,” or the desire to augment
system functionality, prompt after sale code
updates. Field revisions to EPROM-based code
requires the removal of EPROM components or
entire boards. With the 28F010, code updates are
implemented locally via an edge connector, or
remotely over a communcation link.

For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminat es the
need for battery backup. The concern for battery
failure no longer exists, an important consi deration
for portable equipment and medical instruments,
both requiring continuous performanc e. In addition,
flash memory offers a considerable cost advantage
over static RAM.

Flash memory's electrical chip erasure, byte
programmability and complete nonvolatility fit well
with data accumulation and recording needs.
Electrical chip-eras ure gives the designer a “blank
slate” in which to log or record dat a. Data can be
periodically off-loaded for analysis and the flash
memory erased producing a new “blank slate.”

A high degree of on-chip feature integration
simplifies memory -to-processor interfacing. Fi gure 3
depicts two 28F010s tied to the 80C186 system
bus. The 28F010's architect ure minimizes interface
circuitry needed for complete in-circuit updates of
memory contents.

The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 m m thick ness. TSOP i s
particularly suited for portable equipment and
applications requiring large amounts of flash
memory.

With cost-effective in-system reprogramming,
extended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straightforward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.

5

28F010 E

Figure 1. 28F010 Block Diagram

Table 1. Pin Description

Symbol Type Name and Function

A0–A

16

INPUT ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a write cycle.

DQ0–DQ7INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs

data during memory read cycles. The data pins are active high and float to
tri-state off when the chip is deselected or the outputs are disabled. Data is
internally latched during a write cycle

CE# INPUT CHIP ENABLE: Activates the device's control logic, input buffers, decoders

and sense amplifiers. CE# is active low; CE# high deselects the memory
device and reduces power consumption to standby levels.

OE# INPUT OUTPUT ENABLE: Gates the devices output through the data buffers

during a read cycle. OE# is active low.

WE# INPUT WRITE ENABLE: Controls writes to the control register and the array. Write

enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE# pulse.

Note: With V

≤ 6.5 V, memory contents cannot be altered.

PP

6

290207-1

E 28F010

Table 1. Pin Description (Continued)

Symbol Type Name and Function

V

PP

V

CC

V

SS

NC NO INTERNAL CONNECTION to device. Pin may be driven or left floating.

ERASE/PROGRAM POWER SUPPLY for writing the command register,

erasing the entire array, or programming bytes in the array.

DEVICE POWER SUPPLY (5 V ±10%)
GROUND

Figure 2. 28F010 Pin Configurations

7

28F010 E

Figure 3. 28F010 in a 80C186 System

2.0 PRINCIPLES OF OPERATION

Flash memory augments EPROM func tionality with
in-circuit electric al erasure and reprogramm ing. The
28F010 introduces a command regist er to manage
this new functionality. The c ommand regis ter allows
for: 100% TTL-level control inputs; fixed power
supplies during erasure and programming; and
maximum EPROM compatibility.

In the absence of high volt age on the V
28F010 is a read-only memory. Manipulation of the
external memory control pins yields the standard
EPROM read, standby, output disable, and
intelligent identifier operations.

The same EPROM read, standby, and output
disable operations are available when high voltage
is applied to the V
on V

enables erasure and programming of the

PP

pin. In addition, high volt age

PP

device. All functions associated with altering
memory contents—intelligent identifier, erase,

erase verify, program, and program verify—are
accessed via the command register.

8

pin, the

PP

290207-4

Commands are written to the register using
standard microprocessor write timings. Register
contents serve as input to an i nternal s tat e machi ne
which controls the erase and programm ing c irc uit ry.
Write cycles also internally latch addresses and
data needed for programming or erase operations .
With the appropriate command written to the
register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output data for erase and program
verification.

2.1 Integrated Stop Timer

Successive command write cycles define the
durations of program and erase operations;
specifically, the program or erase time durations are
normally terminated by associated Program or
Erase Verify commands. An integrated stop timer
provides simplified timing control over these
operations; thus eliminati ng the need for maximum
program/erase timing specifications. Programming
and erase pulse durations are minimums only.
When the stop timer terminat es a program or erase
operation, the device enters an inactive state and
remains inactive until receiving the appropriate
Verify or Reset command.

E 28F010

Table 2. 28F010 Bus Operations

Mode V

Read V
Output Disable V

READ-ONLY Standby V

Intelligent Identifier (Mfr)

(2)

Intelligent Identifier (Device)
Read V

READ/WRITE Output Disable V

(5)

Standby
Write V

NOTES:

1. Refer to

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other

3. V

4. Read operations with V

5. With V

6. Refer to Table 3 for valid data-in during a write operation.

7. X can be V

DC Characteristics

addresses low.

is the intelligent identifier high voltage. Refer to

ID

at high voltage, the standby current equals ICC + IPP (standby).

PP

or VIH.

IL

. When VPP = V

= V

may access array data or the intelligent identifier codes.

PP

PPH

memory contents can be read but not written or erased.

PPL

(1)

PP

PPLA0

PPL

PPL

V

PPLVILVID

(2)

V

PPLVIHVID

PPHA0

PPH

V

PPH

PPHA0

DC Characteristics

A

A9CE# OE# WE# DQ0–DQ

0

A

VILVILVIHData Out

9

XXVILVIHVIHTri-State
XXVIHX X Tri-State

(3)

VILVILVIHData = 89H

(3)

VILVILVIHData = B4H

A

VILVILVIHData Out

9

XXVILVIHVIHTri-State
XXVIHX X Tri-State

A

VILVIHVILData In

9

.

7

(4)

(6)

2.2 Write Protection

The command register is only ac tive when VPP is at
high voltage. Depending upon the application, the
system designer may choose to make the V
power supply switchable—available only when

memory updates are desired. When V

= V

PP

contents of the register default to the Read
command, making the 28F010 a read-only mem ory.
In this mode, the memory contents cannot be
altered.

Or, the system designer may choose to “hardwire”
V

, making the high voltage supply constantly

PP

available. In this case, all command register
functions are inhibited whenev er V
write lockout voltage V

Power-Up/Down Protection

. (See Section 3.4,

LKO

.) The 28F010 is

is below the

CC

designed to accommodate either design practice,
and to encourage optimization of the processor
memory interface.

The two-step program/erase write sequence t o the
command register provides additional software
write protections.

PPL

PP

, the

2.2.1 BUS OPERATIONS

2.2.1.1 Read

The 28F010 has two control functions, both of
which must be logically active, to obtain dat a at t he
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins , independent
of device selection. Refer to the AC read timing
waveforms.

When V

is high (V

PP

), the read operation can be

PPH

used to access array data, to output t he intelligent
identifier codes, and to access data for
program/erase verificati on. When V

is low (V

PP

PPL

the read operation can only access the array data.

2.2.1.2 Output Disable

With OE# at a logic-high level (V

), output from the

IH

device is disabled. Output pins are placed i n a high­impedance state.

),

9

28F010 E

2.2.1.3 Standby

With CE# at a logic-high level, the standby

operation disables most of the 28F010’s circuitry
and substantially reduces device power
consumption. The outputs are placed in a high­impedance state, independent of the OE# signal. I f
the 28F010 is deselected during erasure,
programming, or program/erase verification, the
device draws active current until the operation is
terminated.

2.2.1.4 Intelligent Identifier Operation

The intelligent identifier operation outputs the
manufacturer code (89H) and device code (B4H).
Programming equipment automatical ly matches t he
device with its proper erase and programming
algorithms.

With CE# and OE# at a logic low lev el, raisi ng A
high voltage V

(see

DC Characteristics

ID

to

9

) activates
the operation. Data read from locations 0000H and
0001H represent the manufacturer's code and the
device code, respectively.

The manufacturer and device codes can also be
read via the command register, for ins tances where
the 28F010 is erased and reprogrammed in the
target system. Following a write of 90H to the
command register, a read from address location
0000H outputs the manufacturer code (89H). A
read from address 0001H outputs the dev ice code
(B4H).

2.2.1.5 Write

Device erasure and programming are acc ompli shed
via the command register, when high voltage is
applied to the V

pin. The contents of the register

PP

serve as input to the internal state machine. The
state machine outputs dictate the function of the
device.

The command register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with
address and data information needed to execute
the command.

The command register is writ ten by bringing WE# to
a logic-low level (V

), while CE# is low. Addresses

IL

are latched on the falling edge of WE#, while data is
latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.

Refer to

Only Operations

AC Characteristics—Write/Erase/Program

and the erase/programming

waveforms for specific timing parameters.

2.2.2 COMMAND DEFINITIONS

When low voltage is applied to the V

pin, the

PP

contents of the command register default to 00H,
enabling read-only operations.

Placing high voltage on the V

pin enables

PP

read/write operations. Device operations are
selected by writing specific data patterns into the
command register. Table 3 defines these 28F010
register commands.

10

E 28F010

Address

Table 3. Command Definitions

First Bus Cycle Second Bus Cycle

Bus

Command

Read Memory 1 Write X 00H
Read Intelligent

Identifier Codes
Set-Up

Erase/Erase
Erase Verify
Set-Up Program/

Program
Program Verify
Reset

NOTES:

1. Bus operations are defined in Table 2.

2. IA = Identifier address: 00H for manufacturer code, 01H for device code.

EA = Erase Address: Address of memory location to be read during erase verify.
PA = Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.

3. ID = Identifier Data: Data read from location IA during device identification (Mfr = 89H, Device = B4H).

EVD = Erase Verify Data: Data read from location EA during erase verify.
PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of WE#.
PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.

4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.

5. Figure 5 illustrates the

6. Figure 4 illustrates the

7. The second bus cycle must be followed by the desired command register write.

(5)

(5)

(6)

(7)

Cycles

Req’d Operation

(4)

(6)

3 Write IA 90H Read IA ID

2 Write X 20H Write X 20H

2 Write EA A0H Read X EVD
2 Write X 40H Write PA PD

2 Write X C0H Read X PVD
2 Write X FFH Write X FFH

28F010 Quick-Erase Algorithm
28F010 Quick-Pulse Programming Algorithm

(1)

Address

flowchart.

(2)

(3)

Data

flowchart.

Operation

(1)

(2)

Data

(3)

2.2.2.1 Read Command

While V
memory contents can be accessed via the Read
command. The read operation is initiat ed by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register
contents are altered.

The default contents of the register upon V
power-up is 00H. This default value ens ures that no
spurious alteration of memory contents occurs
during the V
supply is hardwired to the 28F010, the device
powers-up and remains enabled for reads until the
command register contents are changed. Refer to
the
waveforms for specific timing parameters.

is high, for erasure and programming,

PP

power transition. Where the V

PP

AC Characteristic s—Read-Only Operati ons

PP

PP

and

2.2.2.2 Intelligent Identifier Command

Flash memories are intended for us e in applic ations
where the local CPU alters memory contents. As
such, manufacturer and device codes must be
accessible while the device resides in the target
system. PROM programmers typically access
signature codes by raising A
However, multiplexing high voltage onto address
lines is not a desired system design practice.

The 28F010 contains an intelligent identifier
operation to supplement traditional PROM­programming methodology. The operation is
initiated by writing 90H int o the command register.
Following the command Write, a read cycle from
address 0000H retrieves the manuf acturer code of
89H. A read cycle from address 0001H returns the
device code of B4H. To term inate the operation, it

to a high voltage.

9

11

28F010 E

is necessary to write another valid command into
the register.

2.2.2.3 Set-Up Erase/Erase Commands

Set-Up Erase is a command-only operation that
stages the device for electrical erasure of all bytes
in the array. The set-up erase operation is
performed by writing 20H to the command register.

To commence chip-erasure, the Erase command
(20H) must again be written to the register. The
erase operation begins with the ris ing edge of the
WE# pulse and terminates with the rising edge of
the next WE# pulse (i.e., Erase Verify command).

This two-step sequence of set-up followed by
execution ensures that memory contents are not
accidentally erased. Also, chip-erasure can only
occur when high voltage is applied to the pin. In the
absence of this high volt age, memory contents are
protected against erasure. Refer to

AC

Characteristics—Write/Erase/Program Only Oper-

ations

and waveforms for specific timing

parameters.

2.2.2.4 Erase Verify Command

The Erase command erases all bytes of t he array in
parallel. After each erase operat ion, all bytes mus t
be verified. The erase verify operati on is ini ti ated by
writing A0H into the command register. The
address for the byte to be v erified must be s upplied
as it is latched on the falling edge of t he WE # pulse.
The register write terminates the erase operation
with the rising edge of its WE# pulse.

The 28F010 applies an internally-generat ed margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicat es that al l bits in the by te
are erased.

The Erase Verify command must be writt en to the
command register prior to each byt e verification to
latch its address. The process continues for each
byte in the array until a byt e does not return FFH
data, or the last address is accessed.

In the case where the data read is not FFH, another
erase operation is performed. (Refer Section

2.2.2.3,
Verification then resumes from the address of the
last-verified byte. Once all bytes in the array have
been verified, the erase step is complete. The
device can be programmed. At this

Set-Up Erase/Erase Commands.

point, the verify operation is termi nated by writing a
valid command (e.g., Program Set-Up) to the
command register. Figure 5, the

Erase Algorithm

commands and bus operations are combined to
perform electrical erasure of the 28F010. Refer to

flowchart, illustrates how

28F010 Quick-

AC Characteristics—Write/Erase/Program Only
Operations

parameters.

2.2.2.5 Set-Up Program/Program

Set-up program is a command-onl y operation that
stages the device for byte programming. Writing
40H into the command register performs the set-up
operation.

Once the program set-up operation is performed,
the next WE# pulse causes a transit ion to an activ e
programming operation. Addresses are internally
latched on the falling edge of the WE# pulse. Data
is internally latched on the risi ng edge of the WE#
pulse. The rising edge of WE# also begins the
programming operation. The programming
operation terminates with the next rising edge of
WE#, used to write the Program V erify command.
Refer to

Only Operations

parameters.

2.2.2.6 Program Verify Command

The 28F010 is programmed on a byte-by-byte
basis. Byte programmi ng may occ ur sequenti ally or
at random. Following each programming operat ion,
the byte just programmed must be verified.

The program verify operation is i nitiated by writing
C0H into the command register. The regist er write
terminates the programming operation with the
rising edge of its WE# pulse. The program verify
operation stages the device for verification of the
byte last programmed. No new addres s information
is latched.

The 28F010 applies an internally-generat ed margin
voltage to the byte. A microprocessor read cycle
outputs the data. A suc ces sf ul compari son between
the programmed byte and true data means that the
byte is successfully programmed. Programming

)

then proceeds to the next desired byte location.
Figure 5, the

Algorithm

combined with bus operations to perform byte

and waveforms for specific timing

Commands

AC Characteristics—Write/Erase/Program

and Waveforms for spec ific timi ng

28F010 Quick-Pulse Programming

flowchart, illustrates how commands are

12

E 28F010

programming. Refer to

Write/Erase/Program Only Operations

waveforms for specific timing parameters.

2.2.2.7 Reset Command

A Reset command is prov ided as a means to saf ely
abort the Erase or Program command sequences.
Following either Set-Up command (Erase or
Program) with two consecutive writes of FFH will
safely abort the operation. Memory cont ents will not
be altered. A valid command must t hen be written
to place the device in the desired state.

2.2.3 EXTENDED ERASE/PROGRAM

CYCLING

EEPROM cycling failures have always concerned
users. The high electrical field required by thin
oxide EEPROMs for tunneling can literally tear
apart the oxide at defect regions. To combat this,
some suppliers have implemented redundancy
schemes, reducing cycling failures to insignificant
levels. However, redundancy requires that c ell size
be doubled—an expensive solution.

Intel has designed extended c ycling capability into
its ETOX flash memory technology. Resulting
improvements in cycling reliability come without
increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge
carrying ability ten-fold. Second, the oxide area per
cell subjected to the t unneling electric field is one­tenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally,
the peak electric field during erasure is
approximately 2 MV/cm lower than EEPROM. The
lower electric field greatly reduces ox ide stress and
the probability of failure.

The 28F010 is capable or 100,000 program/erase
cycles. The device is programmed and erased
using Intel's quick-pulse programming and quick­erase algorithms. Intel 's algorithmic approach uses
a series of operations (pulses), along with byte
verification, to completely and reliably erase and
program the device.

AC Characteristics—

and

2.2.4 QUICK-PULSE PROGRAMMING

The quick-pulse programming algorithm uses
programming operations of 10 µs duration. Each
operation is followed by a byte verification to
determine when the addressed byte has been
successfully programmed. The algorithm allows for
up to 25 programming operations per byte, although
most bytes verif y on the first or second operati on.
The entire sequence of programming and byte
verification is performed with V
Figure 4 illustrates the

Programming Algorithm

2.2.5 QUICK-ERASE ALGORITHM

Intel's quick-erase al gorithm yields fast and reliable
electrical erasure of memory contents. The
algorithm employs a closed-loop flow, s imilar to the
quick-pulse programming algorithm, to simul­taneously remove charge from all bits in the array.

Erasure begins with a read of memory contents.
The 28F010 is erased when shipped from the
factory. Reading FFH data from the device would
immediately be followed by device programming.

For devices being erased and reprogrammed,
uniform and reliable erasure is ensured by first
programming all bits in the device to their c harged
state (Data = 00H). This is accom plished, usi ng the
quick-pulse programming algorithm, in approxi­mately two seconds.

Erase execution then continues with an ini tial erase
operation. Erase verific ation (data = FFH) begins at
address 0000H and continues through the array to
the last address, or until data other than FFH is
encountered. With each erase operation, an
increasing number of bytes verify to the erased
state. Erase effici ency may be improved by st oring
the address of the last byte verified in a register.
Following the next erase operation, verification
starts at that stored address location. Erasure
typically occurs in one second. Figure 5 illustrates
the

ALGORITHM

PP

28F010 Quick-Pulse

flowchart.

28F010 Quick-Erase Algorithm

at high voltage.

flowchart.

13

28F010 E

Increment

Address

Programming

Time Out 10 µs

N

Write Read Cmd

Start

Apply V

PPH

PLSCNT = 0

Write Set-Up

Program Cmd

Write Program

Cmd (A/D)

Write Program

Verify Cmd

Time Out 6 µs

Read Data

from Device

Verify

Data

Y

Last

Address?

Y

Apply V

PPL

Bus

(4)

(1)

Operation

Standby

Command Comments

Wait for VPP Ramp to

(1)

V

PPH

Initialize Pulse-Count

Write

Set-Up

Program

Data = 40H

Write Program Valid Address/Data

Standby

Write

Program

Verify

Stand-by t

Read

Duration of Program
Operation (t

Data = C0H; Stops

(2)

Program Operations

WHGL

Read Byte to Verify
Programming

WHWH1

)

(3)

N

N

Inc

PLSCNT

=25?

Standby

Compare Data Output to
Data Expected

Y

Write Read

Standby Wait for VPP Ramp to V

(1)

(1)

Apply V

PPL

Data = 00H, Resets the
Register for Read
Operations

(1)

PPL

Programming

Completed

Program

Error

NOTES:

1. See

DC Characteristics

for the value of V

PPH

and V

PPL

.

2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the

register is written with the Read command.

3. Refer to

Principles of Operation

.

4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device.

Figure 4. 28F010 Quick-Pulse Programming Algorithm

14

0207_04

E 28F010

Increment Addr

Start Erasure

Y

Data = 00H?

Program All

Bytes to 00H

Apply V

ADDR = 00H

PLSCNT = 0

Write Erase

Set-Up Cmd

Write Erase Cmd

Time Out 10 ms

Write Erase

Verify Cmd

Time Out 6 µs

Read Data

from Device

Data = FFH?

N

Last Address?

Write Read Cmd

Apply V

PPH

PPL

(4)

N

(1)

N

N

Y

Y

(1)

Inc

PLSCNT =

1000?

Apply V

Y

(1)

PPL

Bus

Operation

Standby Wait for VPP Ramp to V

Write Data = 20H

Write Data = 20H

Stand-by

Write

Standby t

Read Read Byte to Verify Erasure

Standby

Write

Standby Wait for VPP Ramp to V

Command

Set-Up

Erase

Erase

(2)

Erase

Verify

Read

Comments

Entire Memory Must = 00H
Before Erasure

Use Quick-Pulse
Programming Algorithm
(Figure 4)

Initialize Addresses and
Pulse-Count

Duration of Erase Operation

)

(t

WHWH2

Addr = Byte to Verify;
Data = A0H; Stops Erase

(3)

Operation

WHGL

Compare Output to FFH
Increment Pulse-Count

Data = 00H, Resets the
Register for Read Operations

(1)

PPH

(1)

PPL

Erasure

Completed

Erase Error

NOTES:

1. See

DC Characteristics

for the value of V

PPH

and V

PPL

.

2. Erase Verify is performed only after chip-erasure. A final read/compare may be performed (optional) after the register is

written with the Read command.

3. Refer to

Principles of Operation

.

4. CAUTION: The algorithm must be followed to ensure proper and reliable operation of the device.

Figure 5. 28F010 Quick-Erase Algorithm

0207_05

15

28F010 E

3.0 DESIGN CONSIDERATIONS

3.1 Two-Line Output Control

Flash memories are often used in larger memory
arrays. Intel provides two read control inputs to
accommodate multiple memory connections. Two­line control provides for:

a. the lowest possible memory power dissipation

and,

b. complete assurance that output bus contention

will not occur.

To efficiently use these two control inputs, an
address decoder output should drive chip-enable,
while the system’s read signal controls all flash
memories and other parallel memories. This
assures that only enabled memory devices have
active outputs, while deselected devices maintain
the low power standby condition.

3.2 Power Supply Decoupling

Flash memory power-switching characteristics
require careful device decoupling. System
designers are interested in three supply current
(I

) issues—standby, ac tive, and transient current

CC

peaks produced by falling and rising edges of chip­enable. The capacitive and inductive loads on the
device outputs determine the m agnitudes of these
peaks.

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 µF ceramic
capacitor connected between V
between V

and VSS.

PP

Place the high-frequency, low-inherent inductance
capacitors as close as possible to the devices.
Also, for every eight devices, a 4.7 µF electrolytic
capacitor should be placed at the array's power
supply connection, bet ween V
capacitor will overcome voltage slumps c aused by
printed circuit board trace inductance, and will
supply charge to the smaller capacitors as needed.

and VSS, and

CC

and VSS. The bulk

CC

3.3 VPP Trace on Printed Circuit Boards

Programming flash memories , while they reside in
the target system, requires that the printed circuit
board designer pay attention to the V
supply trace. The V

pin supplies the memory c ell

PP

power

PP

current for programming. Use similar trace widths
and layout considerations gi ven t he V
Adequate V
decrease V

supply traces and decoupling will

PP

voltage spikes and overshoots.

PP

power bus.

CC

3.4 Power-Up/Down Protection

The 28F010 is designed to offer protec tion against
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is
indifferent as to which power supply, V

or VCC,

PP

powers up first. Power supply sequencing is not
required. Internal circuitry in the 28F010 ensures
that the command register i s reset to the read mode
on power-up.

A system designer must guard against active writes
for V

voltages above V

CC

when VPP is active.

LKO

Since both WE# and CE# must be low for a
command write, driving either to V

will inhibit

IH

writes. The control regist er architect ure provides an
added level of protection si nce al terati on of m emory
contents only occurs after successful completion of
the two-step command sequences.

3.5 28F010 Power Dissipation

When designing portable systems, designers must
consider battery power consum pti on not onl y during
device operation, but also f or data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain
code or data when the system is off. Table 4
illustrates the power dissipated when updat ing the
28F010.

16

E 28F010

Table 4. 28F010 Typical Update Power Dissipation

(4)

Operation Notes Power Dissipation (Watt-Seconds)

Array Program/Program Verify 1 0.171
Array Erase/Erase Verify 2 0.136
One Complete Cycle 3 0.478

NOTES:

1. Formula to calculate typical Program/Program Verify Power = [V

+ t

× I

WHGL

2. Formula to calculate typical Erase/Erase Verify Power = [V
Bytes)] + [V

3. One Complete Cycle = Array Preprogram + Array Erase + Program.

4. “Typicals” are not guaranteed, but based on a limited number of samples from production lots.

typical)] + [VCC × # Bytes × typical # Prog Pulses (t

PP4

(I

CC

typical × t

CC3

ERASE

typical + I

typical × t

CC5

× # Bytes × typical # Prog Pulses (t

PP

× I

typical + t

CC2

ERASE

typical + I

(V

PP
WHGL

WHWH1

typical × t

PP3

× # Bytes)].

WHGL

× I

PP5

WHWH1

typical].

CC4

typical × t

WHGL

× I

× #

PP2

typical

17

28F010 E

4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings*

Operating Temperature

During Read ...............................0 °C to +70 °C

During Erase/Program................0 °C to +70 °C

Operating Temperature

During Read...........................–40 °C to +85 °C

During Erase/Program............–40 °C to +85 °C

Temperature Under Bias............–10 °C to +80 °C

Temperature Under Bias............–50 °C to +95 °C

Storage Temperature.................. –65 °C to +125 °C

Voltage on Any Pin with

Respect to Ground..................–2.0 V to +7.0 V

Voltage on Pin A9 with

Respect to Ground.............–2.0 V to +13.5 V

VPP Supply Voltage with
Respect to Ground

During Erase/Program........–2.0 V to +14.0 V

VCC Supply Voltage with

Respect to Ground..................–2.0 V to +7.0 V

Output Short Circuit Current.....................100 mA

(3, 4)

(3, 4)

NOTICE: This is a production datasheet. The specifications
are subject to change without notice.

*WARNING: Stressing the device beyond the

Maximum Ratings

are stress ratings only. Operation beyond the

Conditions

(1)

beyond the

(1)

reliability.

NOTES:

(2)

1. Operating Temperature is for commercial product as

(2)
(1)
(2)

(3)

(3)
(5)

defined by this specification.

2. Operating Temperature is for extended temperature
products as defined by this specification.

3. Minimum DC input voltage is –0.5 V. During transitions,

inputs may undershoot to –2.0 V for periods less than
20 ns. Maximum DC voltage on output pins is V

0.5 V, which may overshoot to V
less than 20 ns.

4. Maximum DC voltage on A
+14.0 V for periods less than 20 ns.

5. Output shorted for no more than one second. No more
than one output shorted at a time.

6. See

AC Testing Load Circuit

characteristics.

may cause permanent damage. These

is not recommended and extended exposure

Operating Conditions

AC Testing Input/Output Waveform

may affect device

+ 2.0 V for periods

CC

or VPP may overshoot to

9

(Figure 7) for testing

(Figure 6) and

4.2 Operating Conditions

Limits

Symbol Parameter Min Max Unit

T

A

T

A

V

CC

V

CC

Operating Temperature

Operating Temperature

V

Supply Voltage (10%)

CC

VCC Supply Voltage (5%)

(1)

(2)

(6)

(7)

070°C

–40 +85 °C

4.50 5.50 V

4.75 5.25 V

Absolute

Operating

+

CC

4.3 Capacitance

TA = 25 °C, f = 1.0 MHz

Limits

Symbol Parameter Notes Min Max Unit Conditions

C

IN

C

OUT

NOTE:

1. Sampled, not 100% tested.

18

Address/Control Capacitance 1 8 pF VIN = 0 V
Output Capacitance 1 12 pF V

OUT

= 0 V

E 28F010

PPH

PPH

PPH

PPH

PPH

PPH

4.4 DC Characteristics—TTL/NMOS Compatible—Commercial Products

Limits

Symbol Parameter Notes Min Typ

I

LI

I

LO

I

CCS

I

CC1

I

CC2

I

CC3

I

CC4

Input Leakage Current 1 ±1.0 µA VCC = VCC Max

Output Leakage Current 1 ±10 µA VCC = VCC Max

VCC Standby Current 1 0.3 1.0 mA VCC = VCC Max

VCC Active Read Current 1 10 30 mA VCC = VCC Max, CE# = V

VCC Programming Current 1, 2 1.0 10 mA Programming in Progress
VCC Erase Current 1, 2 5.0 15 mA Erasure in Progress
VCC Program Verify

1, 2 5.0 15 mA VPP = V

Current

I

I
I

CC5

PPS

PP1

VCC Erase Verify Current 1, 2 5.0 15 mA VPP = V

VPP Leakage Current 1 ±10 µA VPP ≤ V
VPP Read Current

1 90 200 µA VPP > V

or Standby Current

I

I

I

PP2

PP3

PP4

VPP Programming Current 1, 2 8.0 30 mA VPP = V

VPP Erase Current 1, 2 6.0 30 mA VPP = V

VPP Program Verify

1, 2 2.0 5.0 mA VPP = V

Current

I

V
V

V

V

V

PP5

VPP Erase Verify Current 1, 2 2.0 5.0 mA VPP = V

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 2.0 V

IH

Output Low Voltage 0.45 V VCC = VCC Min

OL

Output High Voltage 2.4 V VCC = VCC Min

OH1

A9 Intelligent Identifier

ID

11.50 13.00 V

Voltage

(3)

Max Unit Test Conditions

V

= VCC or V

IN

V

= VCC or V

OUT

CE# = V

IH

f = 6 MHz, I

Program Verify in Progress

Erase Verify in Progress

CC

CC

±10.0 VPP ≤ V

CC

Programming in Progress

Erasure in Progress

Program Verify in Progress

Erase Verify in Progress

V

CC

+ 0.5

I

= 5.8 mA

OL

I

= –2.5 mA

OH

OUT

SS

SS

IL

= 0 mA

19

28F010 E

CC

PPH

PPH

4.4 DC Characteristics—TTL/NMOS Compatible—Commercial Products

(Continued)

Limits

Symbol Parameter Notes Min Typ

I

ID

A9 Intelligent Identifier

1, 2 90 200 µA A9 = V

Current

V

PPL

V

during Read-Only

PP

0.00 6.5 V NOTE: Erase/Program are

Operations

V

VPP during Read/Write

PPH

11.40 12.60 V

Operations

V

LKO

V

Erase/Write Lock

2.5 V

Voltage

NOTES:

Sampled, not 100% tested.

1. All currents are in RMS unless otherwise noted. Typical values at V

valid for all product versions (packages and speeds).

2. Not 100% tested: characterization data available.

3. “Typicals” are not guaranteed, but based on a limited number of samples from production lots.

(3)

Max Unit Test Conditions

ID

Inhibited when V

= 5.0 V, VPP = 12.0 V, T = 25 °C. These currents are

CC

PP

4.5 DC Characteristics—CMOS Compatible—Commercial Products

Limits

Symbol Parameter Notes Min Typ

I

LI

I

LO

I

CCS

I

CC1

I

CC2

I

CC3

I

CC4

Input Leakage Current 1 ±1.0 µA VCC = VCC Max

Output Leakage Current 1 ±10 µA VCC = VCC Max

V

Standby Current 1 50 100 µA VCC = VCC Max

CC

VCC Active Read Current 1 10 30 mA VCC = VCC Max, CE# = V

VCC Programming Current 1, 2 1.0 10 mA Programming in Progress
VCC Erase Current 1, 2 5.0 15 mA Erasure in Progress
VCC Program Verify

1, 2 5.0 15 mA V

Current

I

I

CC5

PPS

VCC Erase Verify Current 1, 2 5.0 15 mA V

VPP Leakage Current 1 ±10 µA VPP ≤ V

(3)

Max Unit Test Conditions

V

= VCC or V

IN

V

= VCC or V

OUT

CE# = V

CC

f = 6 MHz, I

= V

PP

Program Verify in Progress

= V

PP

Erase Verify in Progress

CC

SS

±0.2 V

= 0 mA

OUT

SS

= V

PPL

IL

20

E 28F010

PPH

PPH

PPH

PPH

CC

4.5 DC Characteristics—CMOS Compatible—Commercial Products (Continued)

Limits

Symbol Parameter Notes Min Typ

I

PP1

VPP Read Current, ID

1 90 200 µA V
Current or Standby
Current

I

I

I

PP2

PP3

PP4

V

Programming Current 1, 2 8.0 30 mA VPP > = V

PP

VPP Erase Current 1, 2 6.0 30 mA VPP = V

VPP Program Verify

1, 2 2.0 5.0 mA VPP = V

Current

I

V
V

V

V

V

PP5

VPP Erase Verify Current 1, 2 2.0 5.0 mA VPP = V

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 0.7

IH

Output Low Voltage 0.45 V VCC = VCC Min

OL

Output High Voltage 0.85

OH1

OH2

V

CC

V

CC

V

CC

– 0.4

V

A9 Intelligent Identifier

ID

11.50 13.00 V

Voltage

I

ID

A9 Intelligent Identifier

1, 2 90 200 µA A9 = V

Current

V

PPL

V

during Read-Only

PP

0.00 6.5 V NOTE: Erase/Programs are

Operations

V

VPP during Read/Write

PPH

11.40 12.60 V

Operations

V

LKO

V

Erase/Write Lock

2.5 V

Voltage

NOTES:

Refer to Section 4.4.

(3)

Max Unit Test Conditions

> V

PP

CC

±10 VPP ≤ V

CC

Programming in Progress

Erasure in Progress

Program Verify in Progress

Erase Verify in Progress

V

CC

V

+ 0.5

I

= 5.8 mA

OL

VVCC = VCC Min

I

= –2.5 mA

OH

= VCC Min

V

CC

I

= –100 µA

OH

ID

Inhibited when V

PP

= V

PPL

21

28F010 E

CC

PPH

PPH

PPH

PPH

PPH

PPH

4.6 DC Characteristics—TTL/NMOS Compatible—Extended Temperature Products

Limits

Symbol Parameter Notes Min Typ

I

LI

I

LO

I

CCS

I

CC1

I

CC2

I

CC3

I

CC4

Input Leakage Current 1 ±1.0 µA VCC = VCC Max

Output Leakage Current 1 ±10 µA VCC = VCC Max

VCC Standby Current 1 0.3 1.0 mA VCC = VCC Max

VCC Active Read Current 1 10 30 mA VCC = VCC Max, CE# = V

V

Programming Current 1, 2 1.0 30 mA Programming in Progress

CC

VCC Erase Current 1, 2 5.0 30 mA Erasure in Progress
V

Program Verify

1, 2 5.0 30 mA VPP = V

Current

I

I
I

CC5

PPS

PP1

V

Erase Verify Current 1, 2 5.0 30 mA V

CC

V

Leakage Current 1 ±10 µA VPP ≤ V

PP

VPP Read Current or

1 90 200 µA VPP > V

Standby Current

I

I

I

PP2

PP3

PP4

V

Programming Current 1, 2 8.0 30 mA VPP = V

PP

VPP Erase Current 1, 2 6.0 30 mA VPP = V

VPP Program Verify

1, 2 2.0 5.0 mA VPP = V

Current

I

V
V

V

V

V

PP5

VPP Erase Verify Current 1, 2 2.0 5.0 mA VPP = V

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 2.0 V

IH

Output Low Voltage 0.45 V VCC = VCC Min

OL

Output High Voltage 2.4 V VCC = VCC Min

OH1

A9 Intelligent Identifier

ID

11.50 13.00 V

Voltage

(3)

Max Unit Test Conditions

V

= VCC or V

IN

V

= VCC or V

OUT

CE# = V

IH

f = 6 MHz, I

Program Verify in Progress

= V

PP

Erase Verify in Progress

CC

CC

±10.0 VPP ≤ V

CC

Programming in Progress

Erasure in Progress

Program Verify in Progress

Erase Verify in Progress

V

CC

+ 0.5

I

= 5.8 mA

OL

I

= –2.5 mA

OH

OUT

SS

SS

= 0 mA

IL

22

E 28F010

CC

PPH

PPH

4.6 DC Characteristics—TTL/NMOS Compatible—Extended Temperature
Products (Continued)

Limits

Symbol Parameter Notes Min Typ

I

ID

A9 Intelligent Identifier

1, 2 90 500 µA A9 = V

(3)

Max Unit Test Conditions

ID

Current

V

V

V

PPL

PP

Operations
VPP during Read/Write

PPH

during Read-Only

0.00 6.5 V NOTE: Erase/Program are
Inhibited when V

PP

= V

11.40 12.60 V

PPL

Operations

V

LKO

V

Erase/Write Lock

2.5 V

Voltage

NOTES:

Refer to Section 4.4.

4.7 DC Characteristics—CMOS Compatible—Extended Temperature Products

Limits

Symbol Parameter Notes Min Typ

I

LI

I

LO

I

CCS

I

CC1

I

CC2

I

CC3

I

CC4

Input Leakage Current 1 ±1.0 µA VCC = VCC Max

Output Leakage Current 1 ±10 µA VCC = VCC Max

VCC Standby Current 1 50 100 µA VCC = VCC Max

VCC Active Read Current 1 10 30 mA VCC = VCC Max, CE# = V

VCC Programming Current 1, 2 1.0 10 mA Programming in Progress
VCC Erase Current 1, 2 5.0 30 mA Erasure in Progress
VCC Program Verify

1, 2 5.0 30 mA VPP = V

Current

I

I
I

CC5

PPS

PP1

VCC Erase Verify Current 1, 2 5.0 30 mA VPP = V

VPP Leakage Current 1 ±10 µA VPP ≤ V
VPP Read Current, ID

1 90 200 µA V
Current or Standby
Current

(3)

Max Unit Test Conditions

V

= VCC or V

IN

V

= VCC or V

OUT

CE# = V

CC

f = 10 MHz, I

Program Verify in Progress

Erase Verify in Progress

CC

> V

PP

CC

±10 VPP ≤ V

CC

SS

±0.2 V

OUT

SS

IL

= 0 mA

23

28F010 E

PPH

PPH

PPH

PPH

4.7 DC Characteristics—CMOS Compatible—Extended Temperature Products

(Continued)

Limits

Symbol Parameter Notes Min Typ

I

I

I

PP2

PP3

PP4

VPP Programming Current 1, 2 8.0 30 mA VPP = V

VPP Erase Current 1, 2 6.0 30 mA VPP = V

VPP Program Verify

1, 2 2.0 5.0 mA VPP = V

Current

I

V

V

V

V

V

PP5

VPP Erase Verify Current 1, 2 2.0 5.0 mA VPP = V

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 0.7

IH

Output Low Voltage 0.45 V VCC = VCC Min

OL

Output High Voltage 0.85

OH1

OH2

V

CC

V

CC

V

CC

– 0.4

V

A9 Intelligent Identifier

ID

11.50 13.00 V

Voltage

I

ID

A9 Intelligent Identifier

1, 2 90 500 µA A9 = V

Current

V

VPP during Read-Only

PPL

0.00 6.5 V NOTE: Erase/Programs are

Operations

V

VPP during Read/Write

PPH

11.40 12.60 V

Operations

V

VCC Erase/Write Lock

LKO

2.5 V

Voltage

NOTE:

Refer to Section 4.4.

(3)

Max Unit Test Conditions

Programming in Progress

Erasure in Progress

Program Verify in Progress

Erase Verify in Progress

VCC +

V

0.5

I

= 5.8 mA

OL

VVCC = VCC Min

I

= –2.5 mA

OH

= VCC Min

V

CC

I

= –100 µA

OH

ID

Inhibited when V

PP

= V

PPL

24

E 28F010

2.4

0.45

AC test inputs are driven at VOH (2.4 V

and VOL (0.45 V
VIH (2.0 V
and VIL. Input rise and fall times (10% to 90%) <10 ns.

2.0

0.8

) for a Logic “0”. Input timing begins at

TTL

) and VIL (0.8 V

TTL

). Output timing ends at V

TTL

TTL

Figure 6. Testing Input/Output Waveform

NOTE:

1. Testing characteristics for 28F010-90, 28F010-120, and
28F010-150.

2.0
OutputTest PointsInput

0.8

) for a Logic “1”

0207_06

(1)

1N914

= 3.3 k

L

= 100 pF

L

Ω

Out

R

IH

Device

Under Test

CL Includes Jig Capacitance

C

Figure 7. AC Testing Load Circuit

4.8 AC Characteristics—Read-Only Operations—Commercial and Extended

Temperature Products

1.3V

Versions 28F010-90

(1)

28F010-120

Symbol Characteristic Notes Min Max Min Max Min Max Unit

t

AVAV/tRC

t

ELQV/tCE

t

AVQV

t

GLQV/tOE

t

ELQX/tLZ

t

EHQZ

Read Cycle Time 90 120 150 ns
CE# Access Time 90 120 150 ns

/tACC Address Access Time 90 120 150 ns

OE# Access Time 35 50 55 ns
CE# to Low Z 2, 3 0 0 0 ns
Chip Disable to Output in

2 455555ns

High Z

t

GLQX/tOLZ

t

GHQZ/tDF

OE# to Output in Low Z 2, 3 0 0 0 ns
Output Disable to Output in

2 303035ns

High Z

tOHOutput Hold from Address,

2, 4 0 0 0 ns

CE#, or OE# Change

t

WHGL

Write Recovery Time before

666µs

Read

NOTES:

1. See AC

2. Sampled, not 100% tested.

3. Guaranteed by design.

4. Whichever occurs first.

Input/Output Waveform

and AC

Testing Load Circuit

for testing characteristics.

(1)

28F010-150

(1)

0207_07

25

28F010 E

290207-9

26

Figure 8. AC Waveforms for Read Operations

E 28F010

4.9 AC Characteristics—Write/Erase/Program Only Operations

(1)

—

Commercial and Extended Temperature Products

Versions 28F010-90

Symbol Characteristic Notes Min Max Min Max Min Max Unit

t

AVAV/tWC

t

AVWL/tAS

t

WLAX/tAH

t

DVWH/tDS

t

WHDX/tDH

t

WHGL

t

GHWL

t

ELWL/tCS

t

WHEH/tCH

t

WLWH/tWP

t

WHWL/tWPH

t

WHWH1

t

WHWH2

t

VPEL

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to

Characteristics for Read-Only Operations

2. See AC

3. Minimum specification for extended temperature product.

4. Guaranteed by design.

5. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum
specification.

Write Cycle Time 90 120 150 ns
Address Set-Up Time 0 0 0 ns
Address Hold Time 40 40 40 ns

355

Data Set-Up Time 40 40 40 ns

55
Data Hold Time 10 10 10 ns
Write Recovery Time before

Read

Read Recovery Time before
Write

Chip Enable Set-Up Time
before Write

Chip Enable Hold Time 0 0 0 ns
Write Pulse Width 40 60 60 ns

Write Pulse Width High 20 20 20 ns
Duration of Programming

Operation
Duration of Erase Operation 5 9.5 9.5 9.5 ms
VPP Set-Up Time to Chip

Enable Low

.

Input/Output Waveform

and AC

Testing Load Circuit

666µs

4000ns

15 15 15 ns

355

5101010µs

4111µs

for testing characteristics.

(2)

28F010-120

(2)

28F010-150

(2)

AC

27

28F010 E

Figure 9. Typical Programming Capability

Figure 10. Typical Program Time at 12 V

28

290207-13

290207-14

290207-15

Figure 11. Typical Erase Capability

290207-16

Figure 12. Typical Erase Time at 12 V

E 28F010

Figure 13. AC Waveforms for Programming Operations

290207-10

29

28F010 E

30

290207-11

Figure 14. AC Waveforms for Erase Operations

E 28F010

4.10 AC Characteristics—Alternative CE#-Controlled Writes

(1)

—

Commercial and Extended Temperature

Versions 28F010-90

Symbol Characteristic Notes Min Max Min Max Min Max Unit

t

AVAV

t

AVEL

t

ELAX

t

DVEH

t

EHDX

t

EHGL

t

GHWL

t

WLEL

t

EHWH

t

ELEH

t

EHEL

t

EHEH1

t

EHEH2

t

VPEL

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to

Characteristics for Read-Only Operations

2. See AC

3. Minimum specification for extended temperature product.

4. Guaranteed by design.

5. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum
specification.

Write Cycle Time 90 120 150 ns
Address Set-Up Time 0 0 0 ns
Address Hold Time 45 55 55 ns

360

Data Set-Up Time 35 45 45 ns

350
Data Hold Time 10 10 10 ns
Write Recovery Time before

Read

Read Recovery Time before
Write

Write Enable Set-Up Time
before Chip Enable

Write Enable Hold Time 0 0 0 ns
Write Pulse Width 45 70 70 ns

Write Pulse Width High 20 20 20 ns
Duration of Programming

Operation
Duration of Erase Operation 5 9.5 9.5 9.5 ms
VPP Set-Up Time to Chip

Enable Low

.

Input/Output Waveform

and AC

Testing Load Circuit

666µs

4000ns

000ns

360

5101010µs

4111µs

(2)

28F010-120

for testing characteristics.

(2)

28F010-150

(2)

AC

31

28F010 E

4.11 Erase and Programming Performance

Parameter Notes Min Typical Max Unit

Chip Erase Time 1, 3, 4 1 10 Sec
Chip Program Time 1, 2, 4 2 12.5 Sec

NOTES:

1. “Typicals” are not guaranteed, but based on samples from production lots. Data taken at 25 °C, 12.0 V V

2. Minimum byte programming time excluding system overhead is 16 µsec (10 µsec program + 6 µsec write recovery), while
maximum is 400 µsec/byte (16 µsec x 25 loops allowed by algorithm). Max chip programming time is specified lower than
the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.

3. Excludes 00H programming prior to erasure.

4. Excludes system level overhead.

.

PP

NOTE:

Alternative CE#-Controlled Write Timings also apply to erase operations.

Figure 15. Alternate AC Waveforms for Programming Operations

32

290207-19

E 28F010

5.0 ORDERING INFORMATION

E 2 8 F 0 1 0 - 1 2 0

Operating Temperature

T = Extended Temp
Blank = Commercial Temp

Package

P = 32-Pin PDIP
N = 32-Lead PLCC
E = 32-Lead TSOP

Product Line Designator

for all Intel Flash products

VALID COMBINATIONS:

E28F010-90 N28F010-90 P28F010-90
E28F010-120 N28F010-120 P28F010-120
E28F010-150 N28F010-150 P28F010-150

TE28F010-90 TN28F010-90 TP28F010-90
TE28F010-120 TN28F010-120 TP28F010-120
TE28F010-150 TN28F010-150 TP28F010-150

Access Speed

Density

= 1 Mbit

010

(ns)

6.0 ADDITIONAL INFORMATION

Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.

290207-20

33