Datasheet TDA9962 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA9962

12-bit, 3.0 V, 20 Msps
analog-to-digital interface for CCD
cameras

Objective specification
File under Integrated Circuits, IC02

2000 May 01

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

FEATURES

• Correlated Double Sampling (CDS), Programmable
GainAmplifier (PGA),12-bitAnalog-to-DigitalConverter
(ADC) and reference regulator included

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 20 MHz

• PGA gain range of 24 dB (in steps of 0.1 dB)

• Low power consumption of only 140 mW at 2.7 V

• Power consumption in standby mode of 4.5 mW (typ.)

• 3.0 V operation and 2.2 to 3.6 V operation for the digital

outputs

• All digital inputs accept 5 V signals

• Active control pulses polarity selectable via serial

interface

• 8-bit DAC included for analog settings

• TTL compatible inputs, CMOS compatible outputs.

TDA9962

APPLICATIONS

• Low-power, low-voltage CCD camera systems.

GENERAL DESCRIPTION

The TDA9962 is a 12-bit analog-to-digital interface for
CCD cameras. The device includes a correlated double
samplingcircuit, PGA, clamploops and alow-power 12-bit
ADC together with its reference voltage regulator.

The PGA gain and the ADC input clamp level are
controlled via the serial interface.

An additional DAC is provided for additional system
controls; its output voltage range is 1.0 V (p-p) which is
available at pin OFDOUT.

ORDERING INFORMATION

TYPE

NUMBER

TDA9962HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

NAME DESCRIPTION VERSION

PACKAGE

2000 May 01 2

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

ADC

res

V

i(CDS)(p-p)

f

pix(max)

f

pix(min)

DR

PGA

N

tot(rms)

E

in(rms)

P

tot

analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital outputs supply voltage 2.2 2.5 3.6 V
analog supply current all clamps active − 49 − mA
digital supply current − 2 − mA
digital outputs supply current f

= 20 MHz; CL= 20 pF; input

pix

− 1 − mA

ramp response time is 800 µs
ADC resolution − 12 − bits
maximum CDS input voltage

(peak-to-peak value)

VCC= 2.85 V 650 −−mV

V

≥ 3.0 V 800 −−mV

CC

maximum pixel rate 20 −−MHz
minimum pixel rate tbf −−MHz
PGA dynamic range − 24 − dB
total noise from CDS input to

PGA gain = 0 dB; see Fig.8 − 1.2 − LSB
ADC output

equivalent input noise

gain=24dB − 95 −µV
(RMS value)

total power consumption V

CCA=VCCD=VCCO

V

CCA=VCCD=VCCO

=3V − 155 − mW
= 2.7 V − 140 − mW

2000 May 01 3

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2000 May 01 4

BLOCK DIAGRAM

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

interface for CCD cameras

CPCDS1

CPCDS2

V

CCA2

AGND2

V

CCA3

AGND3

OFDOUT

47

REGULATOR

OE

39

OUTPUT
BUFFER

22
21

37

38
36
35
34
33
32
31
30
29
28
27
26
25

24
23

10

FCE504

DGND1
V

CCD1

OGND2

V

CCO2

D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1

D0

OGND1

V

CCO1

DCLPC

20

BLK

43

BLANKING

42

STDBY

SHD

AGND4

V

CCA1

1

46

SHIFT

V

ref

13

AGND5

SHP

45

CDS CLOCK GENERATOR

8

9
7

3

CORRELATED

4

IN

14

5

11

DOUBLE

SAMPLING

OFD DAC

12 6

TEST

CLAMP

AGND1

2

CLAMP

V

CCA4

41

AGND6

40

PGA

8-BIT

REGISTER

8-BIT

REGISTER

CLPDM

CLPOB

48

44

15

OPGA OPGAC

TDA9962

16

BLACK
LEVEL
SHIFT

19

SEN

7-BIT

REGISTER

SERIAL

INTERFACE

18

SCLK

SDATA

12-bit ADC

17

VSYNC

CLK

DATA

FLIP-

FLOP

handbook, full pagewidth

Fig.1 Block diagram.

TDA9962

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

PINNING

SYMBOL PIN DESCRIPTION

V

CCA1

AGND1 2 analog ground 1
AGND2 3 analog ground 2
IN 4 input signal from CCD
AGND3 5 analog ground 3
AGND4 6 analog ground 4
V

CCA2

CPCDS1 8 clamp storage capacitor pin 1
CPCDS2 9 clamp storage capacitor pin 2
DCLPC 10 regulator decoupling pin
OFDOUT 11 analog output of the additional 8-bit control DAC
TEST 12 test mode input pin (should be connected to AGND5)
AGND5 13 analog ground 5
V

CCA3

OPGA 15 PGA output (test pin)
OPGAC 16 PGA complementary output (test pin)
SDATA 17 serial data input for serial interface control
SCLK 18 serial clock input for serial interface
SEN 19 strobe pin for serial interface
VSYNC 20 vertical sync pulse input
V

CCD1

DGND1 22 digital ground 1
V

CCO1

OGND1 24 digital output ground 1
D0 25 ADC digital output 0 (LSB)
D1 26 ADC digital output 1
D2 27 ADC digital output 2
D3 28 ADC digital output 3
D4 29 ADC digital output 4
D5 30 ADC digital output 5
D6 31 ADC digital output 6
D7 32 ADC digital output 7
D8 33 ADC digital output 8
D9 34 ADC digital output 9
D10 35 ADC digital output 10
D11 36 ADC digital output 11 (MSB)
OGND2 37 digital output ground 2
V

CCO2

OE 39 output enable control input (LOW = outputs active; HIGH = outputs in high-impedance)
AGND6 40 analog ground 6

1 analog supply voltage 1

7 analog supply voltage 2

14 analog supply voltage 3

21 digital supply voltage 1

23 digital outputs supply voltage 1

38 digital outputs supply voltage 2

2000 May 01 5

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

SYMBOL PIN DESCRIPTION

V

CCA4

STDBY 42 standby mode control input (LOW = TDA9962 active; HIGH = TDA9962 standby)
BLK 43 blanking control input
CLPOB 44 clamp pulse input at optical black
SHP 45 preset sample-and-hold pulse input
SHD 46 data sample-and-hold pulse input
CLK 47 data clock input
CLPDM 48 clamp pulse input at dummy pixel

handbook, full pagewidth

41 analog supply voltage 4

CLPDM

CLK

48

47

SHD
46

SHP
45

CLPOB

BLK

44

43

STDBY

V

42

41

CCA4

AGND6
40

39

OE

CCO2

V
38

OGND2
37

V

CCA1
AGND1
AGND2

IN

AGND3
AGND4

V

CCA2

CPCDS1

CPCDS2

DCPLC

OFD

TEST

D11

24

OGND1

36
35
34
33
32
31
30
29
28
27
26
25

FCE505

D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

1
2
3
4
5
6
7
8
9

10
11
12

13

14

CCA3

V

AGND5

15

OPGA

TDA9962HL

16

17

SDATA

OPGAC

18

SCLK

19

SEN

21

20

CCD1

V

VSYNC

22

23

CCO1

DGND1

V

Fig.2 Pin configuration.

2000 May 01 6

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

CC

V

i

I

o

T

stg

T

amb

T

j

Note

1. The supply voltages V
voltage difference ∆VCC remains as indicated.

analog supply voltage note 1 −0.3 +7.0 V
digital supply voltage note 1 −0.3 +7.0 V
digital outputs supply voltage note 1 −0.3 +7.0 V
supply voltage difference

between V
between V
between V

CCA
CCA
CCD

and V
and V
and V

CCD
CCO
CCO

−0.5 +0.5 V

−0.5 +1.2 V

−0.5 +1.2 V

input voltage referenced to AGND −0.3 +7.0 V
data output current −±10 mA
storage temperature −55 +150 °C
ambient temperature −20 +75 °C
junction temperature − +150 °C

, V

CCA

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 76 K/W

2000 May 01 7

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

CHARACTERISTICS

V

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

Digital inputs

INS SHP, SHD AND CLK (REFERENCED TO DGND)

P
V

IL

V

IH

I

i

Z

i

C

i

PINS CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK AND VSYNC
V

IL

V

IH

I

i

Clamps

= 3.0 V; V

CCO

= 2.5 V; f

= 20 MHz; T

pix

=25°C; unless otherwise specified.

amb

analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
digital outputs supply

2.2 2.5 3.6 V

voltage
analog supply current all clamps active − 49 − mA
digital supply current − 2 − mA
digital outputs supply

current

CL= 20 pF on all data
outputs; input ramp

− 1 − mA

response time is 800 µs

LOW-level input voltage 0 − 0.6 V
HIGH-level input voltage 2.2 − 5.5 V
input current 0 ≤ Vi≤ 5.5 V −3 − +3 µA
input impedance f
input capacitance f

=20MHz − 50 − kΩ

CLK

=20MHz −− 2pF

CLK

LOW-level input voltage 0 − 0.6 V
HIGH-level input voltage 2.2 − 5.5 V
input current 0 ≤ Vi≤ 5.5 V −2 − +2 µA

GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
t

W(clamp)

clamp active pulse width
in number of pixels

PGA code = 255 for

maximum 4 LSB error
INPUT CLAMP (DRIVEN BY CLPDM)
g

m(CDS)

CDS input clamp
transconductance

Correlated Double Sampling (CDS)

V

i(CDS)(p-p)

V

reset(max)

maximum peak-to-peak
CDS input amplitude
(video signal)

maximum CDS input reset

VCC= 2.85 V 650 −−mV

≥ 3.0 V 800 −−mV

V

CC

pulse amplitude

I

i(IN)

C

i

t

CDS(min)

input current into pin IN at floating gate level tbf − tbf µA
input capacitance − 2 − pF
CDS control pulses

minimum active time

V

i(CDS)(p-p)

= 800 mV
black-to-white transition in
1 pixel with 99% Vi recovery

2000 May 01 8

12 −−pixels

− 20 − mS

500 −−mV

11 15 − ns

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

h(IN;SHP)

t

h(IN;SHD)

Amplifier

DR

PGA

∆G

PGA

Analog-to-Digital Converter (ADC)

DNL differential non linearity f

Total chain characteristics (CDS + PGA + ADC)

f

pix(max)

f

pix(min)

t

CLKH

t

CLKL

t

d(SHD;CLK)

t

su(BLK;SHD)

V

i(IN)(FS)

N

tot(rms)

E

in(rms)

O

CCD(max)

Digital-to-analog converter (OFDOUT DAC)

V

OFDOUT(p-p)

V

OFDOUT(0)

V

OFDOUT(255)

TC

DAC

Z

OFDOUT

I

OFDOUT

CDS input hold time
(pin IN) compared to
control pulse SHP

CDS input hold time
(pin IN) compared to
control pulse SHD

V

CCA=VCCD

T

=25°C;

amb

= 3.0 V;

see Figs 3 and 4
V

CCA=VCCD

T

=25°C;

amb

= 3.0 V;

see Figs 3 and 4

− 12ns

− 12ns

PGA dynamic range − 24 − dB
PGA gain step 0.08 0.10 0.12 dB

= 20 MHz; ramp input −±0.5 ±0.9 LSB

pix

maximum pixel frequency 20 −−MHz
minimum pixel frequency tbf −−MHz
CLK pulse width HIGH 15 −−ns
CLK pulse width LOW 15 −−ns
time delay between

see Figs 3 and 4 10 −−ns

SHD and CLK
set-up time of BLK

see Figs 3 and 4 5 −−ns

compared to SHD
video input dynamicsignal

for ADC full-scale output
total noise from CDS input

to ADC output
(RMS value)

equivalent input noise
voltage (RMS value)

maximum offset between

PGA code = 00 800 −−mV
PGA code = 255 50 −−mV
see Fig.8

PGA gain = 0 dB − 1.2 − LSB

PGA gain = 9 dB − 2.0 − LSB
PGA gain = 24 dB − 95 −µV
PGA gain=9dB − 135 −µV

−100 − +100 mV
CCD floating level and
CCD dark pixel level

additional 8-bit control

Ri=1MΩ−1.0 − V
DAC(OFD) output voltage
(peak-to-peak value)

DC output voltage for

− AGND − V

code 0
DC output voltage for

− AGND + 1.0 − V

code 255
DAC output range

− 250 − ppm/°C

temperature coefficient
DAC output impedance − 2000 −Ω
OFD output current drive static −− 100 µA

2000 May 01 9

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital outputs (f

V

OH

V

OL

I

OZ

t

h(o)

t

d(o)

C

L

Serial interface

f

SCLK(max)

= 20 MHz; CL= 10 pF); see Figs 3 and 4

pix

HIGH-level output voltage IOH= −1mA V

− 0.5 − V

CCO

CCO

V
LOW-level output voltage IOL=1mA 0 − 0.5 V
output current in 3-state

0.5V<Vo<V

CCO

−20 − +20 µA

mode
output hold time 5 −−ns
output delay time CL= 10 pF; V

C

= 10 pF; V

L

C

= 10 pF; V

L

= 3.0 V − 16 tbf ns

CCO

= 2.7 V − 18 tbf ns

CCO

= 2.2 V − tbf tbf ns

CCO

output load capacitance −− 20 pF

maximum frequency of

10 −−MHz

serial clock interface

2000 May 01 10

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2000 May 01 11

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

interface for CCD cameras

IN

SHP

SHD

CLK

DATA

0.6 V

t

h(IN;SHP)

N

0.6 V

t

h(IN;SHD)

2.2 V

t

CLKH

t

d(SHD;CLK)

t

CDS(min)

0.6 V

0.6 V

N + 2 N + 1 N + 3 N + 4

2.2 V

t

CDS(min)

2.2 V

2.2 V

0.6 V

50%

N − 2 N − 1 N − 3 N − 4

t

h(o)

t

d(o)

2.2 V

2.2 V

N

N + 5

ADC CLAMP

CODE

BLK

t

su(BLK;SHD)

handbook, full pagewidth

Fig.3 Pixel frequency timing diagram; all polarities active HIGH.

FCE506

TDA9962

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2000 May 01 12

IN

SHP

SHD

2.2 V

t

h(IN;SHP)

N

2.2 V

t

CDS(min)

N + 2 N + 1 N + 3 N + 4

0.6 V

2.2 V

0.6 V

N + 5

0.6 V

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

interface for CCD cameras

CLK

DATA

BLK

t

h(IN;SHD)

t

CLKL

t

CDS(min)

2.2 V 2.2 V

0.6 V

t

d(SHD;CLK)

50%

N − 2 N − 1 N − 3 N − 4

handbook, full pagewidth

t

h(o)

0.6 V

Fig.4 Pixel frequency timing diagram; all polarities active LOW.

t

d(o)

0.6 V

t

su(BLK;SHD)

N

ADC CLAMP

CODE

FCE507

TDA9962

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

handbook, full pagewidth

OFDOUT DAC

voltage

output

(V)

1.0

0

0

OFDOUT control DAC input code

TDA9962

FCE508

255

handbook, full pagewidth

Fig.5 DAC voltage output as a function of DAC input code.

CLPOB

WINDOW

AGCOUT VIDEO OPTICAL BLACK

CLPOB

(active HIGH)

CLPDM

(active HIGH)

BLK

(active HIGH)

CLPDM

WINDOW

HORIZONTAL FLYBACK DUMMY VIDEO

BLK window

FCE509

Fig.6 Line frequency timing diagram.

2000 May 01 13

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

30

handbook, halfpage

TOTAL

gain
(dB)

24

18

12

6

1.9

0

0 64 192

128

TDA9962

FCE510

25.9

255

PGA input code

Fig.7 Total gain from CDS input to ADC input as a function of PGA input code.

FCE511

256

PGA code

N

tot(rms)

(LSB)

8

7

6

5

4

3

2

1

0

640 192128

handbook, halfpage

Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works
at 20 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during
the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into
account.

Fig.8 Typical total noise performance as a function of PGA gain.

2000 May 01 14

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

handbook, full pagewidth

SDATA

SCLK

SEN

SCLK

8 10 5 9

OFDOUT DAC

LATCHES

SD0

LSB

PGA GAIN

LATCHES

SD2SD1

SD3 SD4

12

ADC CLAMP

LATCHES

SD5

SHIFT REGISTER

SD6

SD7

CONTROL PULSE

POLARITY

LATCHES

SD8 SD9

SD10

SD11

MSB

VSYNC

A0

SELECTION

TDA9962

A1 A2 A3

LATCH

handbook, full pagewidth

SDATA

SCLK

SEN

FLIP-FLOP

8-bit DAC

A3

t

su1

FLIP-FLOP

PGA control

A1A2

FLIP-FLOP

ADC clamp

control

control pulses

polarity settings

Fig.9 Serial interface block diagram.

MSB

A0

SD11

SD10

SD9

SD8

SD7 SD6 SD5 SD4 SD3

t

su2

t

hd4

FCE512

LSB

SD2 SD1 SD0

t

su3

t

hd3

FCE513

t

su1=tsu2=tsu3

= 10 ns (min.); t

hd3=thd4

= 10 ns (min.).

Fig.10 Loading sequence of control input data via the serial interface.

2000 May 01 15

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

Table 1 Serial interface programming

ADDRESS BITS

A3 A2 A1 A0

0000PGA gain control (SD7 to SD0)
0001DAC OFDOUT output control (SD7 to SD0)
0010ADC clamp reference control (SD6 to SD0); from code 0 to 127
0011control pulses (pins SHP, SHD,CLPDM, CLPOB, BLK and CLK) polarity settings; SD2,

SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see Tables 3, 4, 5 and 6

0100SD7=0bydefault; SD7 = 1 PGA gain up to 36 dB but noise and clamp behaviour are

not guaranteed

1111initialization (SD8 = 1; SD11 to SD9 = 0 and SD7 to SD0 = 0)

other addresses test modes

Table 2 Polarity settings

SYMBOL PIN SERIAL CONTROL BIT ACTIVE EDGE OR LEVEL

SHP and SHD 45 and 46 SD4 1 = HIGH; 0 = LOW
CLK 47 SD5 1 = rising; 0 = falling
CLPDM 48 SD0 1 = HIGH; 0 = LOW
CLPOB 44 SD1 1 = HIGH; 0 = LOW
BLK 43 SD3 1 = HIGH; 0 = LOW
VSYNC 20 SD8 0 = rising; 1 = falling

DATA BITS SD11 TO SD0

Table 3 Standby control using pin STDBY

BIT SD7 OF REGISTER

0011

1 1 last logic state 1.5 mA

0 1 active 51 mA

STDBY ADC DIGITAL OUTPUTS SD11 TO SD0 I

0 active 51 mA

0 test logic state 1.5 mA

CCA+ICCO+ICCD

(typ.)

2000 May 01 16

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

Table 4 Output enable selection using output enable pin (OE)

BIT SD6 OF REGISTER 0011 OE ADC DIGITAL OUTPUTS SD9 TO SD0

1 0 active, binary

1 high-impedance

0 0 high-impedance

1 active binary

Table 5 Standby control by serial interface (register address A3 = 0, A2 = 0, A1 = 1, A0 = 1);

pin STDBY connected to ground

SD7 ADC DIGITAL OUTPUTS SD9 TO SD0 I

0 last logic state 1.5 mA
1 active 72 mA

Table 6 Output enable control by serial interface (register address A3 = 0, A2 = 0, A1 = 1, A0 = 1);

output enable pin (OE) connected to ground

SD6 ADC DIGITAL OUTPUTS SD9 TO SD0

0 high-impedance
1 active binary

CCA+ICCO+ICCD

(typ.)

TDA9962

2000 May 01 17

Philips Semiconductors Objective specification

n

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

APPLICATION INFORMATION

V

CCA

V

STDBY

V

100 nF

CCA4

CCD

AGND6

dbook, full pagewidth

CLK

(2) (2)

SHD

SHP

BLK

CLPOB

TDA9962

V

CCA

CCD

(2)

1 µF

V

100 nF

CCA

1 µF

1 µF

1 µF

V

CCA1
AGND1
AGND2

AGND3

AGND4
V

CCA2

CPCDS1
CPCDS2

DCPLC

OFD

TEST

CLPDM

48 47 46 45 44 43 42 41 40 39 38 37
1
2
3

IN

4
5
6
7
8
9
10
11
12

13 14 15 16 17 18 19 20 21 22 23 24

OE

V

CCO

100 nF

CCO2

V

V

CCD

OGND2

D11

36

D10

35

D9

34

D8

33

D7

32

D6

31

D5

30

D4

29

D3

28

D2

27

D1

26

D0

25

CCA3

V

V

CCA

OPGA

100 nF

OPGAC

AGND5

(1) Pins SEN and VSYNC should be interconnected when vertical sync signal is not available.
(2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals t

Fig.11 Application diagram.

2000 May 01 18

SCLK

SDATA

serial

interface

h(IN;SHP)

SEN

and t

CCD1

VSYNC

(1)

V

h(IN;SHD)

V

CCD

CCO1

V

DGND1

100 nF

(see Chapter “Characteristics”).

V

OGND1

100 nF

CCO

FCE514

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

Power and grounding recommendations

When designing a printed-circuit board for applications
such as PC cameras, surveillance cameras, camcorders
and digital still cameras, care should be taken to minimize
the noise.

For the front-end integrated circuit, the basic rules of
printed-circuit board design and implementation of analog
components (such as classical operational amplifiers)
must be respected, particularly with respect to power and
ground connections.

The following additional recommendation is given for the
CDS input pin(s) which is/are internally connected to the
programmable gain amplifier.

The connections between the CCD interface and the CDS
input should be as short as possible and a ground ring
protection around these connections can be beneficial.
Separate analog and digital supplies provide the best
solution. If itis not possible to dothis on the board thenthe
analog supply pins must be decoupled effectively from the
digital supply pins. If the same power supply and ground
are used for all the pins then the decoupling capacitors
must be placed as close as possible to the IC package.

TDA9962

In a two-ground system, in order to minimize the noise
through package and die parasitics, the following
recommendation must be implemented.

Allthe analog anddigital supply pinsmustbe decoupled to
the analog ground plane. Only the ground pin associated
with the digital outputs must be connected to the digital
ground plane. All the other ground pins should be
connected to the analog ground plane. The analog and
digital ground planes must be connected together at one
point as close as possible to the ground pin associated
with the digital outputs.

Thedigital output pinsand their associated linesshould be
shielded by the digital ground plane which can then be
used as a return path for digital signals.

2000 May 01 19

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

c

y

X

36

37

25

Z

24

E

A

TDA9962

SOT313-2

e

w M

pin 1 index

48

1

e

DIMENSIONS (mm are the original dimensions)

mm

A

A1A2A3bpcE

max.

0.20

0.05

1.45

1.35

1.60

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

b

p

0.25

w M

D

H

D

0.27

0.17

12

Z

D

(1) (1)(1)

D

0.18

7.1

0.12

6.9

b

p

13

v M

B

v M

0 2.5 5 mm

scale

(1)

eH

H

7.1

6.9

0.5

9.15

8.85

D

E

A

B

9.15

8.85

H

E

LL

E

A

0.75

0.45

p

A

2

A

1

L

detail X

Z

D

0.12 0.10.21.0

0.95

0.55

(A )

3

L

p

Zywv θ

E

0.95

0.55

θ

o

7

o

0

OUTLINE
VERSION

SOT313-2 MS-026136E05

IEC JEDEC EIAJ

REFERENCES

2000 May 01 20

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27
00-01-19

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital
interface for CCD cameras

SOLDERING
Introduction to soldering surface mount packages

Thistext gives a verybriefinsightto a complextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages.Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering andcooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

TDA9962

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on foursides,thefootprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering,the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 May 01 21

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP andTSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

SOLDERING METHOD

WAVE REFLOW

(2)

(3)(4)
(5)

suitable

suitable
suitable

(1)

.

2000 May 01 22

Philips Semiconductors Objective specification

12-bit, 3.0 V, 20 Msps analog-to-digital

TDA9962

interface for CCD cameras

DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or at anyotherconditions above those giveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warranty that such applicationswillbe
suitable for the specified use without further testing or
modification.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expectedto result inpersonal injury. Philips
Semiconductorscustomersusing or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of theseproducts,conveysno licence or title
under any patent, copyright, or mask work right to these
products,and makes no representationsor warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

(1)

2000 May 01 23

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

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220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
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Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

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Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
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Portugal: see Spain
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252042 KIEV, Tel. [phone], Fax. [phone]

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

69

Printed in The Netherlands 753504/01/pp24 Date of release: 2000 May 01 Document order number: 9397 750 06915