Datasheet TDA9901TS-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1998 Apr 15
File under Integrated Circuits, IC02

1999 Oct 08

INTEGRATED CIRCUITS

TDA9901

Wideband differential digital
controlled variable gain amplifier

1999 Oct 08 2

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

FEATURES

• 130 MHz, −3 dB small signal bandwidth

• Digitally controlled gain

• TTL/CMOS compatible digital inputs (3.3 or 5 V)

• TTL single ended or differential clock input with PECL

compatibility

• 24 dB gain control range

• Five steps of 6 dB plus 6 dB fixed gain

• 30 dB gain maximum

• High impedance differential inputs

• Low impedance differential outputs

• High power supply rejection

• 125 nV/√Hz output voltage noise density at 30 dB gain

• Fast gain settling

• Dual control modes: transparent or latched.

APPLICATIONS

• Linear AGC systems

• IF amplifierin IF conversion systems (e.g. base stations

or satellite receivers)

• Instrumentation

• Multi-purpose amplifier

• Driver for differential ADCs (e.g. TDA8768).

GENERAL DESCRIPTION

The TDA9901 is a wideband, low noise amplifier with
differential inputs andoutputs. TheTDA9901 incorporates
an AGC function with digital control. The TDA9901 is
optimized for fast switching between different gain
settings, preserving small phase and amplitude error.

The TDA9901 presents an excellent combination of low
noise and good linearity for a wide input frequency range.

The TDA9901 is optimized for processing IF signals in
GSM base stations. It is also suited for many other
applications as a general purpose digitally controlled
variable gain amplifier.

The TDA9901 is able to operate from 4.75 to 5.25 V
supply for the analog part and from 3.0 to 5.25 V for the
digital part.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DDA

analog supply voltage 4.75 5.0 5.25 V

V

DDD

digital supply voltage 3.0 3.3 5.25 V

I

DDA

analog supply current − 30 36 mA

I

DDD

digital supply current − 3.0 5.0 mA

G

dif

differential gain minimum gain 5.7 6.11 6.46 dB

maximum gain 29.3 30.5 31.5 dB

B

−3dB

−3 dB small signal bandwidth V

o(dif)(p-p)

= 0.125 V;

T

amb

=25°C

110 130 − MHz

P

tot

total power dissipation − 160 216 mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA9901TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

1999 Oct 08 3

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGM962

REFERENCE
GENERATOR

REFERENCE
GENERATOR

LATCHES

DECODER

GRAY2

19

GRAY1

20

V

SSD

17

V

SSA

12

165

7

6

14

15

n.c.

0, 6, 12, 18 or 24 dB

6 dB

8, 9, 10, 13

V

DDA

11

GRAY0

1

TE

2

V

DDD

18

CLK3CLKN

4

CMVGA

IN

INN

OUT
OUTN

CMADC

TDA9901

1999 Oct 08 4

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

PINNING

SYMBOL PIN DESCRIPTION

GRAY0 1 digital control signal bit 0 input

(LSB)
TE 2 transparent enable input
CLK 3 clock input for gain control setting
CLKN 4 inverting clock input for gain

control setting (active low)
CMVGA 5 regulator output common mode

VGA input
IN 6 non-inverting analog input
INN 7 inverting analog input (active low)
n.c. 8 not connected
n.c. 9 not connected
n.c. 10 not connected
V

DDA

11 analog supply voltage

V

SSA

12 analog ground
n.c. 13 not connected
OUTN 14 inverting analog output (active low)
OUT 15 non-inverting analog output
CMADC 16 regulator output common mode

ADC input

V

SSD

17 digital ground
V

DDD

18 digital supply voltage
GRAY2 19 digital control signal bit 2 input

(MSB)

GRAY1 20 digital control signal bit 1 input

handbook, halfpage

GRAY0

TE

CLK

CLKN

CMVGA

IN

INN

n.c.
n.c.
n.c.

GRAY1
GRAY2

V

DDD

V

SSD

OUT
OUTN

CMADC

n.c.
V

SSA

V

DDA

1
2
3
4
5
6
7
8
9

10

11

12

20
19
18
17
16
15
14
13

TDA9901TS

MGM963

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

The TDA9901 provides a digitally controlled variable gain function for high-frequency applications.
The TDA9901 can beoperated in two different modes, depending onthe value at pin TE. When TE is at logic 1, the gain

can be instantly controlled when the clock signal is HIGH (transparent mode). The gain is fixed during the LOW period
of the clock. When TE is at logic 0 the gain of the TDA9901 is changed at the rising edge of the clock signal.

1999 Oct 08 5

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

CHARACTERISTICS

V

DDA=V11

to V12= 4.75 to 5.25 V; V

DDD=V18

to V17= 3.0 to 5.25 V; V

SSA

and V

SSD

shorted together;

T

amb

= −40 to +85 °C; typical values measured at V

DDA

= 5.0 V; V

DDD

= 3.3 V and T

amb

=25°C; unless otherwise

specified; note 1.

SYMBOL PARAMETER MIN. MAX. UNIT

V

DDA

analog supply voltage −0.3 +7.0 V

V

DDD

digital supply voltage −0.3 +7.0 V

∆V

DD

supply voltage difference between V

DDA

and V

DDD

−1.0 +4.0 V

V

I

input voltage level −0.3 +7.0 V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

ambient temperature −40 +85 °C

T

j

junction temperature − 150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 120 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

analog supply voltage 4.75 5.0 5.25 V

V

DDD

digital supply voltage 3.0 3.3 5.25 V

∆V

DD

voltage difference
between V

DDA

and V

DDD

−0.2 − +2.5 V

I

DDA

analog supply current − 30 36 mA

I

DDD

digital supply current − 3.0 5.0 mA

Variable gain amplifier transfer characteristics

B

−3dB

−3 dB small signal

bandwidth

V

o(dif)(p-p)

= 0.125 V;

T

amb

=25°C

110 130 − MHz

t

d(g)

group delay time up to fi= 20 MHz;

minimum gain;
T

amb

=25°C

− 2.5 − ns

∆t

d(g)

group delay difference 6 dB gain step;

T

amb

=25°C

−−300 ps

1999 Oct 08 6

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

t

st

settling time 10 to 90% maximum

output transition;
C

L(max)

= 5 pF on
each output;
T

amb

=25°C

−−3.6 ns

G

step

gain step size DC input

T

amb

=25°C 5.88 6.09 6.28 dB

all temperatures 5.6 6.09 6.56 dB

G

(min)

minimum gain setting DC input

T

amb

=25°C 5.76 6.11 6.40 dB

all temperatures 5.7 6.11 6.46 dB

G

(max)

maximum gain setting DC input

T

amb

=25°C 29.9 30.5 30.9 dB

all temperatures 29.3 30.5 31.5 dB

∆G/∆T gain stability as a function

of temperature

minimum gain −−1.0 − mdB/°C
maximum gain −−7.5 − mdB/°C

|∆G/∆VDD| gainstability as a function

of power supply

minimum gain − 15 25 mdB/V

∆V

i(offset)

input offset voltage
difference

6 dB gain step − 0.8 − mV

F noise figure R

s

= 100 Ω;

fi= 20 MHz

minimum gain − 29.1 − dB
maximum gain − 9.9 − dB

V

n(o)(eq)

equivalent output noise
voltage spectral density

Rs= 100 Ω;
fi= 20 MHz;
T

amb

=25°C
G=6dB − 75 − nV/√Hz
G = 12 dB − 82 − nV/√Hz
G = 18 dB − 97 − nV/√Hz
G = 24 dB − 91 − nV/√Hz
G = 30 dB − 124 − nV/√Hz

PSRR

(VDDA)

power supply ripple
rejection of V

DDA

minimum gain

0to20MHz − 57 − dB
20 to 100 MHz − 39 − dB

PSRR

(VDDD)

power supply ripple
rejection of V

DDD

minimum gain dB

0to20MHz − 67 − dB
20 to 100 MHz − 51 − dB

CMRR common mode rejection

ratio

0to20MHz − 75 − dB
20 to 150 MHz − 45 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 08 7

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

Analog inputs

V

i(max)(p-p)

maximum input voltage
(peak-to-peak value)

minimum gain − 1.0 − V
maximum gain − 60.4 − mV

V

i(cm)

common mode input
voltage

2.0 2.7 V

DDA

− 1.9 V

I

i

input current V

i(cm)

= 2.7 V − 55 −µA

R

i

input resistance 10 −−kΩ

C

i

input capacitance −−5pF
Analog outputs; note 2
V

o(max)(p-p)

maximum differential

output voltage

(peak-to-peak value)

maximum gain 2.0 −−V
minimum gain 2.0 −−V

V

o(cm)

common mode output

voltage

referenced to V

DDA

;

T

amb

=25°C

V

DDA

− 2.56 V

DDA

− 2.42 V

DDA

− 2.29 V

∆V

o(cm)

/∆T common mode output

voltage variation with

temperature

−−1.8 − mV/°C

SR

o(se)

single-ended output slew

rate

− 275 − V/µs

R

o

output resistance − 15 26 Ω
C

o

output capacitance − 3 − pF
Variable gain amplifier dynamic performance; CL= 5 pF; RL= 680 Ω (see Figs 6, 7, 8, 9 and 10)
HD

2

2nd harmonic distortion Vo=V

o(max)

fi= 0.5 MHz −−80 −67 dBc
f

i

= 4.43 MHz −−77 −67 dBc

f

i

= 12.5 MHz −−76 −65 dBc

f

i

= 21.4 MHz −−74 −62 dBc

HD

3

3rd harmonic distortion Vo=V

o(max)

;

T

amb

=25°C

f

i

= 0.5 MHz −−64 −60 dBc

f

i

= 4.43 MHz −−64 −59 dBc

f

i

= 12.5 MHz −−62 −58 dBc

f

i

= 21.4 MHz −−61 −57 dBc

∆HD

3

/∆T 3rd harmonic distortion

variation with temperature

fi= 21.4 MHz − 80 − mdB/°C

Reference voltage output ADC: pin CMADC

V

ref(CMADC)

ADC reference output

voltage

referenced to V

DDA

;

T

amb

=25°C

V

DDA

− 1.64 V

DDA

− 1.45 V

DDA

− 1.26 V

R

o(CMADC)

output resistance T

amb

=25°C − 17 26 Ω

∆V

ref(CMADC)

/∆T ADC reference output

voltage variation with

temperature

−−0.11 − mV/°C

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 08 8

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

I

o(CMADC)(max)

maximum output current − 1.0 − mA
C

o(CMADC)

output capacitance − 3 − pF

Reference voltage output VGA: pin CMVGA

V

ref(CMVGA)

VGA reference output

voltage

referenced to V

DDA

;

T

amb

=25°C

V

DDA

− 2.48 V

DDA

− 2.30 V

DDA

− 2.17 V

R

o(CMVGA)

output resistance T

amb

=25°C − 920Ω

∆V

ref(CMVGA)

/∆T VGA reference output

voltage variation with

temperature

− 1.75 − mV/°C

I

o(CMVGA)(max)

maximum output current − 1.0 − mA
C

o(CMVGA)

output capacitance − 3 − pF

Gain switching characteristics (in latched mode); f

CLK

= 52 MHz; T

amb

=25°C; (see Fig.3)

t

h

input data hold time 2.0 −−ns
t

su

input data set-up time 3.8 −−ns
t

W

input data pulse width 5.8 −−ns
t

PD1

propagation delay time − 4.2 5.9 ns
t

set1

gain settling time 10 to 90% full scale

if ±6 dB gain
change; note 3

− 2.6 3.2 ns

Gain switching characteristics (in transparent mode); f

CLK

= 52 MHz; T

amb

=25°C; (see Fig.4)

t

PD2

propagation delay time − 6.7 9.5 ns
t

set2

gain settling time 10 to 90% full scale

if ±6 dB gain
change; note 4

− 5.4 6.9 ns

Clock timing input: pins CLK and CLKN (see Fig.3)
f

CLK(max)

maximum clock frequency 52 −−MHz
t

CPL

clock LOW pulse width 4.0 −−ns
t

CPH

clock HIGH pulse width 4.0 −−ns
t

r

rise time − 4 − ns
t

f

fall time − 4 − ns

Digital inputs: pins TE, GRAY0, GRAY1 and GRAY2

V

IL

LOW-level input voltage 0 − 0.8 V
V

IH

HIGH-level input voltage 2.0 − V

DDD

V

I

IH

HIGH-level input current −10 − +10 µA
I

IL

LOW-level input current −10 − +10 µA
C

i

input capacitance −−3pF

Clock inputs in TTL mode

V

IL

LOW-level input voltage note 5 0 − 0.8 V
V

IH

HIGH-level input voltage note 5 2.0 − V

DDD

V

I

IH

HIGH-level input current 15 − 80 µA
I

IL

LOW-level input current −40 −−10 µA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 08 9

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

Notes

1. Due to on-chip regulator behaviour a warm-up time of 1 minute (typical) is recommended for optimal performance.

2. The analog output voltages are positive with respect to AGND.

3. In latching mode (TE = 0), the gain settling is latched at the rising edge of the clock input.

4. In transparent mode, the gain settling is directly controlled by the input data pattern.

5. The circuit may be used with a single TTL clock on CLK or CLKN. The non used clock pin has to be decoupled to
ground with a 100 nF capacitance.

6. There are four modes of operation for the clock inputs in non TTL mode:
a) PECL mode 1: (DC level vary 1 : 1 with V

DDA

) CLK and CLKN inputs are differential PECL levels.

b) PECL mode 2: (DC level vary 1 : 1 with V

DDA

) CLK input is at PECL level and gain change takes place on the
rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLKN
decoupled to V

SSD

via a 100 nF capacitor.

c) PECL mode 3: (DC level vary 1 : 1 with V

DDA

) CLKN input is at PECL level and gain change takes place on the
rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLK
decoupled to V

SSD

via a 100 nF capacitor.

d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.1 V (p-p) and with

a DC level of 2.5 V, the gain change takes place on the rising edge of the clock signal. When driving the CLKN
input with the same signal, gain change takes place on the falling edge of the clock signal. It is recommended to
decouple the CLKN or CLK input to V

SSD

via a 100 nF capacitor.

Table 1 Input coding

C

i

input capacitance −−2pF

Clock inputs in differential mode

V

IL

LOW-level input voltage V

DDA

= 5.0 V; note 6 3.19 − 3.52 V

V

IH

HIGH-level input voltage V

DDA

= 5.0 V; note 6 3.83 − 4.12 V

I

IH

HIGH-level input current 15 − 80 µA

I

IL

LOW-level input current −40 −−5µA

C

i

input capacitance −−2pF

∆V

i(CLK )(p-p)

differential AC input
voltage for switching
CLK or CLKN
(peak-to-peak value)

DC voltage
level = 2.5 V

0.1 − 2.0 V

STATE

GREY INPUT DATA CODE

GAIN (dB)

D2 D1 D0

0000minimum
1001minimum + 6
2011minimum + 12
3010minimum + 18
4110minimum + 24

Other −−−minimum + 24

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Oct 08 10

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

handbook, full pagewidth

CLK

MGM964

50 %

HIGH

LOW

10 %

90 %

0.5V

o(max)

0 V

V

o(max)

50 %

HIGH

LOW

GRAY0

OUT

and

OUTN

GRAY1
GRAY2

t

h

t

su

t

CPH

t

CPL

t

r

t

f

gain N

gain N + 1

gain N

gain N + 1

t

set1

t

PD1

Fig.3 Latched mode timing diagram.

handbook, full pagewidth

MGM965

10 %

90 %

0.5V

o(max)

0 V

V

o(max)

50 %

HIGH

LOW

GRAY0

OUT

and

OUTN

GRAY1
GRAY2

gain N

gain N + 1

gain N

gain N + 1

t

set2

t

PD2

Fig.4 Transparent mode timing diagram with CLK HIGH.

1999 Oct 08 11

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

handbook, full pagewidth

FCE306

5

CMVGA OUT

CLK

30 MHz

C1

(1)

C2

(1)

(2)
(3)

680 Ω

680 Ω

100 Ω

100

Ω

sine wave
generator

47 nF

47 nF

dB

100
nF

TDA9901TS

6

IN

7

INN OUTN

15

42

V

i

D0...11

12

TDA8768

(ADC)

43

36

V

i

14

FILTER

Fig.5 Dynamic distortion measurement diagram.

(1) C1 and C2 represent the board line capacitance. They represent about 5 pF with the TDA8768 input capacitance. Special

care has to be taken to minimize this load in order to have the best dynamic performance.

(2) The HD

2

and HD3of the TDA8768 is lower than that measured on the TDA9901.This measurement method is preferred to

conventional methods due to its low contribution to the HD

2

.

(3) The chain measurement shows the harmonic distortion of the TDA9901 as the measurement from TDA8768 is negligible.

Fig.6 Harmonic distortion as a function of

frequency for minimum gain.

handbook, halfpage

−55

−85

10

−1

11010

2

FCE307

−80

−75

−65

−70

−60

HD

(dBc)

f (MHz)

(2)

(1)

(1) HD

3

(2) HD

2

Typical condition; 2 V (p-p) differential output.

handbook, halfpage

−55

−85

10

−1

11010

2

FCE308

−80

−75

−65

−70

−60

HD

(dBc)

f (MHz)

(2)

(1)

Fig.7 Harmonic distortion as a function of

frequency for minimum gain plus 6 dB.

Typical condition; 2 V (p-p) differential output.

(1) HD

3

(2) HD

2

1999 Oct 08 12

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

Fig.8 Harmonic distortion as a function of

frequency for minimum gain plus 12 dB.

Typical condition; 2 V (p-p) differential output.

handbook, halfpage

−55

−85

10

−1

11010

2

FCE309

−80

−75

−65

−70

−60

HD

(dBc)

f (MHz)

(2)

(1)

(1) HD

3

(2) HD

2

Fig.9 Harmonic distortion as a function of

frequency for minimum gain plus 18 dB.

Typical condition; 2 V (p-p) differential output.

handbook, halfpage

−55

−85

10

−1

11010

2

FCE310

−80

−75

−65

−70

−60

HD

(dBc)

f (MHz)

(2)

(1)

(1) HD

3

(2) HD

2

Fig.10 Harmonic distortion as a function of

frequency for minimum gain plus 24 dB.

Typical condition; 2 V (p-p) differential output.

handbook, halfpage

−55

−85

10

−1

11010

2

FCE311

−80

−75

−65

−70

−60

HD

(dBc)

f (MHz)

(2)

(1)

(1) HD

3

(2) HD

2

1999 Oct 08 13

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

APPLICATION INFORMATION

handbook, full pagewidth

47
µF

100 nF

100 nF

47 nF

100

nF

47
µF

100

nF

47 nF

3.3 V

100 nF

5 V

GRAY0

TE

CLK

CLKN

(1)

R1

(2)

100 Ω100 Ω

R2

(2)

IN

INN

1:1

n.c.

n.c.

n.c.

GRAY1

GRAY2

n.c.

1

2

3

4

5

6

7

8

9

10

11

12

20

19

18

17

16

15

14

13

TDA9901TS

MGM966

OUT

OUTN

V

IN

Fig.11 Application diagram.

(1) Single-ended clock signal can be applied if required.
(2) R1 and R2 should be at least 680 Ω.

1999 Oct 08 14

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

PACKAGE OUTLINE

UNIT A1A2A

3

b

p

cD

(1)E(1)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.1501.4

1.2

0.32

0.20

0.20

0.13

6.6

6.4

4.5

4.3

0.65 1.0 0.2

6.6

6.2

0.65

0.45

0.48

0.18

10

0

o

o

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

SOT266-1

90-04-05
95-02-25

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

X

(A )

3

A

y

0.25

110

20

11

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm

SOT266-1

A

max.

1.5

1999 Oct 08 15

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

SOLDERING
Introduction to soldering surface mount packages

Thistext gives a verybriefinsightto a complextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages.Wave soldering isnot always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering andcooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on foursides,thefootprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering,the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Oct 08 16

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitablefor SSOP and TSSOP packages with a pitch (e) equal to or largerthan 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Oct 08 17

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

NOTES

1999 Oct 08 18

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

NOTES

1999 Oct 08 19

Philips Semiconductors Product specification

Wideband differential digital controlled
variable gain amplifier

TDA9901

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

68

Philips Semiconductors – a w orldwide compan y

For all other countries apply to: Philips Semiconductors,

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Printed in The Netherlands 545004/25/02/pp20 Date of release: 1999 Oct 08 Document order number: 9397 750 05272