Datasheet TDA9873H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA9873H

Multistandard dual carrier stereo
sound decoder

Product specification
File under Integrated Circuits, IC02

1999 Apr 26

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

FEATURES

• Low power consumption

• Alignment-free multistandard FM sound demodulation

• No external intercarrier sound band-pass filters required

• Auto mute switchable via I2C-bus

• Multistandard A2 stereo sound decoder

• No adjustment for reduced channel separation

requirement

• De-emphasis time constant related to standard

• Very reliable digital identification of sound transmission

mode via I

• No external filter for pilot input required

• I2C-bus transceiver with MAD (Module ADdress)

• I2C-bus control for all functions

• Stabilizer circuit for ripple rejection and constant output

level

• Additional mono output

• Pin aligned with TDA9874AH

• ESD protection on all pins.

2

C-bus, alignment-free

GENERAL DESCRIPTION

The TDA9873H is an economic multistandard dual FM
demodulator and analog carrier stereo decoder with

2

I

C-bus control.

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA9873H QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm);

body 14 × 14 × 2.2 mm

SOT205-1

1999 Apr 26 2

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

QUICK REFERENCE DATA

V

=5V; T

CC

f

= 1 kHz, L = R, stereo mode); input level for first SC V

mod

of Figs 7 and 8; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

V

o(rms)

V

o(cl)(rms)

f

i(FM)

S/N

W

t

ident(on)

V

i(FM)(rms)

α

cs(AF)(stereo)

α

ct(AF)(dual)

=25°C; B/G standard (f

amb

= 5.5 MHz, f

SC1

= 5.742 MHz, SC1/SC2= 7 dB, ∆fAF= 27 kHz,

SC2

i(FM)(rms)

=50mV; f

= 4.000 MHz; measured in test circuit

ref

supply voltage 4.5 5 6.6 V
supply current 40 60 75 mA
AF output level (RMS value) 54% modulation; note 1 400 500 600 mV
clipping level of the output

THD < 1.5% 1400 −−mV

signal level (RMS value)
FM-PLL operating frequencies

(switchable)

1st sound carrier

M standard − 4.5 − MHz
B/G standard − 5.5 − MHz
I standard − 6.0 − MHz
D/K standard − 6.5 − MHz

2nd sound carrier

M standard − 4.72 − MHz
B/G standard − 5.74 − MHz
D/K (1) standard − 6.26 − MHz
D/K (2) standard − 6.74 − MHz
D/K (3) standard − 5.74 − MHz

weighted signal-to-noise ratio
(complete signal path)

CCIR 468-4 weighted;
quasi peak; dual mode;

52 56 − dB

B/G standard; note 1

total identification time on for
identification mode change

FM-PLL input sensitivity for
pull-in (RMS value)

AF channel separation (stereo
mode; complete signal path)

AF crosstalk attenuation (dual

normal mode; note 2 0.35 − 2s
fast mode; note 2 0.1 − 0.5 s
1st carrier −−6mV
2nd carrier −−1mV
B/G standard; note 3

without alignment 25 30 − dB

2

I

C-bus alignment 40 45 − dB

65 70 − dB

mode; complete signal path)

Notes

1. Condition for B/G, I and D/K standard: V

= 5 V and ∆f = 27 kHz (m = 54%).

CC

Condition for M standard: VCC= 5 V and ∆f = 13.5 kHz; 6 dB gain added internally, to compensate smaller deviation.

2. The maximum total system identification time on for a channel change is equal to maximum value of t
t

I2C read-out

identification time off for a channel change is equal to maximum value of t

(

see also “The I2C-bus and how to use it”

(order number 9398 393 40011)). The maximum total system

plus t

ident(off)

I2C read-out

ident(on)

. The fast mode is
proposed mainly during search tuning, program or channel select. If the channel is selected, the identification
response should be switched to normal mode for improved reliability. However due to the transition from fast to
normal mode, the identification bits are not valid for one integrator period. Therefore the transmitter mode detected
during the fast mode has to be stored before changing to normal mode. The storage has to be kept for two seconds
(maximum value of t

in the normal mode) from the moment of transition. The identification can now operate in

ident(on)

the normal mode until the next tuning action.

3. R modulated, L monitored.

1999 Apr 26 3

plus

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1999 Apr 26 4

handbook, full pagewidth

BLOCK DIAGRAM

Multistandard dual carrier stereo sound decoder TDA9873H

Philips Semiconductors Product specification

IF

intercarrier

input

4.5, 5.5, 6.0, 6.5

4.72, 5.74, 6.26,

6.74 MHz

IFINT

n.c.

25

4, 5, 9, 11, 12,
16, 17, 19, 20,
22, 23, 36, 44

loop filter

LF1

14

FM DEMODULATOR
NARROW-BAND PLL

SC1

FM DEMODULATOR
NARROW-BAND PLL

SC2

18
LF2

loop filter

AF

AMPLIFIER

1

AF

AMPLIFIER

2

26

AFR13CAF2

AF1O AF2O

32

10

DIGITAL

ACQUISITION
OSCILLATOR

CLOCK

15

24

XTAL

CAF1

4 MHz

external AF

mono stereo

M

R

L

AF1IAF2I
8

33

CDE16CDE2
3

STEREO DECODER

STEREO ADJUST

B/G, D/K, I, M (Korea)

STANDARD

TDA9873H

DIGITAL

IDENTIFICATION

PILOT

NARROW-BAND PLL

34

LPF31CID35CTRIG

pilot
loop

EXTM

EXTR

EXTL

38

39

40

AF SWITCH

POWER
SUPPLY

2

C-BUS

I

TRANSCEIVER

SDA30SCL29P137P2

1

OUTL

2

OUTR

43

OUTM

V

41

ref

AGND

7

V

CC

28

DGND27
MAD21

42

MHB429

Fig.1 Block diagram.

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

PINNING

SYMBOL PIN DESCRIPTION

OUTL 1 left audio output
OUTR 2 right audio output
CDE1 3 de-emphasis 1 capacitor
n.c. 4 not connected
n.c. 5 not connected
CDE2 6 de-emphasis 2 capacitor
AGND 7 analog ground
AF1I 8 audio 1 input
n.c. 9 not connected
AF1O 10 audio 1 output
n.c. 11 not connected
n.c. 12 not connected
AFR 13 AF1/2 signal return
LF1 14 loop filter 1
XTAL 15 4 MHz reference input
n.c. 16 not connected
n.c. 17 not connected
LF2 18 loop filter 2
n.c. 19 not connected
n.c. 20 not connected
MAD 21 programmable address bit

(module address)

n.c. 22 not connected

SYMBOL PIN DESCRIPTION

n.c. 23 not connected
CAF1 24 audio 1 (AF1) capacitor
IFINT 25 IF intercarrier input
CAF2 26 audio 2 (AF2) capacitor
DGND 27 digital ground
V

CC

SCL 29 serial clock input (I

28 supply voltage (+5 V)

2

C-bus)
SDA 30 serial data input/output (I
LPF 31 pilot loop filter
AF20 32 audio 2 output
AF2I 33 audio 2 input
CTRIG 34 trigger capacitor
CID 35 identification capacitor
n.c. 36 not connected
P1 37 output port 1
EXTM 38 external audio input mono
EXTR 39 external audio input right
EXTL 40 external audio input left
V

ref

41 reference voltage (1⁄2VCC)
P2 42 output port 2
OUTM 43 mono output
n.c. 44 not connected

2

C-bus)

1999 Apr 26 5

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

handbook, full pagewidth

ref

n.c.
44

OUTM
43

P2
42

V

41

EXTL

EXTR

403938

EXTM

P1
37

n.c.
36

CID
35

CTRIG
34

OUTL

OUTR

CDE1

n.c.
n.c.

CDE2

AGND

AF1I

n.c.

AF1O

n.c.

22
n.c.

33
32
31
30
29
28
27
26
25
24
23

MHB430

AF2I
AF2O
LPF
SDA
SCL

V

CC

DGND
CAF2
IFINT
CAF1
n.c.

1
2
3
4
5
6
7
8

9
10
11

12

13

n.c.

AFR

14
LF1

TDA9873H

15

16
n.c.

XTALI

17
n.c.

18

LF2

19
n.c.

20
n.c.

21

MAD

Fig.2 Pin configuration.

1999 Apr 26 6

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

FUNCTIONAL DESCRIPTION
FM demodulators

The FM demodulators are Narrow-Band PLLs (NBPLLs)
with external loop filters, to provide the required selectivity.
To achieve good selectivity, linear Phase Detectors (PDs)
and constant input levels are required. The intercarrier
signal from the input terminal is fed via high-pass filters
and gain controlled amplifiers to the phase detectors.
A carrier cancellation circuit placed before the amplifier for
the second PLL is used to reduce the first sound carrier.
The PD output signals control the integrated relaxation
oscillators via the loop filters. The frequency range is
approximately 4 to 7 MHz. As a result of locking, the
oscillator frequency tracks with the modulation of the input
signal and the oscillator control voltages are
superimposed by the AF voltages. Using this method, the
FM-PLLs operate as FM demodulators. The AF voltages
are present at the loop filters and fed via buffers with 0 dB
gain to the audio amplifiers. The supported standards and
their characteristics are given in Table 1.

Digital acquisition help

A narrow-band PLL requires a measure to lock to the
wanted input signal. Each relaxation oscillator of the three
integrated PLLs (1st and 2nd sound carriers and pilot
carrier) has a wide frequency range. To guarantee correct
locking of the PLL with respect to the catching range, the
digital acquisition help provides individual control until the
VCO frequency is within the standard and PLL dependent
lock-in window, related to the standard dependent carriers.
It ensures that the oscillator frequency of the FM-PLL is
within ±225 kHz of the sound carrier to be demodulated.
The pilot carrier frequency window is ±150 Hz.

The working principal of the digital acquisition help is as
follows: The VCOs are connected, one at a time, to a
down-counter. The counter start value is standard
dependent and predefined for each of the three PLLs.
After a given counting time the stop value of the
down-counter is probed.

In an endless circle the VCO of the next PLL will be
connected to the down-counter and the described
procedure starts again.

The whole tracing as well as the counting time itself is
derived from the external frequency reference. The cycle
time is 256 µs.

Auto mute

If a sound carrier is missed, acquisition pulses are
generated when the NBPLL frequency leaves the window
edges. To avoid noise at the audio output, an I2C-bus
switchable mute-enable stage is built in. If auto mute is
enabled via the I
after the first acquisition pulse. If a sound carrier occurs
(no further acquisition pulses), the mute stage
automatically returns to active mode after 40 ms.

If the 1st sound carrier is not present, the 2nd audio
channel will also be muted.

Audio preamplifier

The AF preamplifiers are operational amplifiers with
internal feedback, high gain and high common mode
rejection. The AF voltages from the PLL demodulators
(small output signals) are amplified by approximately
34 dB. Using a DC operating point control circuit, the AF
amplifiers are decoupled from the PLL DC voltage.
The amplified AF signals are available at the output
terminals and fed via external decoupling capacitors to the
stereo decoder input terminals.

Stereo decoder

The input circuit incorporates a soft-mute stage which is
controlled by the FM-PLL acquisition circuit. The auto
mute function can be disabled via the I

The AF output voltage is 500 mV (RMS) for 54%
modulation, clipping therefore may occur at high
over-modulation. If more headroom is required the input
signal can be attenuated by 6 dB via the I2C-bus.

2

C-bus, the circuit mutes immediately

2

C-bus.

If the stop value is lower (higher) than the expected value
range, the VCO frequency is higher (lower) than the lock-in
window. A negative (positive) control current is injected
into the loop filter for a short time, thereby decreasing
(increasing) the VCO frequency by a proportional value.

If the stop value meets the expected value range, the VCO
frequency is within the defined lock-in window and no
control current is injected into the loop filter.

1999 Apr 26 7

A stereo adjustment (see Fig.6) is incorporated to correct
the FM demodulator output voltage spread, see Table 19.
If no I2C-bus adjustment is required (potentiometer
adjustment or no adjustment) the default value should be
0 dB for B/G, M and D/K (2) standard. For the standards
D/K (1) and D/K (3) the 2nd sound carrier frequency is
below the1st sound carrier which results in a lower AF
output level for the 2nd sound carrier. In this state, a gain
of +0.1 dB for D/K (1) and +0.2 dB for D/K (3) is preferred.

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

In the following dematrix, the modes stereo, mono and
dual are processed for the different standards. The 6 dB
level difference between B/G and M standard is
automatically compensated in the dematrix, therefore no
further level adaption is needed.

De-emphasis is performed by two RC low-pass filter
networks with internal resistors and external capacitors.
The time constant is automatically switched to 50 µs or
75 µs according to the chosen standard.

Due to some frequency response peaking of the FM
demodulation, compensation is necessary. This is done by
having a slightly larger time constant for the de-emphasis.

All other settings such as AF switch, stereo channel
adjustment values or default corrections have to be
controlled via the I2C-bus depending on the identification
or user definition.

AF switch

The circuit incorporates a single stereo and mono AF
output. Using rail-to-rail operational amplifiers, the clipping
level is set to 1.4 V (RMS) for V

CC

=5V.

As well as the internal stereo decoder output signal, one
external stereo and one mono input can be switched to the
AF outputs. Both the mono and stereo outputs can be
switched independent of the internal or external sources,
see Tables 15 and 25. Fig.6 shows the switch
configurations.

A nominal gain of 0 dB for the signals from the external
inputs to the outputs is built-in.

Stereo/dual sound identification

The pilot signal is fed to the input of a NBPLL. The PLL
circuit generates the synchronized pilot carrier. This carrier
is used for the synchronous AM-demodulation to get the
low-pass filtered identification signal.

A Schmitt trigger circuit performs pulse shaping of the
identification signal when the signal level is higher than the
Schmitt trigger threshold. For smaller signal levels there is
no AC output signal, thus protecting against
mis-identification caused by spurious signal components.

The identification stages consist of two digital PLL circuits
and digital integrators to generate the stereo or dual sound
identification bits, which can be read out via the I

2

C-bus.

A 4 MHz crystal oscillator provides the reference clock
frequency. The corresponding detection bandwidth is
larger than ±50 Hz for the pilot carrier signal, so that f

pilot

variations from the transmitter can be tracked in the event
of missing synchronization with the horizontal frequency
fH. However, the detection bandwidth for the identification
signal is limited to approximately ±1 Hz for high
identification reliability.

2

C-bus transceiver

I

The TDA9873H is microcontroller controlled via a 2-wire
I2C-bus.

Two wires, serial data (SDA) and serial clock (SCL) carry
information between the devices connected to the bus.

The TDA9873H has an I2C-bus slave transceiver with
auto-increment.

To avoid conflicts in applications with other ICs providing
similar or complementary functions, two slave addresses
are available, selected on the pin MAD. A slave address is
sent from the master to the slave receiver.

In the TV sound processor family several devices are
available. To identify the TDA9873H device, the master
sends a slave address with R/W bit = 0. The slave then
generates an acknowledge and the master sends the data
subaddress 254 to the slave, followed by an acknowledge
from the slave to the master. The master then sends the
slave address with R/W bit = 1. The slave then transmits
the device identification code 80H to the master, followed
by an acknowledge NOT and a STOP condition generated
by the master.

Control ports

Two digital open-collector output ports P1 and P2 provide
external switching functions in the receiver front-end or
IF demodulators. The ports are controlled by the I

2

C-bus

(see Tables 22 and 23) and are freely programmable.

1999 Apr 26 8

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

Power supply

The different supply voltages and currents required for the
analog and digital circuits are derived from two internal
band gap reference circuits. One of the band gap circuits
internally generates a voltage of approximately 2.4 V,
independent of the supply voltage and temperature.
A voltage regulator circuit, connected to this voltage,
produces a constant voltage of 3.55 V which is used as an
internal reference voltage. The AF reference voltage V

1

⁄2VCC. Good ripple rejection is achieved with the external

capacitor C

= 100 µF (16 V) in combination with an

ref

ref

internal resistor at pin 6. No additional DC load for1⁄2V

Power-on reset
When a power-on reset is activated by switching on the

supply voltage or because of a supply voltage breakdown,
the 117/274 Hz DPLL, 117/274 Hz integrator and the
registers will be reset. Both AF channels (main and mono)
are muted. The ports are in position HIGH. Gain stereo
adjustment is 0 dB. Auto mute is active. For detailed
information see Table 12.

is

CC

is allowed.
Analog ground (AGND, pin 7) and digital ground

(DGND, pin 27) should be connected directly to the IC.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

supply voltage (pin 28) maximum chip

0 6.8 V
temperature of
125 °C; note 1

V

T
T
V

i

stg
amb
es

input voltage at:

pins 1 to 28 and 31 to 44 0 V
pins 29 to 30 −0.3 V

CC
CC

V

V
storage temperature −25 +150 °C
operating ambient temperature −20 +70 °C
electrostatic handling note 2 −150 +150 V

note 3 −2500 +2500 V

Notes

1. I

= 60 mA; T

CC

=70°C; R

amb

th(j-a)

= 70 K/W.

2. Machine model class B: C = 200 pF; L = 0.75 µH; R = 0 Ω.

3. Human body model class B: C = 100 pF; R = 1.5 kΩ.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 70 K/W

1999 Apr 26 9

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

CHARACTERISTICS

V

=5V; T

CC

f

= 1 kHz, L = R, stereo mode); input level for first SC V

mod

of Figs 7 and 8; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pin 28)

V

CC

I

CC

FM-PLL demodulator (pin 25); notes 1 to 5
V

i(FM)(rms)

V

i(vid)(p-p)

R

i

f

i(FM)

∆f

FM

∆f

AF

α

AM

K

O(FM)

K

D(FM)

V

CAF

=25°C; B/G standard (f

amb

= 5.5 MHz, f

SC1

= 5.742 MHz, SC1/SC2= 7 dB, ∆fAF= 27 kHz,

SC2

i(FM)(rms)

=50mV; f

= 4.000 MHz; measured in test circuit

ref

supply voltage 4.5 5 6.6 V
supply current 40 60 75 mA

FM-PLL input sensitivity for
pull-in (RMS value)

FM-PLL input level for gain
controlled operation

1st sound carrier −−6mV
2nd sound carrier −−1mV
1st sound carrier; note 2 6 − 150 mV
2nd sound carrier; note 2 1 − 100 mV

(RMS value)
allowable interference video

level (peak-to-peak value)

see Fig.5

V

i(FM1)(rms)

V

i(FM1)(rms)

=6mV −−160 mV

= 150 mV −−2V
input resistance 4 5 6 kΩ
FM-PLL operating

frequencies (switchable)

1st sound carrier

M standard − 4.5 − MHz
B/G standard − 5.5 − MHz
I standard − 6.0 − MHz
D/K standard − 6.5 − MHz

2nd sound carrier

M standard − 4.72 − MHz
B/G standard − 5.74 − MHz
D/K (1) standard − 6.26 − MHz
D/K (2) standard − 6.74 − MHz
D/K (3) standard − 5.74 − MHz

frequency windows of digital
acquisition help

narrow; note 3 −±225 − kHz
wide; note 3 −±450 − kHz

frequency deviation THD < 1.5%; normal gain −−±62 kHz

THD < 1.5%; reduced gain −−±124 kHz

frequency deviation for safe
identification

AM suppression AM: f

VCC= 5 V; stereo: 1 kHz L,
400 Hz R

= 1 kHz; m = 0.3

mod

−−±125 kHz

40 46 − dB
referenced to 27 kHz
FM deviation

VCO steepness ∆fFM/∆V
phase detector steepness

∆I

/∆ϕ(VFM)

LF1,2

DC voltage at CAF1 and
CAF2

LF1,2

note 5 − 3.3 − MHz/V
note 5 − 4 −µA/rad

dependent on intercarrier
frequency f

FM

1.5 − 3.3 V

1999 Apr 26 10

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

B

AF(−3dB)

V

o(FM)(rms)

Audio processing (pins 1, 2, 8 and 33)

V

o(rms)

V

o(cl)(rms)

R

L

C

L

R

L(DC)

R

o

THD total harmonic distortion V

α

cs(AF)(stereo)

α

ct(AF)(dual)

α

mute(AF)

−3 dB audio frequency
bandwidth

measured at AF1O and
AF2O; see Figs 7 and 8

upper limit dependent on

65 80 − kHz

loop filter; note 5
lower limit dependent on

−−20 Hz

CAF; CAF= 470 nF; note 4

output level (RMS value) measured at

− 250 − mV

AF1O and AF2O

AF output level (RMS value) f

mod

= 300 Hz;
54% modulation;
switchable by I2C-bus;
note 6

normal gain 400 500 600 mV
reduced gain 200 250 300 mV

AF output clipping level

VCC= 5 V; THD = 1.5% 1400 −− mV

(RMS value)
allowable load resistor AC coupled 10 −− kΩ
allowable load capacitor −−1.5 nF
allowable DC load resistor 100 −− kΩ
output resistance 70 150 300 Ω

= 0.5 V; fAF= 1 kHz − 0.2 0.5 %

o(rms)

AF channel separation (stereo
mode; complete signal path)

without alignment; note 7

B/G or M (Korea)

25 30 − dB

standard
D/K standard 23 27 − dB

potentiometer alignment;

35 40 − dB
B/G, M and D/K standard;
notes 7 and 8

I2C-bus alignment;
notes 7 and 9

B/G and D/K standard 40 45 − dB
M standard 35 40 − dB

AF crosstalk attenuation
(dual mode; complete signal
path)

A = 1 kHz; B = 400 Hz;
∆f=±50 kHz

complete signal path 65 70 − dB
stereo decoder only 70 75 − dB

mute attenuation of AF signal 75 80 − dB

1999 Apr 26 11

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

S/N

W

t

DEP(B/G)

t

DEP(M)

f

ro

PSRR power supply ripple rejection

R

i(AF1)

R

i(AF2)

External additional inputs (pins 38 to 40)

V

i(nom)(rms)

V

i(cl)(rms)

G

v

R

i

f

ro

α

ct(ext)

weighted signal-to-noise ratio
(complete signal path)

CCIR 468-4 weighted;
quasi peak; dual mode;
note 6

50 µs de-emphasis;

52 56 − dB

B/G, I and D/K standard
75 µs de-emphasis;

48 52 − dB

M standard

signal-to-noise ratio at
external AF with stereo
decoder only

de-emphasis time constant for

CCIR 468-4 weighted;

70 75 − dB
quasi peak;
V

= 500 mV

o(rms)

note 10; see Fig.3 − 50 −µs

B/G, D/K and I standard
de-emphasis time constant for

note 10; see Fig.3 − 75 −µs

M standard
roll-off frequency 470 nF at AF1I and AF2I;

without de-emphasis

low frequency (−3 dB) −−20 Hz
high frequency (−0.5 dB) 20 −− kHz

f

at OUTL and OUTR (overall
performance)

= 70 Hz;

ripple

V

ripple(p-p)

= 100 mV;

dual mode; see Fig.4

20 26 − dB

AF1I input resistance 32 40 48 kΩ
AF2I input resistance 32 40 48 kΩ

nominal input signal voltage

− 0.5 − V

(RMS value)
clipping voltage level

THD ≤ 1.5%; VCC= 5 V 1.4 −− V

(RMS value)
AF signal voltage gain

G=V

o/Vi

−1 0 +1 dB

input resistance 40 50 60 kΩ
roll-off frequency low frequency (−3 dB) −−20 Hz

high frequency (−0.5 dB) 20 −− kHz

AF crosstalk attenuation
(external input)

EXTL = 1 kHz;
EXTR = 400 Hz

70 75 − dB

Mono output OUTM (pin 43)

R

o

R

L

R

L(DC)

C

L

α

mute

output resistance 70 200 350 Ω
load resistor AC coupled 10 −− kΩ
allowable DC load resistor 100 −− kΩ
load capacitor −−1.5 nF
mute attenuation 60 −− dB

1999 Apr 26 12

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Pilot processing (pin 31)

f

pilot

pilot operating frequency
(3.5fH)

K

O(pilot)

K

D(pilot)

∆f

SC2(pilot)

VCO steepness ∆f
phase detector steepness

∆I

/∆ϕ(pilot)

LPF

second sound carrier pilot
frequency deviation

m

AM(pilot)

pilot AM modulation depth 25 50 75 %

Identification (pins 34 and 35)

f

LP(CID)

low-pass frequency response
at pin CID

f

stereo

identification operating
frequencies

f

stereo(h)

f

dual

f

dual(h)

t

ident(on)

total identification time on for
identification mode change

t

ident(off)

total identification time off for
identification mode change

∆f

ident

C/N

pilot

identification window width normal mode; note 13 − 2 − Hz

pilot sideband carrier-to-noise
ratio for start of identification

f

det

pull-in frequency range of
identification PLL (referred to
f

= 117.48 Hz and

stereo

f

= 274.12 Hz)

dual

pilot

/∆V

fH1= 15625 Hz − 54688 − Hz
f

= 15734 Hz − 55070 − Hz

H2

note 11 − 26 − kHz/V

LPF

∆f

window ±150 Hz;

pilot

− 2 −µA/rad

note 11
unmodulated pilot 1.5 2.5 3.5 kHz

−3 dB point 450 600 750 Hz

stereo; B/G and
D/K standard;1⁄

stereo; M standard;1⁄

133fH1

105fH2

dual; B/G and D/K standard;

1

⁄57f

H1

dual; M standard;1⁄57f

H2

− 117.48 − Hz

− 149.85 − Hz

− 274.12 − Hz

− 276.04 − Hz

normal mode; note 12 0.35 − 2s
fast mode; note 12 0.1 − 0.5 s
normal mode; note 12 0.6 − 1.6 s
fast mode; note 12 0.15 − 0.4 s

fast mode; note 13 − 8 − Hz

− 33 − dBc/Hz

normal mode lower side −0.63 −−0.63 Hz
normal mode upper side 0.63 − 0.63 Hz
fast mode lower side −2.05 −−2.05 Hz
fast mode upper side 2.05 − 2.05 Hz

Reference input (operation as crystal oscillator; pin 15)

f

sr(xtal)

series resonant frequency of
crystal

fundamental mode;
CL= 20 to 30 pF during
crystal production

∆f

w(max)

allowed maximum spread of
oscillator working frequency

over operating temperature
range including ageing and
influence of drive circuit;
note 3

∆f
∆f

R

R
d

s(eq)

cutting frequency tolerance −−±50 × 10
frequency drift −−±50 × 10
equivalent crystal series

resistance

1999 Apr 26 13

− 4.0 − MHz

−−±200 × 10−6−

−6

−

−6

−

− 60 200 Ω

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R

s(um)

Reference input (operation as input terminal; pin 15)

f

ω

V

I

R

i

∆f

ref

V

ref(rms)

V

o(ref)

C

K

2

I

C-bus transceiver (pins 29 and 30); note 15

f

clk

V

IH

V

IL

I

IH

I

IL

V

OL

I

o(sink)

I

o(source)

Port outputs P1 and P2 (open-collector outputs; pins 37 and 42)

V

OL

I

o(p)

Power-on reset

V

CC(sr)

V

CC(er)

crystal series resistance of

2 × R

−− Ω

s(eq)

unwanted mode

working frequency − 4 − MHz
DC input voltage 2.3 2.6 2.9 V
input resistance 2.5 3.0 3.5 kΩ
tolerance of reference

notes 3 and 14 −−±300 × 10−6−

frequency
amplitude of reference signal

operation as input terminal 80 − 400 mV

source (RMS value)
output resistance of

−−4.7 kΩ

reference source
decoupling capacitance to

operation as input terminal 22 100 − pF

external reference source

clock frequency 0 − 100 kHz
HIGH-level input voltage 3 − V

CC

V
LOW-level input voltage −0.3 − +1.5 V
HIGH-level input current −10 − +10 µA
LOW-level input current −10 − +10 µA
LOW-level output voltage IOL=3mA −−0.4 V
output sink current VCC=0V −−10 µA
output source current VCC=0V −−10 µA

LOW-level output voltage Io= 1 mA (sink) −−0.3 V
port output sink current port low −−1mA

supply voltage for start of

decreasing supply voltage 2.5 3 3.5 V

reset
supply voltage for end of reset increasing supply voltage;

−−4.5 V
I2C-bus transmission
enabled

Notes

1. Input level for IF intercarrier from an external generator with 50 Ω source impedance, f

= 400 Hz, 27 kHz deviation

mod

of audio references: level for SC1 50 mV (RMS), SC1/SC2= 7 dB. S/N and THD measurements are taken at 50 µs
de-emphasis.

2. For higher input voltages a series resistor connected to pin 25 is recommended.

3. The tolerance of the reference frequency determines the accuracy of the FM-demodulator centre frequencies,
maximum FM deviation, pilot window width and pilot window mid-frequency error.

4. The lower limit of audio bandwidth depends on the value of the capacitors at pins 24 and 26. A value of CAF= 470 nF
leads to f

AF(−3dB)

< 20 Hz and a value of CAF= 220 nF leads to f

AF(−3dB)

<40Hz.

1999 Apr 26 14

Philips Semiconductors Product specification



Multistandard dual carrier stereo sound decoder TDA9873H

5. Approximate calculation of the FM-PLL loop filter can be done using the following formula:

K

B

L3dB–()

with K

1

=

------ ­2π

= VCO steepness or

O

KD= phase detector steepness
R = loop resistor

= series capacitor

C

S

C

= parallel capacitor

P

B
Example: B

= loop bandwidth for −3 dB.

L(−3dB)

L(−3dB)

6. S/N decreases by 4 dB if no 2nd sound carrier is present; auto mute enabled.
Condition for B/G, I and D/K standard: V
Condition for M standard: VCC=5V and ∆f = 13.5 kHz; 6 dB gain added internally, to compensate smaller deviation.

7. R modulated, L monitored. The I2C-bus stereo adjustment has to be set to a default value. For B/G, D/K (2) and
M standard the default is 0 dB, for D/K (1) standard 0.1 dB and for D/K (3) standard 0.2 dB.

8. Using potentiometer adjustment, the AF output voltage is reduced by 1.3 dB because of the series resistor
(see Fig.8).

9. Separate alignment for each standard necessary. Minimum value for D/K (3) standard is 37 dB.

10. Because the loop transfer function is not flat, the de-emphasis is superimposed by an amplitude response correction
that compensates for an influence from the FM demodulators.

11. Approximate calculation of the pilot PLL loop filter can be done using the following formula:

K

1

OKD

f

n

ϑ

B

L(−3dB)

---------------------=

------ ­2π

R

CK

--- ­2

≈ 1.89f

× K

The formulae are only valid under the condition: 0.5 ≤ϑ≤0.8
with K

= VCO steepness or

O

KD= phase detector steepness
R = loop resistor

C = loop capacitor

= natural frequency of PLL

f

n

B

= loop bandwidth for −3dB

L(−3dB)

ϑ= damping factor.
Example: B

L(−3dB)

×

OKD

--------------------- 1.55




C

P

rad

---------



V

–

---------------------------------------------------­4R

µA



---------



rad

1

2

KOKD× CP××

Hz



2π

-------



V

= 80 kHz: CS= 3.3 nF; CP= 680 pF; R = 5.6 kΩ.

= 5 V and ∆f = 27 kHz (m = 54%).

CC

×

C

×=

O

D

n

rad



---------



V

µA



---------



rad

Hz



2π

-------



V

= 544 Hz: C = 100 nF; R = 7.5 kΩ; ϑ = 0.67; fn= 288 Hz.

1999 Apr 26 15

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

12. The maximum total system identification time on for a channel change is equal to the maximum value of t
t

I2C read-out

t

ident(off)

. The maximum total system identification time off for a channel change is equal to the maximum value of

plus t

I2C read-out

. The fast mode is mainly for use during search tuning, program or channel select. If the

ident(on)

plus

channel is selected, the identification response should be switched to normal mode for improved reliability. However
due to the transition from fast to normal mode, the identification bits are not valid for one integrator period. Therefore
the transmitter mode detected during the fast mode must be stored before changing to the normal mode. The storage
must be kept for two seconds (maximum value of t

in the normal mode) from the moment of transition.

ident(on)

The identification can now operate in the normal mode until the next tuning action.

13. Identification window is defined as total pull-in frequency range (lower plus upper side) of identification PLL (steady
detection) plus window increase due to integrator (fluctuating detection).

14. Window width dependent on fω.

15. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz.
Information about the I2C-bus can be found in the brochure

“The I2C-bus and how to use it”

(order number 9398 393 40011).

Table 1 TV standard settings

STANDARD

f

SC1

(MHz)

f

SC2

(MHz)

PILOT

FREQUENCY

f

(kHz)

pilot

STEREO

IDENTIFICATION

FREQUENCY

f

(Hz)

stereo

DUAL

IDENTIFICATION

FREQUENCY

f

(Hz)

dual

DE-EMPHASIS

t

(µs)

DEP

M 4.5 4.724 55.0699 149.85 276.04 75
B/G 5.5 5.742 54.6875 117.48 274.12 50
I6−−−−50
D/K (1) 6.5 6.268 54.6875 117.48 274.12 50
D/K (2) 6.5 6.742 54.6875 117.48 274.12 50
D/K (3) 6.5 5.742 54.6875 117.48 274.12 50

1999 Apr 26 16

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

+3

handbook, full pagewidth

V

o(AF)
(dB)

+2

+1

0

−1

−2

10 10

Fig.3 Tolerance scheme of AF frequency response; de-emphasis with C

MHB431

R: −15%
C: −5%

R: +15%
C: +5%

2

3

10

4

10

DE1,CDE2

f

(Hz)

oAF

= 10 nF (±5%).

5

10

handbook, full pagewidth

VCC = 5 V

VCC = 5 V

TDA9873H

MHB432

at OUTR

V

PSRR 20

ripple

-------------------------------------- -log=
V

at V

ripple

CC

Fig.4 Ripple rejection condition.

1999 Apr 26 17

100 mV (f

ripple

t

= 70 Hz)

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

handbook, full pagewidth

SC1

7dB=

----------­SC2

video: colour-bar

V

i(vid)(p-p)

(V)

2

1

0.5

0.16
0 6 12 25 150

50

V

i(FM)(rms)

(mV)

SC1

Fig.5 Allowable interference video level.

MHB433

1999 Apr 26 18

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1999 Apr 26 19

book, full pagewidth

OUTL

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

AF1I

L + R

2

AF2I

L − R

2

, M, A

, BR,

0/−6 dB
+ MUTE

B5, B7

+

acquisition

0/−6 dB
+ MUTE

stereo

separation

adjust

−0.6 to +0.7 dB

STANDARD

DEPENDENT

DE-MATRIXING

B4 = 0

B4 = 1

(L)

(R)

B4 = 1

B4 = 0

0/6 dB

6 dB

for

standard M

0/6 dB

1
2
3
4
5
6

6
5
4
3
2
1

d

SWITCH

+

d

MHB434

OUTM

(E3, E4, E5)

EXTM
EXTL

EXTR

6 dB

CDE1

DE-EMPHASISDE-MATRIXLEVEL + STEREO ADJUST

1

S

S is open

for

standard M

S

2

CDE2

1
2
3
4
5
6

(mute)

6
5
4
3
2
1

d

6 dB

d = 6 dB attenuation

OUTR

Example: For stereo mode (B4 = 1), OUTL is switched to position 4 and OUTR switched to position 5. For mono mode (B4 = 0), OUTL and OUTR are both switched to position 4.
This means: For mono/stereo switching, not only B4 but also the switch (stereo and mono output) must be set (see Tables 15 and 25).
Stereo output: internal/external source: B0, B1; output switching: B2, B3.

Fig.6 Audio part.

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

I2C-BUS PROTOCOL

2

C-bus format to read (device identification code)

I

S SLAVE ADDRESS R/

W = 0 A SUBADDRESS A S SLAVE ADDRESS R/W = 1 A DATA AN P

Note

1. This data word H80 (device identification code) is read from the subaddress 254 which is set in the last write transfer.

Table 2 Explanation of I

2

C-bus format to read (device identification code)

NAME DESCRIPTION

S START condition; generated by the master
SLAVE ADDRESS 101 101 1; pin MAD not connected (standard)

101 101 0; pin MAD connected to ground (pin programmable)

R/

W logic 0 (write); generated by the master

logic 1 (read); generated by the master
A acknowledge; generated by the slave
SUBADDRESS 111 111 10 (254)
DATA slave transmits the device identification code 80H
AN acknowledge not; generated by the master
P STOP condition; generated by the master

2

C-bus format to read (slave transmits data)

I

S SLAVE ADDRESS R/

W = 1 A DATA AN P

2

Table 3 Explanation of I

C-bus format to read (slave transmits data)

NAME DESCRIPTION

S START condition; generated by the master
SLAVE ADDRESS 101 101 1; pin MAD not connected (standard)

101 101 0; pin MAD connected to ground (pin programmable)
R/

W logic 1 (read); generated by the master
A acknowledge; generated by the slave
DATA slave transmits an 8-bit data word
AN acknowledge not; generated by the master
P STOP condition; generated by the master

Table 4 Definition of the transmitted byte after read condition

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 Y Y DS ST PONR

1999 Apr 26 20

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

Table 5 Bit functions Table 4

BITS FUNCTION

PONR power-on reset; PONR = 1, power-on reset detected
ST stereo sound; ST = 1, stereo sound identified
DS dual sound; DS = 1, dual sound identified
Y indefinite

Table 6 Interpretation of identification bits

ST DS FUNCTION

0 0 mono
0 1 dual sound
1 0 stereo sound
1 1 incorrect identification

Table 7 Power-on reset

PONR FUNCTION

0 after successful reading of the status register
1 after power-on reset or after supply breakdown

If the master generates an acknowledge not and a STOP condition when it has received the data word READ, the master
terminates the bus transfer. On the other hand, if the master generates an acknowledge then the slave started a second
transfer with the READ byte and so on until the master generates an acknowledge not and STOP condition.

2

I

C-bus format to write (slave receives data)

S SLAVE ADDRESS R/

2

Table 8 Explanation of I

NAME DESCRIPTION

S START condition
SLAVE ADDRESS 101 101 1; pin MAD not connected (standard)

R/

W logic 0 (write)
A acknowledge; generated by slave
SUBADDRESS see Table 9
DATA note 1; see Table 10
P STOP condition

C-bus format to write (slave receives data)

W = 0 A SUBADDRESS A DATA A P

101 101 0; pin MAD connected to ground (pin programmable)

Note

1. If more than 1 byte of DATA is transmitted, auto-increment is performed, starting from the transmitted subaddress
and auto-increment of the subaddress is performed in accordance with the order of Table 9.

1999 Apr 26 21

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

Table 9 Subaddress definition (second byte after slave address)

FUNCTION

Switching 00000000
Adjust/standard 00000001
Port 00000010

Note

1. Significant subaddress bit.

Table 10 Data definition (third byte after slave address)

FUNCTION

Switching data B7 B6 B5 B4 B3 B2 B1 B0
Adjust/standard data C7 C6 C5 C4 C3 C2 C1 C0
Port data 0 0 E5 E4 E3 E2 E1 E0

Table 11 Bit functions in Table 10

BITS FUNCTION

B0 and B1 signal source select; see Table 13
B2 and B3 output signal select; see Table 15
B4 stereo setting bit; see Table 15
B5 output level switching; see Table 16
B6 mute bit; see Table 17
B7 auto mute enable; see Table 18
C0 to C3 stereo adjust; see Table 19
C4 to C6 standard switching; see Table 20
C7 identification response time; see Table 21
E0 port 1; see Table 22
E1 port 2; see Table 23
E2 test mode; see Table 24 (not for customer)
E3 to E5 mono output setting; see Table 25

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

(1)

Table 12 Data setting of third byte after power-on reset; see note 1

FUNCTION

Switching data 1 1 XXXXXX
Adjust/standard data 00000110
Port data 00111011

Note

1. X = don’t care.

1999 Apr 26 22

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

Table 13 Source switching; see Table 10

SIGNAL SOURCE B1 B0

Internal 0 0
External stereo 1 0
External mono 1 1

Table 14 Stereo decoder outputs (CDE1, CDE2); see Table 10

TRANSMISSION MODE OUTPUTS B4

Stereo stereo 1
Stereo mono 0
Mono mono 0
Dual dual 0

Table 15 Mode and output switching; data byte to select AF inputs and AF outputs

TRANSMISSION MODE SELECTED MODE OUTL OUTR B4 B3 B2

Mono M M M 0 0 1
Stereo forced mono M M 0 0 1
Stereo ST L R 1 0 0

RL111

Dual AB A B 0 0 0

AA AA001
BB BB010

BA BA011
External mono EXTM EXTM EXTM 0 0 0
External stereo EXTL, EXTR EXTL EXTR 0 0 0

EXTL, EXTL EXTL EXTL 0 0 1

EXTR, EXTR EXTR EXTR 0 1 0

EXTR, EXTL EXTR EXTL 0 1 1

Table 16 Output level switching; see Table 10

OUTPUT LEVEL B5

Normal gain 1
Reduced gain 0

1999 Apr 26 23

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

Table 17 Mute switching of AF outputs; see Table 10

OUTL, OUTR B6

Not muted 0
Muted 1

Table 18 Auto mute activating; see Table 10

AUTO MUTE B7

Disabled 0
Active 1

Table 19 Stereo adjustment, gain adjust in R channel;

see Table 10

GAIN STEREO

ADJUSTMENT (dB)

−0.6 0000

−0.5 0001

−0.4 0010

−0.3 0011

−0.2 0100

−0.1 0101

0.0 0110
+0.1 0111
+0.2 1000
+0.3 1001
+0.4 1010
+0.5 1011
+0.6 1100
+0.7 1101

C3 C2 C1 C0

DATA

Table 21 Identification response time; see Table 10

FUNCTION DATA

RESPONSE TIME C7

Normal 0
Fast 1

Table 22 Port 1 output; see Table 10

PORT 1 E0

LOW 0
HIGH 1

Table 23 Port 2 output; see Table 10

PORT 2 E1

LOW 0
HIGH 1

Table 24 Test mode; note 1; see Table 10

TEST MODE E2

Off 0
On 1

Note

1. Not for customer; for Philips Semiconductors only.

Table 20 Standard switching; see Table 10

STANDARD C6 C5 C4

B/G 0 0 0
M 001
D/K (1) 0 1 0
D/K (2) 0 1 1
D/K (3) 1 0 0
I 101

1999 Apr 26 24

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

Table 25 Mono output; see Table 10

TRANSMISSION MODE STEREO DECODER OUTM E5 E4 E3 B4

Mono mono mono 0000
Stereo forced mono mono 0000
Dual dual dual A 0000
Dual dual dual B 0010
Stereo stereo mono 0101

−−EXT M 0 1 1 −

−−EXT L 1 0 0 −

−−EXT R 1 0 1 −

−−EXT L/R;

−−mute 1 1 1 −

1

⁄2(L+R) 110−

1999 Apr 26 25

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

APPLICATION INFORMATION

handbook, full pagewidth

2.2 µF

2.2 µF

OUTR

10 nF

10 nF

AGND

470

nF

OUTL

CDE1

n.c.

n.c.

CDE2

AF1I

n.c.

AF1O

P2

V

CC

4.7
kΩ

2.2
µF

n.c. OUTM P2Vref EXTL EXTR EXTM P1 CID CTRIG

44 394243 41 3435

1

2

3

4

5

6

7

8

9

10

47
µF

EXTIN

470
nF

40

TDA9873H

470
nF

V

4.7
kΩ

470
nF

38 37

P1

CC

n.c.

36

4.7
nF

470
nF

470 nF

AF2I

33

AF2O

32

100 nF

470 nF

470 nF

47 pF

470 nF

7.5 kΩ

intercarrier

SDA

SCL

V

CC

IF

LPF

31

SDA

30

SCL

29

V

CC

28

DGND

27

CAF2

26

IFINT

25

CAF1

24

n.c.

11

12

n.c.

680 pF

14

13

LF1

AFR

5.6 kΩ

3.3 nF

15

XTAL

16

17

n.c.

n.c.

5.6 kΩ

3.3 nF

Fig.7 Application circuit without potentiometer alignment.

1999 Apr 26 26

n.c.

23

18

LF2

20

n.c.19n.c.

680 pF

22

21

n.c.

MAD

MHB435

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

handbook, full pagewidth

2.2 µF

OUTL

2.2 µF

OUTR

10 nF

CDE1

10 nF

CDE2

AGND

470

nF

AF1O

n.c.

n.c.

AF1I

n.c.

P2

V

CC

4.7
kΩ

2.2
µF

n.c. OUTM P2Vref EXTL EXTR EXTM P1 CID CTRIG

44 394243 41 3435

1

2

3

4

5

6

7

8

9

10

47
µF

EXTIN

470
nF

40

TDA9873H

470
nF

V

4.7
kΩ

470
nF

38 37

P1

CC

n.c.

36

4.7
nF

470
nF

470 nF

AF2I

33

AF2O

32

100 nF

470 nF

470 nF

47 pF

470 nF

7.5 kΩ

SDA

SCL

V

CC

IF

intercarrier

LPF

31

SDA

30

SCL

29

V

CC

28

DGND

27

CAF2

26

IFINT

25

CAF1

24

n.c.

11

12

n.c.

680 pF

14

13

LF1

AFR

5.6 kΩ

3.3 nF

15

XTAL

16

17

n.c.

n.c.

5.6 kΩ

3.3 nF

Fig.8 Application circuit with potentiometer alignment.

1999 Apr 26 27

n.c.

23

18

LF2

20

n.c.19n.c.

680 pF

21

MAD

22

n.c.

4.7
kΩ

10 kΩ

MHB436

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

Fig.9 Pin 1; OUTL and pin 2; OUTR.

10 kΩ

10 kΩ

1, 2

+

2.5 V

handbook, halfpage

+

8 kΩ

MHB437

3, 6

2.5 V

15 kΩ

7.5 kΩ

MHB438

Fig.10 Pin 3; CDE1 and pin 6; CDE2.

handbook, halfpage

8, 33

+

50 kΩ

2.5 V

MHB439

Fig.11 Pin 8; AF1I and pin 33; AF2I.

1999 Apr 26 28

handbook, halfpage

Fig.12 Pin 10; AF1O and pin 32; AF2O.

10, 32

+

240 µA

5 kΩ

34 kΩ

MHB440

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

handbook, halfpage

13

3 V

+

10 kΩ

5 kΩ

1.25 kΩ

80 µA

Fig.13 Pin 13; AFR.

+

7.5 µA

MHB441

handbook, halfpage

Fig.14 Pin 14; LF1 and pin 18; LF2.

+

2 kΩ

2 kΩ

14, 18

1.5 V

23 kΩ

MHB442

handbook, halfpage

15

+

1.5 kΩ

100 µA

MHB443

Fig.15 Pin 15; XTAL.

1999 Apr 26 29

handbook, halfpage

21

+

MHB444

Fig.16 Pin 21; MAD.

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

handbook, halfpage

Fig.17 Pin 24; CAF1 and pin 26; CAF2.

24, 26

2.5 V

handbook, halfpage

+

80
µA

25

3 V

+

5 kΩ

+

5 kΩ

500 µA

MHB446

MHB445

4.8 pF

4.8 pF

3.05 kΩ

3.3 kΩ30 kΩ

2 kΩ

Fig.18 Pin 25; IFINT.

handbook, halfpage

28

+

5 V

MHB447

Fig.19 Pin 28; VCC.

1999 Apr 26 30

handbook, halfpage

29

1.8 kΩ

2.5 V

MHB448

Fig.20 Pin 29; SCL.

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

handbook, halfpage

30

1.8 kΩ

2.5 V

MHB449

Fig.21 Pin 30; SDA.

handbook, halfpage

+

4

kΩ

kΩ

Fig.22 Pin 31; LPF and pin 35; CID.

31, 35

2.5 V

+

4

56

kΩ

2

kΩ

80
µA

MHB450

handbook, halfpage

34

2.5 V

+

56 kΩ

3.33 kΩ

MHB451

Fig.23 Pin 34; CTRIG.

1999 Apr 26 31

handbook, halfpage

37, 42

+

MHB452

Fig.24 Pin 37; P1 and pin 42; P2.

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

handbook, halfpage

38, 39, 40

1

+

25 kΩ

25 kΩ

MHB453

2

3

4

Fig.25 Pin 38; EXTM; pin 39; EXTR and pin 40;

EXTL.

handbook, halfpage

+

100 Ω

5.9 kΩ

Fig.26 Pin 41; V

MHB454

ref

41

6.8 kΩ

.

handbook, halfpage

+

8 kΩ

43

2.5 V

10 kΩ

10 kΩ

MHB455

Fig.27 Pin 43; OUTM.

1999 Apr 26 32

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm

c

y

X

33 23

34

pin 1 index

44

1

Z

22

E

e

w M

b

p

12

11

A

H

E

E

A

2

A

A

1

detail X

L

L

p

SOT205-1

(A )

3

θ

Z

e

w M

b

p

D

H

D

D

B

v M

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.60

0.25

0.05

2.3

2.1

0.25

UNIT A1A2A3b

cE

p

0.50

0.25

0.35

0.14

(1)

(1) (1)(1)

D

14.1

13.9

eH

H

14.1

13.9

19.2

1

18.2

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

SOT205-1

IEC JEDEC EIAJ

133E01A

REFERENCES

1999 Apr 26 33

v M

D

A

B

E

19.2

18.2

LL

p

2.0

1.2

0.152.35 0.10.3

EUROPEAN

PROJECTION

Z

D

2.4

1.8

Zywv θ

E

o

2.4

7

o

1.8

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Apr 26 34

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1999 Apr 26 35

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2

PURCHASE OF PHILIPS I

C COMPONENTS

2

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the

1999 Apr 26 36

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

NOTES

1999 Apr 26 37

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

NOTES

1999 Apr 26 38

Philips Semiconductors Product specification

Multistandard dual carrier stereo sound decoder TDA9873H

NOTES

1999 Apr 26 39

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1999 SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545004/00/01/pp40 Date of release: 1999 Apr 26 Document order number: 9397 750 04818