Datasheet TDA9870A Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA9870A

Digital TV Sound Processor
(DTVSP)

Product specification
Supersedes data of 1998 Aug 10
File under Integrated Circuits, IC02

1999 Dec 20

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

CONTENTS

1 FEATURES

1.1 Demodulator and decoder section

1.2 DSP section

1.3 Analog audio section
2 GENERAL DESCRIPTION

2.1 Supported standards
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING
6 FUNCTIONAL DESCRIPTION

6.1 Demodulator and decoder section

6.2 Description of the DSP

6.3 Analog audio section
7 LIMITING VALUES
8 THERMAL CHARACTERISTICS
9 CHARACTERISTICS

10 I2C-BUS CONTROL

10.1 Introduction

10.2 Power-up state

10.3 Slave receiver mode

10.4 Slave transmitter mode

10.5 Expert mode
11 I2S-BUS DESCRIPTION
12 APPLICATION INFORMATION
13 PACKAGE OUTLINES
14 SOLDERING

14.1 Introduction

14.2 Through-hole mount packages

14.3 Surface mount packages

14.4 Suitability of IC packages for wave,reflow and
dipping soldering methods

15 DEFINITIONS
16 LIFE SUPPORT APPLICATIONS
17 PURCHASE OF PHILIPS I2C COMPONENTS

1999 Dec 20 2

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

1 FEATURES

1.1 Demodulator and decoder section

• Sound IF (SIF) input switch e.g. to select between
terrestrial TV SIF and SAT SIF sources

• SIF AGC with 24 dB control range

• SIF 8-bit Analog-to-Digital Converter (ADC)

• Two-carrier multistandard FM demodulation

(B/G, D/K and M standard)

• Decoding for three analog multi-channel systems
(A2, A2+ and A2*) and satellite sound

• Programmableidentification(B/G, D/K and M standard)
and different identification times.

1.2 DSP section

• Digital crossbar switch for all digital signal sources and
destinations

• Control of volume, balance, contour, bass, treble,
pseudo stereo, spatial, bass boost and soft mute

• Plop-free volume control

• Automatic Volume Level (AVL) control

• Adaptive de-emphasis for satellite

• Programmable beeper

• Monitor selection for FM/AM DC values and signals,

with peak detection option

• I2S-bus interface for a feature extension (e.g. Dolby
surround) with matrix, level adjust and mute.

1.3 Analog audio section

• Analog crossbar switch with inputs for mono and stereo
(also applicable as SCART 3 input), SCART 1
input/output, SCART 2 input/output and line output

• User defined full-level/−3 dB scaling for SCART outputs

• Output selection of mono, stereo, dual A/B, dual A or

dual B

• 20 kHz bandwidth for SCART-to-SCART copies

• Standby mode with functionality for SCART copies

• DualaudioDigital-to-AnalogConverter (DAC)fromDSP

to analog crossbar switch, bandwidth of 15 kHz

• Dual audio ADC from analog inputs to DSP

• Two dual audio DACs for loudspeaker (Main) and

headphone (Auxiliary) outputs; also applicable for
L, R, C and S in the Dolby Pro Logic mode with feature
extension.

2 GENERAL DESCRIPTION

The TDA9870A is a single-chip Digital TV Sound
Processor (DTVSP) for analog multi-channel sound
systems in TV sets and satellite receivers.

2.1 Supported standards

The multistandard/multi-stereo capability of the
TDA9870A is mainly of interest in Europe, but also in
Hong Kong/Peoples Republic of China and South East
Asia.This includesB/G, D/K, I, M and Lstandard.Inother
application areas there exists only subsets of those
standard combinations otherwise only single standards
are transmitted.

M standard is transmitted in Europe by the American
Forces Network (AFN) with European channel spacing
(7 MHz VHF, 8 MHz UHF) and monaural sound.

Korea has a stereo sound system similar to Europe and is
supported by the TDA9870A. Differences include
deviation, modulation contents and identification. It is
based on M standard.

An overview of the supported standards and sound
systems and their key parameters is given in Table 1.

The analog multi-channel sound systems (A2, A2+
and A2*) are 2-Carrier Systems (2CS).

1999 Dec 20 3

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

2.1.1 ANALOG 2-CARRIER SYSTEMS

Table 1 Frequency modulation

STANDARD

SOUND

SYSTEM

CARRIER

FREQUENCY

(MHz)

FM DEVIATION (kHz) MODULATION BANDWIDTH/

DE-EMPHASIS

NOM. MAX. OVER SC1 SC2

(kHz/µs)

M mono 4.5 15 25 50 mono − 15/75
M A2+ 4.5/4.724 15 25 50

B/G A2 5.5/5.742 27 50 80

1

⁄2(L+R)1⁄2(L − R) 15/75 (Korea)

1

⁄2(L + R) R 15/50

I mono 6.0 27 50 80 mono − 15/50
D/K A2 6.5/6.742 27 50 80
D/K A2* 6.5/6.258 27 50 80

1

⁄2(L + R) R 15/50

1

⁄2(L + R) R 15/50

Table 2 Identification for A2 systems

PARAMETER A2/A2* A2+ (KOREA)

Pilot frequency 54.6875 kHz = 3.5 × line frequency 55.0699 kHz = 3.5 × line frequency
Stereo identification

frequency
Dual identification

frequency

117.5 Hz

274.1 Hz

line frequency

= 149.9 Hz

------------------------------------­133

line frequency

= 276.0 Hz

-------------------------------------

57

line frequency

=

------------------------------------­105

line frequency

=

------------------------------------­57

AM modulation depth 50% 50%

1999 Dec 20 4

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

2.1.2 SATELLITE SYSTEMS
An important specification for satellite TV reception is the

“Astra specification”

. The TDA9870A is suited for the reception

of Astra and other satellite signals.

Table 3 FM satellite sound

CARRIER

CARRIER TYPE

FREQUENCY

(MHz)

Main 6.50

(1)

MODULATION

INDEX

0.26 85 mono 15/50

Sub 7.02/7.20 0.15 50 m/st/d

MAXIMUM

FM DEVIATION

(kHz)

MODULATION

(3)

BANDWIDTH/

DE-EMPHASIS

(kHz/µs)

(2)

15/adaptive
Sub 7.38/7.56
Sub 7.74/7.92
Sub 8.10/8.28

Notes

1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received.

2. A de-emphasis of 60 µs, or in accordance with J17, is available.

3. m/st/d = mono, stereo or dual language sound.

4. Adaptive de-emphasis is compatible to transmitter specification.

3 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA9870A SDIP64 plastic shrink dual in-line package; 64 leads (750 mil) SOT274-1
TDA9870AH QFP64 plastic quad flat package; 64 leads (lead length 1.6 mm);

SOT393-1

body 14 × 14 × 2.7 mm

(4)

1999 Dec 20 5

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

4 BLOCK DIAGRAM

handbook, full pagewidth

9 (1)

P1

20 (12)

P2

SCL
SDA

SDI1
SDI2

SCK

WS

3 (59)

13 (5)

4 (60)
5 (61)

18 (10)
19 (11)
21 (13)

27 (19)
26 (18)
25 (17)
24 (16)
22 (14)
23 (15)

15 (7)
64 (56)
14 (6)
49 (41)
35 (27)
17 (9)
16 (8)

28 (20)
30 (22)

I2C-BUS

INTERFACE

IDENTIFICATION

CLOCK

PEAK

DETECTION

I2S-BUS

INTERFACE

DIGITAL
SUPPLY

TEST

MOL

ADDR1
ADDR2

XTALI

XTALO

SYSCLK

SDO1
SDO2

V

DDD1

V

DDD2

V

SSD1

V

SSD2

V

SSD3

V

SSD4

CRESET

TEST1
TEST2

The pin numbers given in parenthesis refer to the TDA9870AH version.

SIF2 SIF1

10 (2) 12 (4)

INPUT SWITCH

AGC, ADC

FM (AM)

DEMODULATION

A2/SATELLITE

DECODER

LEVEL

ADJUST

DIGITAL
SELECT

AUDIO PROCESSING

DAC (2)

(52)

(53)

60

61

MOR

AUXOL

ADC (2)

DAC (2)

DAC (2)

(50)
58

(49)
57

AUXOR

SUPPLY

SOUND IF

(SIF)

TDA9870A

(

TDA9870AH

ANALOG

CROSSBAR

SWITCH

SUPPLY

SCART,

DAC,
ADC

(63) 7

V
V
V
I

ref

DEC1
SSA1
ref1

(62) 6
(3) 11
(64) 8

)

(25) 33
(26) 34

(28) 36
(29) 37

(23) 31
(24) 32

(21) 29

(39) 47
(40) 48

(43) 51
(44) 52
(55) 63
(54) 62

(33) 41
(34) 42
(36) 44
(37) 45

(46) 54
(47) 55

(51) 59
(30) 38

(31) 39
(32) 40

(38) 46
(45) 53

(35) 43
(48) 56
(42) 50

MHB593

(57) 1
(58) 2

SCIR1
SCIL1
SCIR2
SCIL2
EXTIR
EXTIL
MONOIN

SCOR1
SCOL1
SCOR2
SCOL2
LOR
LOL

i.c.
i.c.
i.c.
i.c.
i.c.
i.c.

PCAPR
PCAPL

V

DDA

V

DEC2

V

ref(p)

V

ref(n)

V

ref2

V

ref3

V

SSA2

V

SSA3

V

SSA4

Fig.1 Block diagram.

1999 Dec 20 6

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

5 PINNING

SYMBOL

PIN

TDA9870A TDA9870AH

PIN

TYPE

(1)

DESCRIPTION

i.c. 1 57 − internally connected; note 2
i.c. 2 58 − internally connected; note 2
ADDR1 3 59 I I
SCL 4 60 I I
SDA 5 61 I/O I
V
V
I

ref

SSA1
DEC1

6 62 S supply ground 1; analog front-end circuitry
763−supply voltage decoupling 1; analog front-end circuitry
864−resistor for reference current generator; analog front-end circuitry

2

C-bus slave address input 1

2

C-bus clock input

2

C-bus data input/output

P1 9 1 I/O general purpose input/output pin 1
SIF2 10 2 I sound IF input 2
V

ref1

11 3 − reference voltage 1; analog front-end circuitry
SIF1 12 4 I sound IF input 1
ADDR2 13 5 I I
V
V

SSD1
DDD1

14 6 S supply ground 1; digital circuitry

15 7 S digital supply voltage 1; digital circuitry

2

C-bus slave address input 2

CRESET 16 8 − capacitor for Power-on reset
V

SSD4

17 9 S supply ground 4; digital circuitry
XTALI 18 10 I crystal oscillator input
XTALO 19 11 O crystal oscillator output
P2 20 12 I/O general purpose input/output pin 2
SYSCLK 21 13 O system clock output
SCK 22 14 I/O I
WS 23 15 I/O I
SDO2 24 16 O I
SDO1 25 17 O I
SDI2 26 18 I I
SDI1 27 19 I I
TEST1 28 20 I test pin 1; connected to V

2

S-bus clock input/output

2

S-bus word select input/output

2

S-bus data output 2 (I2S2 output)

2

S-bus data output 1 (I2S1 output)

2

S-bus data input 2 (I2S2 input)

2

S-bus data input 1 (I2S1 input)

for normal operation

SSD1

MONOIN 29 21 I audio mono input
TEST2 30 22 I test pin 2; connected to V

for normal operation

SSD1

EXTIR 31 23 I external audio input right channel
EXTIL 32 24 I external audio input left channel
SCIR1 33 25 I SCART 1 input right channel
SCIL1 34 26 I SCART 1 input left channel
V

SSD3

35 27 S supply ground 3; digital circuitry
SCIR2 36 28 I SCART 2 input right channel
SCIL2 37 29 I SCART 2 input left channel
V

DEC2

38 30 − supply voltage decoupling 2; audio analog-to-digital converter

circuitry

1999 Dec 20 7

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SYMBOL

V

ref(p)

PIN

TDA9870A TDA9870AH

39 31 − positive reference voltage; audio analog-to-digital converter

PIN

TYPE

(1)

DESCRIPTION

circuitry

V

ref(n)

40 32 − reference voltage ground; audio analog-to-digital converter

circuitry
i.c. 41 33 − internally connected; note 3
i.c. 42 34 − internally connected; note 4
V

SSA2

43 35 S supply ground 2; audio analog-to-digital converter circuitry
i.c. 44 36 − internally connected; note 4
i.c. 45 37 − internally connected; note 3
V

ref2

46 38 − reference voltage 2; audio analog-to-digital converter circuitry
SCOR1 47 39 O SCART 1 right channel output
SCOL1 48 40 O SCART 1 left channel output
V
V

SSD2
SSA4

49 41 S supply ground 2; digital circuitry

50 42 S supply ground 4; audio operational amplifier circuitry
SCOR2 51 43 O SCART 2 right channel output
SCOL2 52 44 O SCART 2 left channel output
V

ref3

53 45 − reference voltage 3; audio digital-to-analog converter and

operational amplifier circuitry

PCAPR 54 46 − post-filter capacitor pin right channel, audio digital-to-analog

converter

PCAPL 55 47 − post-filter capacitor pin left channel, audio digital-to-analog

converter

V

SSA3

56 48 S supply ground 3; audio digital-to-analog converter circuitry
AUXOR 57 49 O headphone (Auxiliary) right channel output
AUXOL 58 50 O headphone (Auxiliary) left channel output
V

DDA

59 51 S analog power supply voltage; analog circuitry
MOR 60 52 O loudspeaker (Main) right channel output
MOL 61 53 O loudspeaker (Main) left channel output
LOL 62 54 O line output left channel
LOR 63 55 O line output right channel
V

DDD2

64 56 S digital supply voltage 2; digital circuitry

Notes

1. Pin type: I = Input; O = Output; S = Supply.

2. Test pin: CMOS 3-state stage, pull-up resistor, can be connected to VSS.

3. Test pin: CMOS level input, pull-up resistor, can be connected to VSS.

4. Test pin: CMOS 3-state stage, can be connected to VSS.

1999 Dec 20 8

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

handbook, halfpage

i.c.
i.c.

ADDR1

SCL
SDA

V

SSA1

V

DEC1

I

ref
P1

SIF2

V

ref1

SIF1

ADDR2

V

SSD1

V

DDD1

CRESET

V

SSD4

XTALI

XTALO

P2

SYSCLK

SCK

WS
SDO2
SDO1

SDI2
SDI1

TEST1

MONOIN

TEST2

EXTIR

EXTIL

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

TDA9870A

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

MHB111

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

V

DDD2

LOR
LOL
MOL
MOR
V

DDA

AUXOL
AUXOR
V

SSA3

PCAPL
PCAPR
V

ref3

SCOL2
SCOR2
V

SSA4

V

SSD2

SCOL1
SCOR1
V

ref2

i.c.
i.c.
V

SSA2

i.c.
i.c.
V

ref(n)

V

ref(p)

V

DEC2

SCIL2
SCIR2
V

SSD3

SCIL1
SCIR1

Fig.2 Pin configuration (TDA9870A).

1999 Dec 20 9

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

handbook, full pagewidth

ref

I

64

DEC1VSSA1

V

63

62

SDA
61

SCL
60

ADDR1

i.c.

59

58

i.c.
57

DDD2

V

56

LOR
55

LOL
54

MOL
53

MOR
52

DDA

V

51

AUXOL

AUXOR

50

49

P1

1

SIF2

2

V

3

ref1

SIF1

4

ADDR2

V

V

CRESET

V

XTALO

SYSCLK

5
6

SSD1

7

DDD1

8
9

SSD4
XTALI

10
11

P2

12
13

SCK

14

WS

15

SDO2 33

16

17

SDO1

18

SDI2

19

SDI1

20

TEST1

21

22

TEST2

MONOIN

TDA9870AH

23

24

25

EXTIL

EXTIR

SCIR1

26

SCIL1

27

SSD3

V

28

SCIR2

29

SCIL2

30

DEC2

V

31

ref(p)Vref(n)

V

V

48

SSA3

PCAPL

47

PCAPR

46

V

45

ref3

SCOL2

44

SCOR2

43

V

42

SSA4

V

41

SSD2

SCOL1

40

SCOR1

39

V

38

ref2

i.c.

37

i.c.

36

V

35

SSA2

i.c.

34

i.c.

32

MHB594

Fig.3 Pin configuration (TDA9870AH).

1999 Dec 20 10

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

6 FUNCTIONAL DESCRIPTION

6.1 Demodulator and decoder section

6.1.1 SIF INPUT
Two input pins are provided: SIF1 e.g. for terrestrial TV

and SIF2 e.g. for a satellite tuner. For higher SIF signal
levels the SIF input can be attenuated with an internally
switchable−10 dB resistor divider. As nospecificfiltersare
integrated, both inputs have the same specification giving
flexibility in application. The selected signal is passed
through an AGC circuit and then digitized by an 8-bit ADC
operating at 24.576 MHz.

6.1.2 AGC
The gain of the AGC amplifier is controlled from the ADC

output by means of a digital control loop employing
hysteresis. The AGC has a fast attack behaviour to
prevent ADC overloads and a slow decay behaviour to
prevent AGC oscillations. For AM demodulation the AGC
must be switched off. When switched off, the control loop
is reset and fixed gain settings can be chosen
(see Table 14; subaddress 0).

The AGC can be controlled via the I2C-bus. Details can be
found in the I2C-bus register definitions (see Chapter 10).

6.1.3 MIXER
The digitized input signal is fed to the mixers, which mix

one or both input sound carriers down to zero IF. A 24-bit
control word for each carrier sets the required frequency.
Access to the mixer control word registers is via the
I2C-bus.

6.1.5 FM IDENTIFICATION
The identification of the FM sound mode is performed by

AM synchronous demodulation of the pilot signal and
narrow-band detection of the identification frequencies.
Theresultisavailableviathe I2C-businterface.Aselection
can be made via the I2C-bus for B/G, D/K and M standard
and for three different modes that represent different
trade-offs between speed and reliability of identification.

6.1.6 CRYSTAL OSCILLATOR
The circuitry of the crystal oscillator is fully integrated, only

the external 24.576 MHz crystal is needed (see Fig.10).

6.1.7 TEST PINS
Test pins TEST1 and TEST2 are active HIGH and in

normal operating mode of the device they are connected
to V
and are not available to customers. Without external
circuitry these pins are pulled down to LOW level with
internal resistors.

6.1.8 POWER FAIL DETECTOR
The power fail detector monitors the internal power supply

for the digital part of the device. If the supply has
temporarily been lower than the specified lower limit, the
Power-onreset bit POR (see Section 10.4.1), will be set to
logic 1. Bit CLRPOR (see Section 10.3.2) resets the
Power-on reset flip-flop to LOW. If this is detected, an
initialization of the TDA9870A has to be carried out to
ensure reliable operation.

. Test functions are for manufacturing tests only

SSD1

6.1.4 FM AND AM DEMODULATION
An FM or AM input signal is fed via a band-limiting filter to

a demodulator that can be used for either FM or AM
demodulation. Apart from the standard (fixed)
de-emphasis characteristic, an adaptive de-emphasis is
availableforencodedsatelliteprograms.Astereodecoder
recovers the left and right signal channels from the
demodulated sound carriers. Both the European and
Korean stereo systems are supported.

1999 Dec 20 11

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

6.1.9 POWER-ON RESET
The reset is active LOW. In order to perform a reset at

power-up, a simple RC circuit may be used which consists
of the integrated passive pull-up resistor and an external
capacitor connected to ground. The pull-up resistor has a
nominal value of 50 kΩ, which can easily be measured
between pins CRESET and V

. Before the supply

DDD2

voltage has reached a certain minimum, the state of the
circuit is completely undefined, and it remains in this
undefined state unless a reset is applied.

The reset is guaranteed to be active when:

• The power supply is within the specified limits
(4.75 and 5.5 V)

• The crystal oscillator is functioning

• The voltage at pin CRESET is below 0.3V

V

= 5.0 V, typically below 1.8 V).

DDD

DDD

(1.5 V if

The required capacitor value depends on the gradient of
the rising power supply voltage. The time constant of the
RC circuit should be clearly larger than the rise time of the
power supply, to make sure that the reset condition is
always satisfied (see Fig.4), even considering the
tolerance spread. To avoid problems with a too slow
discharging of the capacitor at power-down, it may be
helpful to add a diode from pin CRESET to V

. It should

DDD

be noted that the internal ESD protection diode does not
help here as it only conducts at higher voltages. Under
difficult power supply conditions (e.g. very slow or
non-monotonic ramp-up), it is recommended to drive the
reset line from a microcontroller port or the like.

handbook, halfpage

5

voltage

(V)

1.5

V

> 4.75 V

DDD

V

CRESET

reset active
guaranteed

Fig.4 Reset at power-on.

MHB595

< 0.3V

DDD

t

1999 Dec 20 12

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1999 Dec 20 13

from ADC

2

S1

I

2

S2

I

2 2 2

LEVEL ADJUST

2

FILTER

2

2

DC

LEVEL ADJUST

LEVEL ADJUST

2

2

4

6

8

ndbook, full pagewidth

DIGITAL

CROSSBAR

SELECT

2

2

2

2

MATRIX

MATRIX

MATRIX

MATRIX

AUTOMATIC

VOLUME

LEVEL

VOLUME

SOFT-MUTE

BASS/TREBLE

BEEPER

LEVEL ADJUST AND MUTE

LEVEL ADJUST AND MUTE

BASS/TREBLE

BASS BOOST

SPATIAL
PSEUDO
VOLUME

CONTOUR

SOFT-MUTE

BEEPER

2

2

2

2

Main

Auxiliary

I

I

6.2 Digital signal processing

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

2

S1

2

S2

FM

2

DC

FILTER

2 4

ADAPTIVE

DE-EMPHASIS

FIXED

DE-EMPHASIS

LEVEL ADJUST

MATRIX

2

10

14

Fig.5 DSP data flow diagram.

MATRIX

DETECTION

MONITOR

SELECT

PEAK

LEVEL ADJUST

2

1

I

MHB112

DAC

2

C-bus

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

6.2.1 LEVEL SCALING
All input channels to the digital crossbar switch (except for

the loudspeaker feedback path) are equipped with a level
adjust facility to change the signal level in a range from
+15 to −15 dB (see Fig.5). It is recommended to scale all
input channels to be 15 dB below full-scale (−15 dB
full-scale) under nominal conditions.

6.2.2 FM (AM) PATH
A high-pass filter suppresses DC offsets from the

FM demodulator, due to carrier frequency offsets, and
supplies the monitor/peak function with DC values and an
unfiltered signal, e.g. for the purpose of carrier detection.

The de-emphasis function offers fixed settings for the
supported standards (50, 60 and 75 µs).

An adaptive de-emphasis is available for
Wegener-Panda 1 encoded programs.

A matrix performs the dematrixing of the A2 stereo, dual
and mono signals.

6.2.3 MONITOR
This function provides data words from a number of

locations of the signal processing paths to the I2C-bus
interface (2 data bytes). Signal sources include the
FM demodulator outputs, most inputs to the digital
crossbar switch and the outputs of the ADC. Source
selection and data read-out is performed via the I2C-bus.

Optionally, the peak value can be measured instead of
simply taking samples. The internally stored peak value is
reset to zero when the data is read via the I2C-bus.
The monitor function may be used, for example, for signal
level measurements or carrier detection.

6.2.4 LOUDSPEAKER (MAIN) CHANNEL

Volume is controlled individually for each channel ranging
from +24 to −83 dB with 1 dB resolution. There is also a
muteposition.Forthepurposeofasimplecontrolsoftware
in the microcontroller, the decimal number that is sent as
an I2C-bus data byte for volume control is identical to the
volume setting in dBs (e.g. the I2C-bus data byte +10 sets
the new volume value to +10 dB).

Balance can be realized by independent control of the left
and right channel volume settings.

Contour is adjustable between 0 and +18 dB with 1 dB
resolution. This function is linked to the volume setting by
means of microcontroller software.

Bass is adjustable between +15 and −12 dB with 1 dB
resolution and treble is adjustable between
+12 and −12 dB with 1 dB resolution.

For the purpose of a simple control software in the
microcontroller, the decimal number that is sent as an
I2C-bus data byte for contour, bass or treble is identical to
the new contour, bass or treble setting in dBs (e.g. the
I2C-bus data byte +8 sets the new value to +8 dB).

Extra bass boost is provided up to 20 dB with 2 dB
resolution. The implemented coefficient set serves merely
as an example on how to use this filter.

The beeper provides tones in a range from approximately
400 Hz to 30 kHz. The frequency can be selected via the
I2C-bus. The beeper output signal is added to the
loudspeaker and headphone channel signals. The beeper
volume is adjustable with respect to full-scale between
0 and −93 dB with 3 dB resolution. The beeper is not
effected by mute.

Soft mute provides a mute ability in addition to volume
control with a well defined time (32 ms) after which thesoft
mute is completed. A smooth fading is achieved by a
cosine masking.

The matrix provides the following functions: forced mono,
stereo, channel swap, channel 1, channel 2 and spatial
effects.

There are fixed coefficient sets for spatial settings of 30%,
40% and 52%.

The Automatic Volume Level (AVL) function provides a
constant output level of −23 dB full-scale for input levels
between 0 and −29 dB full-scale. There are some fixed
decay time constants to choose from, i.e. 2, 4 and 8 s.

Pseudostereoisbasedonaphaseshiftinonechannelvia
a second-order all-pass filter. There are fixed coefficient
sets to provide 90 degrees phase shift at frequencies of
150, 200 and 300 Hz.

1999 Dec 20 14

6.2.5 HEADPHONE (AUXILIARY) CHANNEL
The matrix provides the following functions: forced mono,

stereo, channel swap, channel 1 and channel 2
(or C and S in Dolby Surround Pro Logic mode).

Volume is controlled individually for each channel in a
range from +24 to −83 dB with 1 dB resolution. There is
also a mute position.

For the purpose of a simple control software in the
microcontroller, the decimal number that is sent as an
I2C-bus data byte for volume control is identical to the
volume setting in dB (e.g. the I2C-bus data byte +10 sets
the new volume value to +10 dB).

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Balance can be realized by independent control of the left
and right channel volume settings.

Bass is adjustable between +15 and −12 dB with 1 dB
resolution and treble is adjustable between
+12 and −12 dB with 1 dB resolution.

For the purpose of a simple control software in the
microcontroller, the decimal number that is sent as an
I2C-bus data byte for bass or treble is identical to the new
bass or treble setting in dB (e.g. the I2C-bus data byte +8
sets the new value to +8 dB).

The beeper provides tones in a range from approximately
400 Hz to 30 kHz. The frequency can be selected via the
I2C-bus. The beeper output signal is added to the
loudspeaker and headphone channel signals. The beeper
volume is adjustable with respect to full-scale between
0 and −93 dB with 3 dB resolution. The beeper is not
effected by mute.

Soft mute provides a mute ability in addition to volume
control with a well defined time (32 ms) after which thesoft
mute is completed. A smooth fading is achieved by a
cosine masking.

6.2.6 FEATURE INTERFACE
The feature interface comprises two I2S-bus input/output

ports and a system clock output. Each I2S-bus port is
equipped with level adjust facilities that can change the
signal level in a range from +15 to −15 dB with 1 dB
resolution. Outputs can be disabled to improve EMC
performance.

TheI2S-busoutputmatrixprovidesthefollowingfunctions:
forced mono, stereo, channel swap, channel 1 and
channel 2.

One example of how the feature interface can be used in
a TV set is to connect an external Dolby Surround Pro
Logic DSP, such as the SAA7710, to the I2S-bus ports.
Outputs must be enabled and a suitable master clock
signal for the DSP can be taken from pin SYSCLK.
A stereo signal from any source will be output on one of
the I2S-bus serial data outputs and the four processed
signal channels will be entered at both I2S-bus serial data
inputs. Left and right could then be output to the power
amplifiers via the Main channel, centre and surround via
the Auxiliary channel.

6.2.8 CHANNEL TO THE ANALOG CROSSBAR PATH
Level adjust with control positions 0, +3, +6 and +9 dB.

6.2.9 DIGITAL CROSSBAR SWITCH
Input channels to the crossbar switch are from the audio

ADC, I2S1, I2S2, FM path and from the loudspeaker
channel path after matrix and AVL (see Fig.6).

Outputchannelscomprise loudspeaker, headphone, I2S1,
I2S2 and the audio DACs for line output and SCART.

TheI2S1andI2S2outputsalsoprovidedigitaloutputsfrom
the loudspeaker and headphone channels, but without the
beeper signals.

6.2.10 SIGNAL GAIN
There are a number of functions that can provide signal

gain, e.g. volume, bass and treble control. Great care has
to be taken when using gain with large input signals in
order not to exceed the maximum possible signal swing,
which would cause severe signal distortion. The nominal
signal level of the various signal sources to the digital
crossbar switch should be 15 dB below digital full-scale
(−15 dB full-scale). This means that a volume setting of,
say, +15 dB would just produce a full-scale output signal
and not cause clipping, if the signal level is nominal.

Sending illegal data patterns via the I2C-bus will not cause
any changes of the current setting for the volume, bass,
treble, bass boost and level adjust functions.

6.2.11 EXPERT MODE
The TDA9870A provides a special expert mode that gives

directwriteaccesstotheinternalCoefficientRAM(CRAM)
of the DSP. It can be used to create user-defined
characteristics, such as a tone control with different corner
frequencies or special boost/cut characteristics to correct
the low-frequency loudspeaker and/or cabinet frequency
responsesby means of the bass boost filter. However, this
mode must be used with great care.

More information on the functions of this device, such as
the number of coefficients per function, their default
values, memory addresses etc., can be made available on
request.

6.2.7 CHANNEL FROM THE AUDIO ADC
The signal level at the output of the ADC can be adjusted

in a range from +15 to −15 dB with 1 dB resolution.
The audio ADC itself is scaled to a gain of −6 dB.

1999 Dec 20 15

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

6.2.12 DSP FUNCTIONS

Table 4 Overview of DSP functions

FUNCTION

Bass control for loudspeaker and
headphone output

Treble control for loudspeaker and
headphone output

Contour for loudspeaker output yes control range 0 to +18 dB

Bass boost for loudspeaker output yes control range 0 to +20 dB

Volume control for each separate
channel in loudspeaker and
headphone output

Soft mute for loudspeaker and
headphone output

Spatial effects yes anti-phase crosstalk positions 30, 40 and 52 %
Pseudo stereo yes 90 degrees phase shift at frequency 150, 200 and 300 Hz
Beeper additional to the signal in the

loudspeaker and headphone channel

Automatic Volume Level (AVL) yes step width quasi continuously

General no −3 dB lower corner frequency of DSP 10 Hz

Level adjust I

Level adjust I2S1 and I2S2 outputs yes control range −15 to +15 dB

Level adjust analog crossbar path no control positions 0, 3, 6 and 9 dB

2

S1 and I2S2 inputs yes control range −15 to +15 dB

EXPERT

MODE

yes control range −12 to +15 dB

resolution 1 dB
resolution at frequency 40 Hz

yes control range −12 to +12 dB

resolution 1 dB
resolution at frequency 14 kHz

resolution 1 dB
resolution at frequency 40 Hz

resolution 2 dB
resolution at frequency 20 Hz
corner frequency 350 Hz

no control range −83 to +24 dB

resolution 1 dB
mute position at step 10101100

no processing time 32 ms

yes beep frequencies see Section 10.3.38

control range 0 to −93 dB
resolution 3 dB
mute position at step 00100000

AVL output level for an input level
between 0 and −29 dB full-scale

attack time 10 ms
decay time constant 2, 4 and 8 s

−1 dB bandwidth of DSP 14.5 kHz

resolution 1 dB

resolution 1 dB
mute position at step 00010000

PARAMETER VALUE UNIT

−23 dB

1999 Dec 20 16

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

FUNCTION

EXPERT

MODE

PARAMETER VALUE UNIT

Level adjust audio ADC outputs yes control range +15 to −15 dB

resolution 1 dB

Level adjust FM path yes control range +15 to −15 dB

resolution 1 dB

6.3 Analog audio section

handbook, full pagewidth

SCART 1

SCART 2

external

mono

2

−3 dB

2

−3 dB

2

2

D

2

2

2

A

ANALOG

CROSSBAR

SWITCH

2

2

2

2

ANALOG

MATRIX

ANALOG

MATRIX

ANALOG

MATRIX

A

D

3 dB

2 2

0 dB

3 dB

2

0 dB

3 dB

2

0 dB

2

SCART 1

2

SCART 2

2

Line output

FM

2

I

S1

2

S2

I

2

S1

I

2

S2

I

2
2
2
2
2

DSP
AND

DIGITAL

CROSSBAR

SWITCH

2

D

A

2

D

A

2

Main

2

Auxiliary

MHB113

Fig.6 Block diagram for the audio section.

1999 Dec 20 17

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

6.3.1 ANALOG CROSSBAR SWITCH AND ANALOG MATRIX
There are a number of analog input and output ports with

the TDA9870A (see Figs 6 and 8). Analog source selector
switches are employed to provide the desired analog
signal routing capability. The analog signal routing is
performed by the analog crossbar switch section. A dual
audio ADC provides the connection to the DSP section
and a dual audio DAC provides the connection from the
DSP section to the analog crossbar switch. The digital
signal routing is performed by a digital crossbar switch.

The basic signal routing philosophy of the TDA9870A is
that each switch handles two signal channels at the same
time, e.g. left and right, language A and B, directly at the
source.

Each source selector switch is followed by an analog
matrix to perform further selection tasks, such as putting a
signal from one input channel, say language A, to both
output channels or for swapping left and right channels
(see Fig.7).

handbook, halfpage

left input

right input

ANALOG

MATRIX

left output
right output

MGK110

Fig.7 Analog matrix.

The analog matrix provides the functions given in Table 5.

6.3.2 SCART INPUTS
The SCART specification allows for a signal level of up to

2 V (RMS). Because of signal handling limitations, due to
the 5 V supply voltage of the TDA9870A, it is necessary to
have fixed 3 dB attenuators at the SCART inputs to obtain
a 2 V input. This results in a −3 dB SCART-to-SCART
copy gain. If 0 dB copy gain is preferred (with maximum

1.4 V input), there are 3 and 0 dB amplifiers at the outputs
of SCART 1 and SCART 2 and at the line output.

The input attenuator is realized by an external series
resistor in combination with the input impedance, both of
which form a voltage divider. With this voltage divider the
maximum SCART signal level of 2 V (RMS) is scaled
down to 1.4 V (RMS) at the input pin.

6.3.3 EXTERNAL AND MONO INPUTS
The3 dB input attenuators are not requiredfortheexternal

and mono inputs, because those signal levels are under
control of the TV designer. The maximum allowed input
level is 1.4 V (RMS). By adding external series resistors,
the external inputs can be used as an additional SCART
input.

6.3.4 SCART OUTPUTS
The SCART outputs employ amplifiers with two gain

settings. The gain can be set to 3 or 0 dB via the I2C-bus.
The 3 dB position is needed to compensate for the 3 dB
attenuation at the SCART inputs should
SCART-to-SCART copies with 0 dB gain be preferred
[under the condition of 1.4 V (RMS) maximum input level].
The 0 dB position is needed, for example, for an
external-to-SCART copy with 0 dB gain.

Table 5 Analog matrix functions

MATRIX OUTPUT

MODE

LEFT OUTPUT RIGHT OUTPUT

1 left input right input
2 right input left input
3 left input left input
4 right input right input

All switches and matrices are controlled via the I2C-bus.

1999 Dec 20 18

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

6.3.5 LINE OUTPUT
The line output can provide an unprocessed copy of the

audio signal in the loudspeaker channels. This can be
either an external signal that comes from the dual audio
ADC, or a signal from an internal digital audio source that
comes from the dual audio DAC. The line output employs
amplifiers with two gain settings. The 3 dB position is
needed to compensate for the attenuation at the SCART
inputs, while the 0 dB position is needed, for example, for
non-attenuated external or internal digital signals
(see Section 6.3.4).

6.3.6 LOUDSPEAKER (MAIN) AND HEADPHONE
(AUXILIARY) OUTPUTS

Signals from any audio source can be applied to the
loudspeakerandtotheheadphoneoutput channels via the
digital crossbar switch and the DSP.

6.3.7 DUAL AUDIO DAC

The TDA9870A contains three dual audio DACs, one for
theconnectionfromtheDSPtotheanalogcrossbarswitch
section and two for the loudspeaker and headphone
outputs. Each of the three dual low-noise high-dynamic
range DACs consists of two 15-bit DACs with current
outputs, followed by a buffer operational amplifier.
The audio DACs operate with four-fold oversampling and
noise shaping.

6.3.8 DUAL AUDIO ADC
There is one dual audio ADC in the TDA9870A for the

connection of the analog crossbar switch section to the
DSP. The dual audio ADC consists of two bitstream
3rd-order sigma-delta audio ADCs and a high-order
decimation filter.

6.3.9 STANDBY MODE
The standby mode, selected by setting bit STDBY to

logic 1 (see Section 10.3.2) disables most functions and
reduces power dissipation. The analog crossbar switch
and the SCART section remain operational and can be
controlled by the I2C-bus to support copying of analog
signals from SCART-to-SCART.

Unused internal registers may lose their information in the
standby mode. Therefore, the device needs to be
initialized on returning to the normal operating mode. This
can be accomplished in the same way as after a Power-on
reset.

6.3.10 SUPPLY GROUND
The different supply grounds VSSare internally connected

via the substrate. It is recommended to connect all ground
pins by a copper plane close to the pins.

1999 Dec 20 19

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1999 Dec 20 20

SCART 1

ndbook, full pagewidth

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

FM/AM

part

I2S1

2

I

S2

SCART 2

external

mono

FM/AM

DEMODULATOR

ADAPTIVE

DE-EMPHASIS

FIXED

DE-EMPHASIS

ADC

−6 dB

STEREO

DECODER

ADC

LEVEL

ADJUST

FM

LEVEL

ADJUST

I2S1
INPUT
LEVEL

ADJUST

I2S2
INPUT
LEVEL

ADJUST

DIGITAL
MATRIX

DIGITAL
MATRIX

DIGITAL
MATRIX

DIGITAL
MATRIX

DIGITAL
MATRIX

AUTOMATIC

VOLUME

LEVEL

I2S1

OUTPUT

LEVEL

ADJUST

I2S2

OUTPUT

LEVEL

ADJUST

DAC

GAIN

LOUDSPEAKER

PROCESSING

HEADPHONE
PROCESSING

DAC

CHANNEL

CHANNEL

DAC

DAC

ANALOG

MATRIX

ANALOG

MATRIX

ANALOG

MATRIX

Main

Auxiliary

2

I

S1

2

S2

I

BUFFER

0/+3 dB

BUFFER

0/+3 dB

BUFFER

0/+3 dB

Line

SCART 1

SCART 2

MHB114

Fig.8 Audio signal flow diagram.

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

7 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

∆V

DD

V

n

I

DDD,ISSD

I

lu(prot)

P

tot

T

stg

T

amb

V

es

Notes

1. Human body model: C = 100 pF; R = 1.5 kΩ.

2. Machine model: C = 200 pF; L = 0.75 µH; R = 0 Ω.

DC supply voltage −0.5 +6.0 V
voltage differences between two VDD pins − 550 mV
voltage on any other pin −0.5 VDD+ 0.5 V
DC current per digital supply pin −±180 mA
latch-up protection current 100 − mA
total power dissipation − 1.0 W
storage temperature −55 +125 °C
ambient temperature −20 +70 °C
electrostatic handling voltage note 1 −2000 +2000 V

note 2 −200 +200 V

8 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air

TDA9870A (SDIP64) 40 K/W
TDA9870AH (QFP64) 50 K/W

1999 Dec 20 21

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

9 CHARACTERISTICS

V
V
parameters in accordance with system A2; 1 kΩ measurement source resistance for AF inputs; with external
components of Fig.10; unless otherwise specified.

Supplies

V
V
I
V
V
I

V
V
V
I

V

V

V

V

Demodulator supply decoupling and references

V

V

I

Audio supply decoupling and references

V

V

Z
Z
V

Z
Z

= 300 mV; AGCOFF= 0; AGCSLOW = 0; AGCLEV = 0; level and gain settings in accordance with note 1;

SIF(p-p)

=5V; T

DD

=25°C; settings in accordance with B/G standard; FM deviation ±50 kHz; f

amb

= 1 kHz; FM sound

mod

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DDD1
SSD1

DDD1

DDD2
SSD2

DDD2

digital supply voltage 1 4.75 5.0 5.5 V
digital supply ground 1 note 2 − 0.0 − V
digital supply current 1 V

=5.0V 5368 83mA

DDD1

digital supply voltage 2 4.75 5.0 5.5 V
digital supply ground 2 note 2 − 0.0 − V
digital supply current 2 V

= 5.0 V; system clock

DDD2

0.1 0.4 2 mA

output disabled

SSD3
SSD4
DDA

DDA

digital supply ground 3 note 2 − 0.0 − V
digital supply ground 4 note 2 − 0.0 − V
analog supply voltage 4.75 5.0 5.5 V
analog supply current for

V

= 5.0 V; digital silence 44 56 68 mA

DDA

DACpart

SSA1

analog ground for analog

note 2 − 0.0 − V

front-end

SSA2

analog ground for audio ADC

note 2 − 0.0 − V

part

SSA3

analog ground for audio DAC

note 2 − 0.0 − V

part

SSA4

DEC1

analog ground for SCART − 0.0 − V

analog supply decoupling

3.0 3.3 3.6 V

voltage for demodulator part

ref1

analog reference voltage for

− 2 − V

demodulator part

ref1(sink)

DEC2

sink current at pin V

ref1

analog supply decoupling

− 200 −µA

3.0 3.3 3.6 V

voltage for audio ADC part

ref2

Vref2-VDEC2
Vref2-VSSA2
ref3

reference voltage ratio for
audio ADCs

impedance pins V
impedance pins V

ref2
ref2

to V
to V

reference voltage ratio for
audio DAC and operational

referenced to V
V

DEC2
SSA2

referenced to V
V

SSA2

SSA3

DEC2

DDA

and

and

− 50 − %

− 20 − kΩ

− 20 − kΩ

− 50 − %

amplifier

Vref3-VDDA
Vref3-VSSA3

impedance pins V
impedance pins V

ref3
ref3

to V
to V

DDA
SSA3

− 20 − kΩ

− 20 − kΩ

1999 Dec 20 22

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Power fail detector

V

th(pf)

Digital inputs and outputs

INPUTS

CMOS level input, pull-down (pins TEST1 and TEST2)

V

IL

V

IH

C

i

Z

i

CMOS level input, hysteresis, pull-up (pin CRESET)

V

IL

V

IH

V

hys

C

i

Z

i

INPUTS/OUTPUTS

power fail threshold voltage − 3.9 − V

LOW-level input voltage −− 0.3V
HIGH-level input voltage 0.7V

−−V

DDD

DDD

V

input capacitance −− 10 pF
input impedance − 50 − kΩ

LOW-level input voltage −− 0.3V
HIGH-level input voltage 0.7V

−−V

DDD

DDD

V

hysteresis voltage − 1.3 − V
input capacitance −− 10 pF
input impedance 30 50 − kΩ

I2C-bus level input with Schmitt trigger, open-drain output stage, 400 kHz I2C-bus operation (pins SCL and SDA)

V

IL

V

IH

V

hys

I

LI

C

i

V

OL

C

L

LOW-level input voltage −− 0.3V
HIGH-level input voltage 0.7V
hysteresis voltage − 0.05V

−−V

DDD

− V

DDD

DDD

V

input leakage current −− ±10 µA
input capacitance −− 10 pF
LOW-level output voltage −− 0.6 V
load capacitance −− 400 pF

TTL/CMOS level, 4 mA 3-state output stage, pull-up (pins ADDR1, ADDR2, P1, P2, SCK, WS, SDO1, SDO2, SDI1
and SDI2)

V

IL

V

IH

C

i

V

OL

V

OH

C

L

Z

i

LOW-level input voltage −− 0.8 V
HIGH-level input voltage 2.0 −−V
input capacitance −− 10 pF
LOW-level output voltage −− 0.4 V
HIGH-level output voltage 2.4 −−V
load capacitance −− 100 pF
input impedance − 50 − kΩ

OUTPUTS

CMOS level output, 4 mA 3-state output stage, slew rate controlled (pin SYSCLK)

V

OL

V

OH

C

L

I

LIZ

LOW-level output voltage −− 0.3V
HIGH-level output voltage 0.7V

−−V

DDD

DDD

V

load capacitance −− 100 pF
3-state leakage current Vi= 0 to V

DDD

−− ±10 µA

1999 Dec 20 23

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SIF1 and SIF2 analog inputs

V

SIF(max)(p-p)

maximum composite SIF input
voltage for clipping
(peak-to-peak value)

V

SIF(min)(p-p)

minimum composite SIF input
voltage for lower limit of AGC

(peak-to-peak value)
AGC AGC range − 24 − dB
f

i

R

i

C

i

∆f

FM

∆f

FM(FS)

C/N

FM

α

ct

input frequency 4 − 9.2 MHz

input resistance AGCLEV = 0 10 −−kΩ

input capacitance − 7.5 11 pF

FM deviation B/G standard; THD < 1% ±100 −−kHz

FM deviation full-scale level terrestrial FM; level adjust

FM carrier-to-noise ratio NFM bandwidth = 6 MHz;

crosstalk attenuation

SIF1 to SIF2

Demodulator performance

THD + N total harmonic distortion plus

noise

S/N signal-to-noise ratio SC1 from FM source to any

B

f

−3dB

res

−3 dB bandwidth from FM source to any

frequency response

20 Hz to 14 kHz

α

cs(dual)

α

cs(stereo)

α

AM

S/N

AM

dual signal channel separation note 4 65 70 − dB

stereo channel separation note 5 40 45 − dB

AM suppression for FM AM:1 kHz, 30% modulation;

AM demodulation SIF level 100 mV (RMS);

SIF input level adjust 0 dB − 941 − mV
SIF input level adjust −10 dB − 2976 − mV

SIF input level adjust 0 dB − 59 − mV
SIF input level adjust −10 dB − 188 − mV

±150 −−kHz

0dB

white noise for S/N = 40 dB;

“CCIR468”

; quasi peak

− 77 −

dB

------ ­Hz

fi= 4 to 9.2 MHz; note 3 50 −−dB

from FM source to any
output; V

= 1 V (RMS) with

o

− 0.3 0.5 %

low-pass filter

64 70 − dB

output; V

“CCIR468”

SC2 from FM source to any
output; V

“CCIR468”

= 1 V (RMS);

o

; quasi peak

= 1 V (RMS);

o

; quasi peak

60 66 − dB

14.5 15 − kHz

output
from FM to any output;

f

= 1 kHz; inclusive

ref

−±2−dB

pre-emphasis and
de-emphasis

50 −−dB
reference: 1 kHz, 50 kHz
deviation

36 45 − dB
54% AM; 1 kHz AF;

“CCIR468”

; quasi peak

1999 Dec 20 24

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

IDENTIFICATION FOR FM SYSTEMS
mod

p

C/N

p

f

ident

t

ident(on)

t

ident(off)

Analog audio inputs

pilot modulation for

25 50 75 %

identification
pilot sideband carrier-to-noise

ratio for identification start

− 27 −

dB

------ ­Hz

identification window B/G stereo

slow mode 116.85 − 118.12 Hz
medium mode 116.11 − 118.89 Hz
fast mode 114.65 − 120.46 Hz

B/G dual

slow mode 273.44 − 274.81 Hz
medium mode 272.07 − 276.20 Hz
fast mode 270.73 − 277.60 Hz

total identification time ON slow mode −− 2s

medium mode −− 1s
fast mode −− 0.5 s

total identification time OFF slow mode −− 2s

medium mode −− 1s
fast mode −− 0.5 s

MONO INPUT AND EXTERNAL INPUT
V

i(nom)(rms)

nominal level input voltage
(RMS value)

V

i(clip)(rms)

clipping level input voltage
(RMS value)

R

i

input resistance note 6 28 35 42 kΩ
SCART INPUTS
V

i(nom)(rms)

nominal level input voltage at

input pin (RMS value)
V

i(clip)(rms)

clipping level input voltage at

input pin (RMS value)

R

i

input resistance note 6 28 35 42 kΩ

− 500 − mV

THD < 3%; note 6 1250 1400 − mV

−3 dB divider with external

− 350 − mV

15 kΩ resistor; note 7

−3 dB divider with external

1250 1400 − mV
15 kΩ resistor; THD < 3%;
notes 6 and 7

1999 Dec 20 25

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog audio outputs

LOUDSPEAKER (MAIN) AND HEADPHONE (AUXILIARY) OUTPUTS
V

o(clip)(rms)

R

o

R

L(AC)

R

L(DC)

C

L

V

offset(DC)

α

mute

G

ro(main,aux)

PSRR

main,aux

SCART OUTPUTS AND LINE OUTPUT
V

o(nom)(rms)

V

o(clip)(rms)

R

o

R

L(AC)

R

L(DC)

C

L

V

offset(DC)

α

mute

B bandwidth from SCART, external and

PSRR power supply ripple rejection f

clipping level output voltage

THD < 3% 1250 1400 − mV

(RMS value)
output resistance 150 250 375 Ω
AC load resistance 10 −−kΩ
DC load resistance 10 −−kΩ
load capacitance − 10 12 nF
static DC offset voltage − 30 70 mV
mute suppression nominal input signal from

80 −−dB
any source; fi= 1 kHz

roll-off gain at 14.5 kHz for

from any source −3 −2 − dB

Main and Auxiliary channels
power supply ripple rejection

for Main and Auxiliary
channels

f

= 70 Hz;

ripple

V

= 100 mV (peak);

ripple

C

=47µF;

Vref

40 45 − dB

signal from I2S-bus

nominal level output voltage

3 dB amplification − 500 − mV

(RMS value)
clipping level output voltage

THD < 3% 1250 1400 − mV

(RMS value)
output resistance 150 250 375 Ω
AC load resistance 10 −−kΩ
DC load resistance 10 −−kΩ
load capacitance −− 2.5 nF
static DC offset voltage output amplifiers at 3 dB

− 30 50 mV

position

mute suppression nominal input signal from

80 −−dB
any source; fi= 1 kHz

20 −−kHz
mono sources;

−3 dB bandwidth
from DSP sources;

14.5 −−kHz

−3 dB bandwidth

= 70 Hz;

ripple

V

= 100 mV (peak);

ripple

C

=47µF;

Vref

40 45 − dB

signal from I2S-bus

1999 Dec 20 26

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Audio performance

THD + N total harmonic distortion plus

noise

V
fi= 1 kHz; bandwidth
20 Hz to 15 kHz; note 8

S/N signal-to-noise ratio reference voltage

V

“CCIR468”

note 8

α

ct

crosstalk attenuation between any analog input

pairs; fi= 1 kHz
between any analog output

pairs; f

α

cs

channel separation between left and right of any

input pair
between left and right of any

output pair

G

A

gain from SCART-to-SCART
with −3 dB input voltage
divider

output amplifier in 3 dB
position; R

output amplifier in 0 dB
position; R

Crystal specification (fundamental mode)

f

xtal

C

L

C

1

C

0

Φ

pull

crystal frequency − 24.576 − MHz
load capacitance − 20 − pF
series capacitance − 20 − fF
parallel capacitance −− 7pF
pulling sensitivity CLchanged from

18 to 16 pF

R

R

R

N

equivalent series resistance at nominal frequency −− 30 Ω
equivalentseries resistance of

unwanted mode

∆T temperature range −20 +25 +70 °C

= 1 V (RMS);

i=Vo

from any analog audio
input to I

fromI

2

S-bus

2

S-bustoanyanalog

− 0.1 0.3 %

− 0.1 0.3 %

audio output
SCART-to-SCART copy − 0.1 0.3 %
SCART-to-Main copy − 0.2 0.5 %

= 1.4 V (RMS);fi= 1 kHz;

o

; quasi peak;

from any analog audio
input to I

fromI

2

S-bus

2

S-bustoanyanalog

73 77 − dB

78 85 − dB

audio output
SCART-to-SCART copy 78 85 − dB
SCART-to-Main copy 73 77 − dB

70 −−dB

65 −−dB

=10kHz

i

65 −−dB

60 −−dB

−1.5 0 +1.1 dB

=15kΩ±10%

ext

−4.5 −3.0 −1.9 dB

=15kΩ±10%

ext

− 25 −

2R

−−Ω

R

10

----------­pF

6–

1999 Dec 20 27

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

X

J

X

D

X

A

adjustment tolerance −− ±30 10
drift across temperature range −− ±30 10
ageing −− ±5

Notes

1. Definitions of levels and level setting:
a) The full-scale level for analog audio signals is 1.4 V (RMS).
b) The nominal level at the digital crossbar switch is defined at −15 dB (full-scale).
c) Nominal audio input levels for external and mono: 500 mV (RMS) at −9 dB (full-scale).
d) See also Tables 6 and 7.

2. All analog and digital supply ground pins are connected internally.

3. Set demodulator to AM mode. Apply an AM carrier (with 1 kHz and 100%) to one channel. Check AGC step. Switch
AGCoffandset AGC to the gain step found. Measure the 1 kHz signal level of this channel and take it as a reference.
Switch to the other SIF input to which no signal is connected and which is terminated with 50 Ω. Now measure the
1 kHz crosstalk signal level. The SIF source resistance should be low (50 Ω).

4. FM source; in dual mode only A (respectively B) signal modulated; measured at B (respectively A) channel output;
Vo= 1 V (RMS) of modulated channel.

5. FM source; in stereo mode only L (respectively R) signal modulated; measured at R (respectively L) channel output;
Vo= 1 V (RMS) of modulated channel. The stereo channel separation may be limited by adjustment tolerances of
the transmitter.

6. If the supply voltage for the TDA9870A is switched off, because of the ESD protection circuitry, all audio input pins
are short-circuited. To avoid a short-circuit at the SCART inputs a 15 kΩ resistor (−3 dB divider) has to be used.

7. The SCART specification allows a signal level of up to 2 V (RMS). Because of signal handling limitations due to the
5 V supply voltage for the TDA9870A, there is a need for fixed 3 dB attenuators at the SCART inputs. To achieve
SCART-to-SCART copies with 0 dB gain, there are 3 and 0 dB amplifiers at the outputs of SCART 1 and SCART 2
and at the line output. The attenuator is realized by an internal resistor that works together with an external series
resistor as a voltage divider. With this voltage divider the maximum SCART input signal level of 2 V (RMS) is scaled
down to 1.4 V (RMS) at the input pin. To avoid clipping, the 3 dB gain must not be used if the SCART input signal is
larger than 1.4 V (RMS).

8. ADC level adjust is 6 dB, all other level adjusts are 0 dB. If an external −3 dB divider is used set output buffer gain
to 3 dB, tone control to 0 dB, AVL off and volume control to 0 dB.

−6

−6

10

----------­year

6–

1999 Dec 20 28

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1999 Dec 20 29

Table 6 Level setting FM at 0 dB (full-scale) = 1.4 V (RMS); note 1

2 CHANNEL

FM

STANDARD

M 15 kHz deviation −24 dB (full-scale);

B/G 27 kHz deviation −19 dB (full-scale) 5.5 MHz 5.742 MHz on 50 µs+4dB
D/K 27 kHz deviation −19 dB (full-scale) 6.5 MHz 6.742 MHz on 50 µs+4dB

Notes

1. Nominal level at digital crossbar is defined at −15 dB (full-scale). DAC gain setting 6 dB. Output buffer setting 0 dB. Nominal SCART output level
500 mV (RMS).

2. For stereo signals the output level is 6 dB lower. The level adjust has to be increased by 6 dB.

Table 7 Level setting SAT FM at 0 dB (full-scale) = 1.4 V (RMS)

TRANSMITTER

NOMINAL

MODULATION

DEPTH

27 kHz deviation −19 dB (full-scale) 6.5 MHz 6.25 MHz on 50 µs+4dB
27 kHz deviation −19 dB (full-scale) 6.5 MHz 5.742 MHz on 50 µs+4dB

NOMINAL LEVEL AT

DEMODULATOR

OUTPUT

note 2

CARRIER 1

FREQUENCY

4.5 MHz 4.724 MHz on 75 µs+9dB

FREQUENCY IDENT

CARRIER 2

DE-EMPHASISOF

CARRIER 1 AND

CARRIER 2

FM LEVEL

ADJUSTSETTING

OF CARRIER 1

AND CARRIER 2

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

TRANSMITTER

SOURCE

SAT FM, stereo 50 kHz deviation −13 dB (full-scale) +4 dB −9 dB (full-scale) +6 dB 0 dB 1 V (RMS)
SAT FM, mono 85 kHz deviation −9 dB (full-scale) 0 dB

MAXIMUM

MODULATION

DEPTH

NOMINAL LEVEL AT

DEMODULATOR

OUTPUT

FM LEVEL

ADJUST

SETTING

MAXIMUM

LEVEL AT

CROSSBAR

DACGAIN

SETTING

OUTPUT
BUFFER

NOMINAL SCART

OUTPUT VOLTAGE

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10 I2C-BUS CONTROL

10.1 Introduction

The TDA9870A is fully controlled via the I2C-bus. Control
is exercised by writing data to one or more internal
registers. Status information can be read from an array of
registers to enable the controlling microcontroller to
determine whether any action is required.

The device has an I2C-bus slave transceiver, in
accordance with the fast-mode specification, with a
maximumspeedof400 kbits/s. Information concerningthe
I2C-bus can be found in brochure

it”

(order number 9398 393 40011). To avoid conflicts in a
real application with other ICs providing similar or
complementary functions, there are four possible slave
addresses available which can be selected by
pins ADDR1 and ADDR2 (see Table 8).

Table 8 Possible slave addresses

ADDR2 ADDR1

LOW LOW 1011000

LOW HIGH 1011001
HIGH LOW 1011010
HIGH HIGH 1011011

The I2C-bus interface remains operational in the standby
mode of the TDA9870A to allow control of the analog
source selectors with regard to SCART-to-SCART
copying.

The device will not respond to a ‘general call’ on the
I2C-bus, i.e. when a slave address of 0000000 is sent by a
master.

The data transmission between the microcontroller and
the other I2C-bus controlled ICs is not disturbed when the
supply voltage of the TDA9870A is not connected.

A6 A5 A4 A3 A2 A1 A0

“I2C-bus and how to use

SLAVE ADDRESS

10.2 Power-up state

At power-up the device is in the following state:

• All outputs muted

• No sound carrier frequency loaded

• General purpose I/O pins ready for input (HIGH)

• Input SIF1 selected with:

– AGC on
– Small hysteresis
– SIF input level shift 0 dB.

• Demodulators for both sound carriers set to FM with:
– Identification for B/G, D/K, response time 1 s
– Level adjust set to 0 dB
– De-emphasis 50 µs
– Matrix set to mono.

• Main channel set to FM input with:
– Spatial off
– Pseudo off
– AVL off
– Volume mute
– Bass flat
– Treble flat
– Contour off
– Bass boost flat.

• Auxiliary channel set to FM input with:
– Volume mute
– Bass flat
– Treble flat.

• Feature interface all outputs off

• Beeper off

• Monitoring of carrier 1 FM demodulator DC output.

After power-up a device initialization has to be performed
via the I
of operation, in accordance with the desired TV standard,
audio control settings, etc.

2

C-bus to put the TDA9870A into the proper mode

1999 Dec 20 30

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3 Slave receiver mode

As a slave receiver, the TDA9870A provides 46 registers for storing commands and data. These registers are accessed
via so-called subaddresses. A subaddress can be thought of as a pointer to an internal memory location.

2

Table 9 I

S SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA ACK P

Table 10 Explanation of Table 9

S START condition
SLAVE ADDRESS 7-bit device address
0 data direction bit (write to device)
ACK acknowledge by slave
SUBADDRESS address of register to write to
DATA data byte to be written into register
P STOP condition

C-bus; slave address, subaddress and data format

BIT FUNCTION

It is allowed to send more than one data byte per transmission to the TDA9870A. In this event, the subaddress is
automatically incremented after each data byte, resulting in storing the sequence of data bytes at successive register
locations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged with
ACK (acknowledge).

There is no ‘wrap-around’ of subaddresses.
Commands and data are processed as soon as they have been completely received. Functions requiring more than one

byte will, thus, be executed only after all bytes for that function have been received. If the transmission is terminated
(STOP condition) before all bytes have been received, the incomplete data for that function are ignored.

Table 11 Format for a transmission employing auto-increment of subaddresses

S SLAVE ADDRESS 0 ACK SUBADDRESS ACK DATA

BYTE A

Note

1. n data bytes with auto-increment of subaddresses.

Data patterns sent to the various subaddresses are not checked for being illegal or not at that address, except for the
functions of volume, bass and treble control, bass boost and level adjust.

Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation will
then not be executed.

DATA ACK P

(1)

1999 Dec 20 31

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 12 Overview of the slave receiver registers

SUBADDRESS

(DECIMAL)

0 00sgggggAGC level shift, AGC gain selection
1 ccccccccgeneral configuration
2 p 0 0 m m s s s monitor select, peak detector on/off
3 ffffffffcarrier 1 frequency; most significant part
4 ffffffffcarrier 1 frequency
5 ffffffffcarrier 1 frequency; least significant part
6 ffffffffcarrier 2 frequency; most significant part
7 ffffffffcarrier 2 frequency
8 ffffffffcarrier 2 frequency; least significant part

9 ccccccccdemodulator configuration
10 ddddddddFMde-emphasis
11 00000mmmFMmatrix
12 000lllllchannel 1 output level adjust
13 000lllllchannel 2 output level adjust
14 00000000set to logic 0; note 1
15 00000000set to logic 0; note 1
16 00000000set to logic 0; note 1
17 00000000set to logic 0; note 1
18 mmmmmmmmaudio mute control
19 g m m m g s s s DAC output select
20 0 g m m 0 s s s SCART 1 output select
21 0 g m m 0 s s s SCART 2 output select
22 0 g m m 0 0 0 s line output select
23 ssslllllADC output select
24 0 m m m 0 s s s Main channel select
25 00ssppaaaudio effects (AVL, pseudo and spatial)
26 vvvvvvvvvolume control, Main left
27 vvvvvvvvvolume control, Main right
28 000ccccccontour control, Main
29 000bbbbbbass control, Main
30 000ttttttreble control, Main
31 0 m m m 0 s s s Auxiliary channel select
32 vvvvvvvvvolume control, Auxiliary left
33 vvvvvvvvvolume control, Auxiliary right
34 000bbbbbbass control, Auxiliary
35 000ttttttreble control, Auxiliary
36 000cccccfeature interface configuration
37 0mmm0 s s sI

MSB LSB

DATA

2

S1 output select

FUNCTION

1999 Dec 20 32

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

SUBADDRESS

(DECIMAL)

MSB LSB

38 000iiiiiI
39 000oooooI
40 0mmm0 s s sI
41 000iiiiiI
42 000oooooI

DATA

FUNCTION

2

S1 input level adjust

2

S1 output level adjust

2

S2 output select

2

S2 input level adjust

2

S2 output level adjust
43 00000f f fbeeper frequency
44 00vvvvvvbeeper volume, Main and Auxiliary
45 bbbbbbbbbass boost, Main left and right

Note

1. These bits have not been assigned to a function.

The following sub-sections provide a detailed description of the slave receiver registers.

10.3.1 AGC GAIN REGISTER
If the automatic gain control function is switched off in the general configuration register, the contents of this register will

define a fixed gain of the AGC stage. The input voltages given are meant to generate a full-scale output from the SIF
ADC. If automatic gain control is on, the AGCGAIN setting is ignored. After switching off the automatic gain control
function, the latest gain control setting is copied to the AGC gain register.

If the AGC input level shift bit AGCLEV is set to logic 1 the input signal is scaled with −10 dB. The AGCLEV bit is also
active if the automatic gain function is enabled.

It should be noted that the input voltages should be considered as approximate target values.

Table 13 Subaddress 0 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 set to logic 0

6 B6 0 set to logic 0
5 AGCLEV 1 input signal scaled with −10 dB

0 input signal not scaled
4 AGCGAIN − gain control bits (see Table 14).
3
2
1

0 (LSB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 33

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 14 Gain control bits

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

000/111111 0.0 941/2976
000/111110 0.8 861/2723
000/111101 1.5 788/2490
000/111100 2.3 720/2278
000/111011 3.1 659/2084
000/111010 3.9 603/1906
000/111001 4.6 551/1744
000/111000 5.4 504/1595
000/110111 6.2 461/1459
000/110110 7.0 422/1334
000/110101 7.7 386/1221
000/110100 8.5 353/1117
000/110011 9.3 323/1021
000/110010 10.1 295/934
000/110001 10.8 270/855
000/110000 11.6 247/782
000/101111 12.4 226/715
000/101110 13.2 207/654
000/101101 13.9 189/598
000/101100 14.7 173/547
000/101011 15.5 158/501
000/101010 16.3 145/458
000/101001 17.0 132/419
000/101000 17.8 121/383
000/100111 18.6 111/350
000/100110 19.4 101/321
000/100101 20.1 93/293
000/100100 20.9 85/268
000/100011 21.7 78/245
000/100010 22.5 71/224
000/100001 23.2 65/205
000/100000 24.0 59/188 (note 1)

AGC GAIN

(dB)

SIF INPUT VOLTAGE

[mV (p-p)]

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 34

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.2 GENERAL CONFIGURATION REGISTER

Table 15 Subaddress 1 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) P2OUT − This bit controls the general purpose input/output pin P2. The contents of this bit

is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1, subaddress 0).

6 P1OUT − This bit controls the general purpose input/output pin P1. The contents of this bit

is written directly to the corresponding pin. If input is desired, the bit must be set to
logic 1 to allow the pin to be pulled LOW externally. Input from the pin is reflected
in the device status register (see Section 10.4.1, subaddress 0). P1OUT is
recommended to be used for switching an SIF trap for the adjacent picture carrier
in designs that employ such a trap.

5 STDBY 1 The TDA9870A is in the standby mode. Most functions are disabled and power

dissipation is somewhat reduced, but the analog selectors/matrices remain
operational to support analog copying from SCART-to-SCART.

0 The TDA9870A is in normal operating mode. On return from standby mode, the

device is in its Power-on reset mode and needs to be re-initialized.

4 INIT 1 Causes initialization of the TDA9870A to its default settings. This has the same

effect as a Power-on reset. If there is a conflict between the default settings and
any bit set to logic 1 in this register, the bits of this register have priority over the
corresponding default setting.

0 Automatically reset to logic 0 after initialization. When set to logic 0, the

TDA9870A is in normal operating mode.

3 CLRPOR 1 Resets the power fail detector to LOW.

0 This bit is automatically reset to logic 0 after bit POR in the device status register

has been reset.

2 AGCSLOW 1 A longer decay time is selected for input signals with strong video modulation

(intercarrier). This bit only has an effect when bit AGCOFF = 0.

0 Selects normal attack and decay times for the AGC.

1 AGCOFF 1 Forces the AGC block to a fixed gain as defined in the AGC gain register.

0 The automatic gain control function is enabled and the contents of the AGC gain

register is ignored.

0 (LSB) SIFSEL 1 Selects pin SIF2 for input (recommended for satellite tuner).

0 Selects pin SIF1 for input (terrestrial TV).

Note

1. The default setting at power-up is 11000000.

1999 Dec 20 35

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.3 MONITOR SELECT REGISTER
This register is used to define the signal source, the level of which is to be monitored, and if the peak level is to be

monitored. Peak level refers to the magnitude of the maximum excursion of a signal.
Audio magnitude/phase is related to the FM demodulator output. Phase information is provided, when it operates in

FM mode, while magnitude is supplied in AM mode.
Data can be read-out in the I2C-bus slave transmitter mode. By reading out level read-out registers

(subaddresses 5 and 6, see Section 10.4), the current peak level will be reset.

Table 16 Subaddress 2 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) PEAKMON 1 selects the peak level of a source to be monitored

0 the last sample will be supplied
6 B6 0 default value
5 B5 0 default value
4B4−monitor output (see Table 17)
3B3
2B2−signal source (see Table 18)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 17 Monitor output

B4 B3 MONITOR OUTPUT

00

0 1 L input (channel 1, respectively)
1 0 R input (channel 2, respectively)

Table 18 Signal source (note 1)

B2 B1 B0 SIGNAL SOURCE

0 0 0 DC output of FM demodulator
0 0 1 audio magnitude/phase, FM demodulator output
0 1 0 crossbar input from FM/AM channel
0 1 1 don’t care
1 0 0 crossbar input from I
1 0 1 crossbar input from I
1 1 0 crossbar input from audio ADC channel
1 1 1 input to Main channel DAC (without beeper)

L input R input+

------------------------------------------­2

2

S1 channel

2

S2 channel

Note

1. The term ‘crossbar’ refers to the digital selector, where level-adjusted signals from various sources are available.

1999 Dec 20 36

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.4 CARRIER 1 FREQUENCY REGISTER
The three bytes together constitute a 24-bit frequency

control word to represent the sound carrier (i.e. mixer)
frequency in accordance with the following formula:

f

data

mix

--------­f

clk

224×=

Where:

data = 24-bit frequency control word
f

= desired sound carrier frequency

mix

f

= 12.288 MHz (clock frequency of mixer)

clk

224= 16777216 (number of steps in a 24-bit word size).

Example: A 5.5 MHz sound carrier frequency will be
generated by sending the following sequence of data
bytes to the TDA9870A (data = 7509333 in decimal
notation or 729555 in hexadecimal):
01110010 10010101 01010101.

As three bytes are required to define a carrier frequency,
execution of this command starts only after all bytes have
been received. If an error occurs, e.g. a premature STOP
condition, partial data for this function is ignored.

The default setting at power-up is 00000000 for all three
bytes.

Most significant part at subaddress 3 and least significant
part at subaddress 5 (see Table 19).

Table 19 Subaddresses 3 to 5

SUB-

ADDRESS

BIT DESCRIPTION

3 7 (MSB) carrier 1 frequency;

6

most significant part

5
4
3
2
1
0

4 7 carrier 1 frequency

6
5
4
3
2
1
0

5 7 carrier 1 frequency;

6

least significant part

5
4
3
2
1

0 (LSB)

1999 Dec 20 37

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.5 CARRIER 2 FREQUENCY REGISTER
Same as for sound carrier 1, except for subaddresses (subaddresses 6 to 8). If the carrier 2 frequency register is used,

it will be for the second FM sound carrier of a terrestrial or satellite FM program.

10.3.6 DEMODULATOR CONFIGURATION REGISTER
It is recommended to switch the FM sound mode identification off whenever the received program is not a terrestrial

2-carrier sound. Switching the identification off will reset the associated hardware to a defined state.

Table 20 Subaddress 9 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) IDMOD1 − these bits define the response time after which a FM sound mode identification

6 IDMOD0

5 IDAREA 1 selects FM identification frequencies in accordance with the specification for

4 FILTBW1 − selects filter bandwidth (see Table 22)
3 CH2MOD1 − channel 2 receive mode: these bits control the hardware for the second sound
2 CH2MOD0
1 FILTBW0 − selects filter bandwidth (see Table 22)

0 (LSB) CH1MODE 1 selects the hardware for the first sound carrier to operate in AM mode

result may be expected; the longer the time, the more reliable the identification
(see Table 21)

Korea

0 selects frequencies for Europe (B/G and D/K standard)

carrier (see Table 23)

0 FM mode is assumed; this applies to both terrestrial and satellite FM reception

Note

1. The default setting at power-up is 00000000.

Table 21 Identification mode

B7 B6 IDENT MODE

0 0 slow
0 1 medium
1 0 fast
1 1 off/reset

Table 22 Filter bandwidth channel 1 and channel 2

FILTER

B4 B1

0 0 narrow narrow recommended for nominal terrestrial broadcast conditions and

0 1 extrawide narrow recommended only for high-deviation SAT mono carriers

1 0 medium medium recommended for moderately overmodulated broadcast conditions
1 1 wide wide recommended for strongly overmodulated broadcast conditions

BANDWIDTH

CH1 CH2

FILTER MODES

SAT with 2 carriers

(e.g. obsolete Main channel on Astra)

1999 Dec 20 38

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 23 Channel 2 receive mode

B3 B2 CHANNEL 2

00 FM
01 AM
1 0 don’t care

10.3.7 FM
This register is used to select the proper de-emphasis characteristics as appropriate for the standard of the received

carrier. Bits B3 to B0 apply to sound carrier 1, bits B7 to B4 apply to sound carrier 2.
In the event of A2 reception, both groups must be set to the same characteristics.

Table 24 Subaddress 10 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) ADEEM2 1 Activates the adaptive de-emphasis function, which is required for certain satellite

6B6−Time constant selection for FM de-emphasis (see Table 25).
5B5
4B4
3 ADEEM1 1 Activates the adaptive de-emphasis function, which is required for certain satellite

2B2−Time constant selection for FM de-emphasis (see Table 26).
1B1

0 (LSB) B0

Notes

1. The default setting at power-up is 00000000.

2. The FM de-emphasis gain is 0 dB at 40 Hz.

DE-EMPHASIS REGISTER

FM channels. The standard FM de-emphasis must then be set to 75 µs (note 2).

0 The adaptive de-emphasis is off.

FM channels. The standard FM de-emphasis must then be set to 75 µs (note 2).

0 The adaptive de-emphasis is off.

Table 25 De-emphasis sound carrier 2

B6 B5 B4 DE-EMPHASIS

000 50µs (Europe)
001 60µs
010 75µs (M standard)
011 J17
100 off

1999 Dec 20 39

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 26 De-emphasis sound carrier 1

B2 B1 B0 DE-EMPHASIS

000 50µs (Europe)
001 60µs
010 75µs (M standard)
011 J17
100 off

10.3.8 FM
This register is used to select the proper dematrixing characteristics as appropriate for the standard of the received

carrier and the related sound mode identification.

Table 27 Subaddress 11 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 28 Dematrixing characteristics

B2 B1 B0 L OUTPUT ROUTPUT MODE

0 0 0 CH1 input; note 1 CH1 input; note 1 mono 1
0 0 1 CH2 input; note 2 CH2 input; note 2 mono 2
0 1 0 CH1 input; note 1 CH2 input; note 2 dual
0 1 1 CH2 input; note 2 CH1 input; note 1 dual swapped
1 0 0 2CH1 input − CH2 input CH2 input; note 2 stereo Europe
1 0 1 stereo Korea; note 3

MATRIX REGISTER

6 B6 0 default value
5 B5 0 default value
4 B4 0 default value
3 B3 0 default value
2B2−dematrixing characteristics (see Table 28)
1B1

CH1 input CH2 input+

----------------------------------------------------------­2

CH1 input CH2 input–

----------------------------------------------------------­2

Notes

1. CH1 input: audio signal from FM channel 1.

2. CH2 input: audio signal from FM channel 2.

3. For stereo Korea the dematrix applies 6 dB attenuation (see Table 6).

1999 Dec 20 40

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.9 FM CHANNEL 1 LEVEL ADJUST REGISTER
This register is used to correct for standard and station-dependent differences of signal levels.
Table 29 applies to sound carrier 1.

Table 29 Subaddress 12

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10
00010101 −11
00010100 −12
00010011 −13
00010010 −14
00010001 −15
00010000 mute

GAIN SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 41

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.10 FM CHANNEL 2 LEVEL ADJUST REGISTER
This register is used to correct for standard and station-dependent differences of signal levels. Table 30 applies to sound

carrier 2 in its FM and AM modes. In the event of A2, channels 1 and 2 should be adjusted to the same level.

Table 30 Subaddress 13

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10
00010101 −11
00010100 −12
00010011 −13
00010010 −14
00010001 −15
00010000 mute

GAIN SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 42

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.11 REGISTER 14
Set to logic 0. These bits have not been assigned to a function.

10.3.12 REGISTER 15
Set to logic 0. These bits have not been assigned to a function.

10.3.13 REGISTER 16
Set to logic 0. These bits have not been assigned to a function.

10.3.14 REGISTER 17
Set to logic 0. These bits have not been assigned to a function.

10.3.15 AUDIO MUTE CONTROL REGISTER
When any of these bits are set to logic 1, the corresponding pair of output channels will be muted. A bit set to logic 0

allows normal signal output.
There is a soft-mute facility for the Main and Auxiliary output channels to provide click-free muting independent of the

volume control. This is switched on/off by bits MUTMAIN and MUTAUX.

Table 31 Subaddress 18 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) MUTI

6 MUTI

2

S2 1 mute I2S2 outputs

0 normal I

2

S1 1 mute I2S1 outputs

0 normal I

2

S2 outputs

2

S1 outputs

5 MUTDAC 1 mute internal DAC

0 normal internal DAC

4 MUTLINE 1 mute line outputs

0 normal line outputs

3 MUTSC2 1 mute SCART 2 outputs

0 normal SCART 2 outputs

2 MUTSC1 1 mute SCART 1 outputs

0 normal SCART 1 outputs

1 MUTAUX 1 mute Auxiliary outputs

0 normal Auxiliary outputs

0 (LSB) MUTMAIN 1 mute Main outputs

0 normal Main outputs

Note

1. The default setting at power-up is 11111111.

1999 Dec 20 43

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.16 DAC OUTPUT SELECT REGISTER
This register is used to define both the signal source to be entered into the DAC and the mode of the digital matrix for

signal selection. The DAC is used for signal output from digital sources at analog outputs.
The bits DACGAIN1 and DACGAIN2 can introduce some extra gain at the input to the DAC. DACGAIN1 adds 3 dB and

DACGAIN2 adds 6 dB of gain, respectively.

Table 32 Subaddress 19 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) DACGAIN2 − extra gain setting (see Table 33)

6B6−DAC output selection (see Table 34)
5B5
4B4
3 DACGAIN1 − extra gain setting (see Table 33)
2B2−signal source selection (see Table 35)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 33 Extra gain setting

B7 B3 GAIN (dB)

00 0
01 3
10 6
11 9

1999 Dec 20 44

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 34 DAC output selection

B6 B5 B4 L OUTPUT R OUTPUT

0 0 0 L input R input
0 0 1 L input L input
0 1 0 R input R input
0 1 1 R input L input
100

Table 35 Signal source selection

LR+

------------- ­2

LR+

------------- ­2

B2 B1 B0

0 0 0 FM left FM right
0 0 1 don’t care
010 I
011 I
1 0 0 ADC left ADC right
1 0 1 AVL left AVL right
1 1 0 don’t care
1 1 1 don’t care

LEFT RIGHT

2

S1 left I2S1 right

2

S2 left I2S2 right

SIGNAL SOURCE

1999 Dec 20 45

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.17 SCART 1 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at SCART 1 and the output channel selector mode.

Table 36 Subaddress 20 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

6 SC1GAIN 1 Activatesthe 3 dB gain stage at the SCART 1 output buffers.As any SCART input

passes a 3 dB attenuator, this gain stage can be used to compensate that
attenuation, resulting in a 0 dB insertion loss when copying from SCART 2 input to
SCART 1 output. However,that gain must be used with great care, as it will cause
signal clipping at high input levels.

0 the audio signal output will be unchanged (0 dB gain)
5B5−output channel selection (see Table 37)
4B4
3 B3 0 default value
2B2−signal source selection (see Table 38)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000001.

Table 37 Output channel selection

B5 B4 L OUTPUT R OUTPUT

0 0 L input R input
0 1 L input L input
1 0 R input R input
1 1 R input L input

Table 38 Signal source selection

B2 B1 B0 SIGNAL SOURCE

0 0 0 SCART 1 input
0 0 1 SCART 2 input
0 1 0 external input
0 1 1 mono input
1 0 0 DAC input

1999 Dec 20 46

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.18 SCART 2 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at SCART 2 and the output channel selector mode.

Table 39 Subaddress 21 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

6 SC2GAIN 1 Activatesthe 3 dB gain stage at the SCART 2 output buffers.As any SCART input

passes a 3 dB attenuator, this gain stage can be used to compensate that
attenuation, resulting in a 0 dB insertion loss when copying from SCART 1 input to
SCART 2 output. However,that gain must be used with great care, as it will cause
signal clipping at high input levels.

0 the audio signal output will be unchanged (0 dB gain)
5B5−output channel selection (see Table 40)
4B4
3 B3 0 default value
2B2−signal source selection (see Table 41)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 40 Output channel selection

B5 B4 L OUTPUT R OUTPUT

0 0 L input R input
0 1 L input L input
1 0 R input R input
1 1 R input L input

Table 41 Signal source selection

B2 B1 B0 SIGNAL SOURCE

0 0 0 SCART 1 input
0 0 1 SCART 2 input
0 1 0 external input
0 1 1 mono input
1 0 0 DAC input

1999 Dec 20 47

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.19 LINE OUTPUT SELECT REGISTER
By definition, the line output conveys the same signal as the Main (loudspeaker) channel, but in a non-processed form.

This register is used to characterize the signal to be output at the line output and define the output channel selector mode.

Table 42 Subaddress 22 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 set to logic 0

6 LINGAIN 1 activates the 3 dB gain stage at the line output buffers

0 the audio signal output will be unchanged (0 dB gain)
5B5−output channel selection (see Table43)
4B4
3 B3 0 set to logic 0
2 B2 0 set to logic 0
1 B1 0 set to logic 0

0 (LSB) LINSEL 1 A signal from an analog source is being processed in the Main channel for line

output. Analog signal sources comprise SCART 1 input, SCART 2 input,
external input and mono input, i.e. any input to the ADC.

0 A signal from a digital source is being processed in the Main channel for line

output. Digital signal sources comprise FM, I

2

S1 input and I2S2 input.

Note

1. The default setting at power-up is 00000000.

Table 43 Output channel selection

B5 B4 L OUTPUT R OUTPUT

0 0 L input R input
0 1 L input L input
1 0 R input R input
1 1 R input L input

1999 Dec 20 48

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.20 ADC OUTPUT SELECT REGISTER
This register is used to define the signal source for the ADC. There is no output channel selector, because all digital

signal sinks of the ADC have their own matrix. Instead, a level adjustment facility for the ADC output is provided.

Table 44 Subaddress 23 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 − signal source selection (see Table 45)

6B6
5B5
4B4−ADC level adjust (see Table 46)
3B3
2B2
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 45 Signal source selection

B7 B6 B5 SIGNAL SOURCE

0 0 0 SCART 1 input
0 0 1 SCART 2 input
0 1 0 external input
0 1 1 mono input

1999 Dec 20 49

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 46 ADC level adjust (note 1)

B4 B3 B2 B1 B0 GAIN SETTING (dB)

01111 +15
01110 +14
01101 +13
01100 +12
01011 +11
01010 +10
01001 +9
01000 +8
00111 +7
00110 +6
00101 +5
00100 +4
00011 +3
00010 +2
00001 +1
00000 0
11111 −1
11110 −2
11101 −3
11100 −4
11011 −5
11010 −6
11001 −7
11000 −8
10111 −9
10110 −10
10101 −11
10100 −12
10011 −13
10010 −14
10001 −15
10000 mute

Note

1. If the ADC level adjust is set to 0 dB a full-scale input signal to the ADC results into a level of −6 dB full-scale at the
digital crossbar.

1999 Dec 20 50

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.21 MAIN CHANNEL SELECT REGISTER

This register is used to define both the signal source to be processed in the Main (loudspeaker) channel and the mode
of the digital matrix for signal selection.

Table 47 Subaddress 24 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

6B6−output channel selection (see Table 48)
5B5
4B4
3 B3 0 default value
2B2−signal source selection (see Table 49)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 48 Output channel selection

B6 B5 B4 L OUTPUT R OUTPUT

0 0 0 L input R input
0 0 1 L input L input
0 1 0 R input R input
0 1 1 R input L input
100

Table 49 Signal source selection

B2 B1 B0 SIGNAL SOURCE

0 0 0 FM input
0 0 1 don’t care
010 I
011 I
1 0 0 ADC input

LR+

------------- ­2

2

S1 input

2

S2 input

LR+

------------- ­2

1999 Dec 20 51

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.22 AUDIO EFFECTS REGISTER
Switching the AVL off will reset the associated hardware to a defined state.
When the signal source for the Main channel is changed while the AVL is on, the AVL needs to be reset in order to avoid

excessive settling times. This can be achieved by switching the AVL off and on again.
The pseudo stereo function is based on an all-pass filter. A 90 degrees phase shift occurs at the frequencies stated in

Table 52. There is a gain of 3 dB in the left audio channel.

Table 50 Subaddress 25 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 Default value.

6 B6 0 Default value.
5 SPATIAL1 − These bits set the amount of the effect function (stereo base width expansion)
4 SPATIAL0

3 PSEUDO1 − These bits set the amount of the effect function (pseudo stereo) for mono
2 PSEUDO0

1 AVL1 − These bits set the mode of operation of the automatic volume level control

0 (LSB) AVL0

for stereo signals in the Main channel (see Table 51). This function should be
activated only in accordance with the result of the sound mode identification.

signals in the Main channel (see Table 52). This function should be activated
only in accordance with the result of the sound mode identification.

function at the entrance to the Main (loudspeaker) channel (see Table 53).

Note

1. The default setting at power-up is 00000000.

Table 51 Spatial control setting

B5 B4 SPATIAL SETTING (%)

0 0 off
01 30
10 40
11 52

Table 52 Pseudo control setting

B3 B2 PSEUDO SETTING (Hz)

0 0 off
0 1 300
1 0 200
1 1 150

Table 53 AVL control mode

B1 B0 AVL MODE

0 0 off/reset
0 1 short decay
1 0 medium decay
1 1 long decay

1999 Dec 20 52

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.23 VOLUME CONTROL REGISTERS (MAIN)
These two registers control the volume setting of the Main (loudspeaker) channel. The register at subaddress 26 applies

to the left channel signal, while the register at subaddress 27 applies to the right channel signal.
Balance control is exercised by offsetting the left and right channel volume settings.

Table 54 Subaddresses 26 and 27

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00011000 +24
00010111 +23
00010110 +22
00010101 +21
00010100 +20
00010011 +19
00010010 +18
00010001 +17
00010000 +16
00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0
11111111 −1
11111110 −2
11111101 −3
11111100 −4
11111011 −5
11111010 −6
11111001 −7
11111000 −8
11110111 −9

VOLUME SETTING (dB)

1999 Dec 20 53

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

11110110 −10
11110101 −11
11110100 −12
11110011 −13
11110010 −14
11110001 −15
11110000 −16
11101111 −17
11101110 −18
11101101 −19
11101100 −20
11101011 −21
11101010 −22
11101001 −23
11101000 −24
11100111 −25
11100110 −26
11100101 −27
11100100 −28
11100011 −29
11100010 −30
11100001 −31
11100000 −32
11011111 −33
11011110 −34
11011101 −35
11011100 −36
11011011 −37
11011010 −38
11011001 −39
11011000 −40
11010111 −41
11010110 −42
11010101 −43
11010100 −44
11010011 −45
11010010 −46
11010001 −47
11010000 −48

VOLUME SETTING (dB)

1999 Dec 20 54

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

11001111 −49
11001110 −50
11001101 −51
11001100 −52
11001011 −53
11001010 −54
11001001 −55
11001000 −56
11000111 −57
11000110 −58
11000101 −59
11000100 −60
11000011 −61
11000010 −62
11000001 −63
11000000 −64
10111111 −65
10111110 −66
10111101 −67
10111100 −68
10111011 −69
10111010 −70
10111001 −71
10111000 −72
10110111 −73
10110110 −74
10110101 −75
10110100 −76
10110011 −77
10110010 −78
10110001 −79
10110000 −80
10101111 −81
10101110 −82
10101101 −83
10101100 mute (note 1)

VOLUME SETTING (dB)

Note

1. The default setting at power-up is 10101100.

1999 Dec 20 55

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.24 CONTOUR CONTROL REGISTER
This register is used to apply the contour or loudness function (physiological volume control) to the left and right signal

channels of the Main channel by means of an extra bass boost. The gain setting must be chosen in accordance with the
volume control setting for the Main channel. For example, the contour gain could be incremented for every 5 dB, or so,
of decrease of the volume setting. This needs to be done by the microcontroller. The 0 dB contour setting is equal to
contour off.

Table 55 Subaddress 28

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00010010 18
00010001 17
00010000 16
00001111 15
00001110 14
00001101 13
00001100 12
00001011 11
00001010 10
00001001 9
00001000 8
00000111 7
00000110 6
00000101 5
00000100 4
00000011 3
00000010 2
00000001 1
00000000 0 (note 1)

CONTOUR GAIN (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 56

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.25 BASS CONTROL REGISTER (MAIN)
This register is used to apply bass control to the left and right signal channels of the Main channel.

Table 56 Subaddress 29

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10

00010101 −11
00010100 −12

BASS SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 57

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.26 TREBLE CONTROL REGISTER (MAIN)
This register is used to apply treble control to the left and right signal channels of the Main channel.

Table 57 Subaddress 30

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10
00010101 −11
00010100 −12

TREBLE SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 58

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.27 AUXILIARY CHANNEL SELECT REGISTER
This register is used to define both the signal source to be processed in the Auxiliary (headphone) channel and the mode

of the digital matrix for signal selection.

Table 58 Subaddress 31 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

6B6−output channel selection (see Table 59)
5B5
4B4
3 B3 0 default value
2B2−signal source selection (see Table 60)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 59 Output channel selection

B6 B5 B4 L OUTPUT R OUTPUT

0 0 0 L input R input
0 0 1 L input L input
0 1 0 R input R input
0 1 1 R input L input
100

Table 60 Signal source selection

B2 B1 B0 SIGNAL SOURCE

0 0 0 FM input
0 0 1 don’t care
010 I
011 I
1 0 0 ADC input
1 0 1 AVL input

LR+

------------- ­2

2

S1 input

2

S2 input

LR+

------------- ­2

1999 Dec 20 59

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.28 VOLUME CONTROL REGISTERS (AUXILIARY)
These two registers control the volume setting of the Auxiliary (headphone) channel. The register at subaddress 32

applies to the left channel signal, while the register at subaddress 33 applies to the right channel signal.
Balance control is exercised by offsetting the left and right channel volume settings.

Table 61 Subaddresses 32 and 33

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00011000 +24
00010111 +23
00010110 +22
00010101 +21
00010100 +20
00010011 +19
00010010 +18
00010001 +17
00010000 +16
00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0
11111111 −1
11111110 −2
11111101 −3
11111100 −4
11111011 −5
11111010 −6
11111001 −7
11111000 −8
11110111 −9
11110110 −10

VOLUME SETTING (dB)

1999 Dec 20 60

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

11110101 −11
11110100 −12

11110011 −13
11110010 −14
11110001 −15
11110000 −16
11101111 −17
11101110 −18
11101101 −19
11101100 −20
11101011 −21
11101010 −22
11101001 −23
11101000 −24
11100111 −25
11100110 −26
11100101 −27
11100100 −28
11100011 −29
11100010 −30
11100001 −31
11100000 −32
11011111 −33
11011110 −34
11011101 −35
11011100 −36
11011011 −37
11011010 −38
11011001 −39
11011000 −40
11010111 −41
11010110 −42
11010101 −43
11010100 −44
11010011 −45
11010010 −46
11010001 −47
11010000 −48
11001111 −49
11001110 −50
11001101 −51

VOLUME SETTING (dB)

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Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

11001100 −52
11001011 −53
11001010 −54

11001001 −55
11001000 −56
11000111 −57
11000110 −58
11000101 −59
11000100 −60
11000011 −61
11000010 −62
11000001 −63
11000000 −64
10111111 −65
10111110 −66
10111101 −67
10111100 −68
10111011 −69
10111010 −70
10111001 −71
10111000 −72
10110111 −73
10110110 −74
10110101 −75
10110100 −76
10110011 −77
10110010 −78
10110001 −79
10110000 −80
10101111 −81
10101110 −82
10101101 −83
10101100 mute (note 1)

VOLUME SETTING (dB)

Note

1. The default setting at power-up is 10101100.

1999 Dec 20 62

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.29 BASS CONTROL REGISTER (AUXILIARY)
This register is used to apply bass control to the left and right signal channels of the Auxiliary channel.

Table 62 Subaddress 34

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10

00010101 −11
00010100 −12

BASS SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 63

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.30 TREBLE CONTROL REGISTER (AUXILIARY)
This register is used to apply treble control to the left and right signal channels of the Auxiliary channel.

Table 63 Subaddress 35

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

XXX01100 +12
XXX01011 +11
XXX01010 +10
XXX01001 +9
XXX01000 +8
XXX00111 +7
XXX00110 +6
XXX00101 +5
XXX00100 +4
XXX00011 +3
XXX00010 +2
XXX00001 +1
XXX00000 0(note 1)
XXX11111 −1
XXX11110 −2
XXX11101 −3
XXX11100 −4
XXX11011 −5
XXX11010 −6
XXX11001 −7
XXX11000 −8
XXX10111 −9
XXX10110 −10
XXX10101 −11
XXX10100 −12

TREBLE SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 64

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.31 FEATURE INTERFACE CONFIGURATION REGISTER

Table 64 Subaddress 36 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

6 B6 0 default value
5 B5 0 default value
4 SYSCL1 − system clock frequency selection (see Table 65)
3 SYSCL0
2 SYSOUT 1 enables the output of a system (or master) clock signal at pin SYSCLK

0 the output will be off, thereby improving the EMC performance

1I

0 (LSB) I

2

SFORM 1 an MSB-aligned (MSB-first) serial output format is selected, i.e. a level change at

pin WS indicates the beginning of a new audio sample

0 the standard I

2

SOUT 1 enables the I2S-bus outputs (both serial data outputs plus serial bit clock and word

2

S-bus output format is selected

select) in a format determined by bit I2SFORM; the TDA9870A is then an I2S-bus
master

0 the outputs mentioned will be 3-stated, thereby improving the EMC performance

Note

1. The default setting at power-up is 00000000.

Table 65 System clock frequency selection

B4 B3 SYSCLK OUTPUT FREQUENCY (MHz)

0 0 256f
0 1 384f
1 0 512f
1 1 768f

Note

1. With 16.384 MHz the duty cycle is 33%.

s
s
s
s

8.192

12.288

16.384

24.576

(1)

1999 Dec 20 65

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.32 I2S1 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at I2S1 and the mode of the digital matrix for signal

selection.

Table 66 Subaddress 37 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

6B6−output selection (see Table 67)
5B5
4B4
3 B3 0 default value
2B2−signal source selection (see Table 68)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 67 Output selection

B6 B5 B4 L OUTPUT R OUTPUT

0 0 0 L input R input
0 0 1 L input L input
0 1 0 Rinput R input
0 1 1 Rinput L input
100

Table 68 Signal source selection (note 1)

B2 B1 B0 SIGNAL SOURCE

0 0 0 FM output
0 0 1 don’t care
010 I
011 I
1 0 0 ADC output
1 0 1 AVL output
1 1 0 Auxiliary output
1 1 1 Main output

LR+

------------- ­2

2

S1 input

2

S2 input

LR+

------------- ­2

Note

1. The Main and Auxiliary channel outputs will not contain the beeper signal.

1999 Dec 20 66

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.33 I2S1 INPUT LEVEL ADJUST REGISTER
This register is used to adjust the input level at the I2S1 interface. Left and right signal channel are treated identically.

Table 69 Subaddress 38

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10
00010101 −11
00010100 −12
00010011 −13
00010010 −14
00010001 −15
00010000 mute

GAIN SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 67

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.34 I2S1 OUTPUT LEVEL ADJUST REGISTER
This register is used to adjust the output level at the I2S1 interface. Left and right signal channel are treated identically.

Table 70 Subaddress 39

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10
00010101 −11
00010100 −12
00010011 −13
00010010 −14
00010001 −15
00010000 mute

GAIN SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 68

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.35 I2S2 OUTPUT SELECT REGISTER
This register is used to define both the signal source to be output at I2S2 and the mode of the digital matrix for signal

selection.

Table 71 Subaddress 40 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 0 default value

6B6−output selection (see Table 72)
5B5
4B4
3 B3 0 default value
2B2−signal source selection (see Table 73)
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 72 Output selection

B6 B5 B4 L OUTPUT R OUTPUT

0 0 0 L input R input
0 0 1 L input L input
0 1 0 Rinput R input
0 1 1 Rinput L input
100

Table 73 Signal source selection (note 1)

B2 B1 B0 SIGNAL SOURCE

0 0 0 FM output
0 0 1 don’t care
010 I
011 I
1 0 0 ADC output
1 0 1 AVL output
1 1 0 Auxiliary output
1 1 1 Main output

LR+

------------- ­2

2

S1 input

2

S2 input

LR+

------------- ­2

Note

1. The Main and Auxiliary channel outputs will not contain the beeper signal.

1999 Dec 20 69

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.36 I2S2 INPUT LEVEL ADJUST REGISTER
This register is used to adjust the input level at the I2S2 interface. Left and right signal channel are treated identically.

Table 74 Subaddress 41

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10
00010101 −11
00010100 −12

00010011 −13
00010010 −14
00010001 −15
00010000 mute

GAIN SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 70

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.37 I2S2 OUTPUT LEVEL ADJUST REGISTER
This register is used to adjust the output level at the I2S2 interface. Left and right signal channel are treated identically.

Table 75 Subaddress 42

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00001111 +15
00001110 +14
00001101 +13
00001100 +12
00001011 +11
00001010 +10
00001001 +9
00001000 +8
00000111 +7
00000110 +6
00000101 +5
00000100 +4
00000011 +3
00000010 +2
00000001 +1
00000000 0(note 1)
00011111 −1
00011110 −2
00011101 −3
00011100 −4
00011011 −5
00011010 −6
00011001 −7
00011000 −8
00010111 −9
00010110 −10
00010101 −11
00010100 −12

00010011 −13
00010010 −14
00010001 −15
00010000 mute

GAIN SETTING (dB)

Note

1. The default setting at power-up is 00000000.

1999 Dec 20 71

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.38 BEEPER FREQUENCY CONTROL REGISTER
This register is used to select from sample beeper oscillator frequencies. The beeper output signal is added to the Main

and Auxiliary channel output DAC.
Due to the frequency response of the audio DACs upsampling filters, the 25 kHz beep is approximately 5 dB louder than

the 390 Hz beep.

Table 76 Subaddress 43 (note 1)

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00000111 25000
00000110 7040
00000101 3580
00000100 1770
00000011 1270
00000010 900
00000001 640
00000000 390

Note

1. The default setting at power-up is 00000000.

10.3.39 BEEPER VOLUME CONTROL REGISTER
This register is used to set the beeper volume. The gain setting is relative to digital full-scale at the input to the Main and

Auxiliary channel output DACs. The beeper volume is independent of any other volume setting.
The beeper signal is added to the Main and Auxiliary channel output signals in the 2 × fs domain. The beeper volume

should be set with great care, when the audio signals in the Main and Auxiliary channels are close to digital full-scale, to
avoid output signal distortion due to overload.

GENERATED FREQUENCY (Hz)

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Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 77 Subaddress 44

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00000000 0
00111111 −3
00111110 −6
00111101 −9
00111100 −12
00111011 −15
00111010 −18

00111001 −21
00111000 −24
00110111 −27
00110110 −30
00110101 −33
00110100 −36
00110011 −39
00110010 −42
00110001 −45
00110000 −48
00101111 −51
00101110 −54
00101101 −57
00101100 −60
00101011 −63
00101010 −66
00101001 −69
00101000 −72
00100111 −75
00100110 −78
00100101 −81
00100100 −84
00100011 −87
00100010 −90
00100001 −93
00100000 mute (note 1)

GAIN SETTING (dB)

Note

1. The default setting at power-up is 00100000.

1999 Dec 20 73

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.3.40 BASS BOOST CONTROL REGISTER
This register is used to select from a few sample bass boost settings to modify the frequency characteristics of the Main

channel (shelving filter). Bits B3 to B0 apply to the left channel, bits B7 to B4 apply to the right channel. This function
must be used with care in order to avoid clipping distortion at high volume settings.

More sophisticated control of the bass boost filter can be exercised in the expert mode (see Section 10.5). The user then
has full control over this second-order filter and can, within limits, realize bass equalizers with arbitrary centre
frequencies, Q factors and boost/cut settings.

Table 78 Subaddress 45 (note 1)

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 − gain setting of right channel (see Table 79)

6B6
5B5
4B4
3B3−gain setting of left channel (see Table 80)
2B2
1B1

0 (LSB) B0

Note

1. The default setting at power-up is 00000000.

Table 79 Gain setting of right channel

B7 B6 B5 B4 GAIN SETTING (dB) CORNER FREQUENCY (Hz)

1010 20 350
1001 18 350
1000 16 350
0111 14 350
0110 12 350
0101 10 350
0100 8 350
0011 6 350
0010 4 350
0001 2 350
0000 0 350

1999 Dec 20 74

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 80 Gain setting of left channel

B3 B2 B1 B0 GAIN SETTING (dB) CORNER FREQUENCY (Hz)

1010 20 350
1001 18 350
1000 16 350
0111 14 350
0110 12 350
0101 10 350
0100 8 350
0011 6 350
0010 4 350
0001 2 350
0000 0 350

1999 Dec 20 75

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.4 Slave transmitter mode

As a slave transmitter, the TDA9870A provides 13 registers with status information and data, a part of which is for Philips
internal purposes only. These registers can be accessed by means of subaddresses.

Table 81 General format for reading data from the TDA9870A

S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE ADDRESS 1 ACK DATA NAm P

Table 82 Explanation of Tables 81 and 83

BIT FUNCTION

S START condition
SLAVE ADDRESS 7-bit device address
0 data direction bit (write to device)
ACK acknowledge (by the slave)
SUBADDRESS address of register to read from
Sr repeated START condition
1 data direction bit (read from device)
DATA data byte read from register
NAm not acknowledge (by the master)
Am acknowledge (by the master)
P STOP condition

Reading of data can start at any valid subaddress. It is allowed to read more than 1 data byte per transmission from the
TDA9870A. In this situation, the subaddress is automatically incremented after each data byte, which results in reading
the sequence of data bytes from successive register locations, starting at SUBADDRESS.

Table 83 Format of a transmission using automatic incrementing of subaddresses

S SLAVE ADDRESS 0 ACK SUBADDRESS ACK Sr SLAVE

ADDRESS

Note

1. n data bytes with auto-increment of subaddresses.

Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master).
The subaddresses ‘wrap around’ from decimal 255 to 0. If an attempt is made to read from a non-existing subaddress,
the device will send a data pattern of all ones, i.e. FF in hexadecimal notation.

1 ACK DATA BYTE

Am

(1)

DATA NAm P

1999 Dec 20 76

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 84 Overview of the slave transmitter registers; note 1

SUBADDRESS

(DECIMAL)

0 s s X X X s s s device status (power-on, identification, etc.)
1 XXXXXXXXdon’t care; note 1
2 XXXXXXXXdon’t care; note 1
3 XXXXXXXXdon’t care; note 1
4 XXXXXXXXdon’t care; note 1
5 lllllllllevel read-out (MSB)
6 lllllllllevel read-out (LSB)

7 XXXcccccSIF level
251 aaaaaaaatest register 3; note 2
252 aaaaaaaatest register 2; note 2
253 aaaaaaaatest register 1; note 2
254 dddddddddevice identification code
255 sssssssssoftware identification code

Notes

1. X indicates a bit that has not been assigned to a function. This bit is reserved for future extensions.

2. Registers from subaddress 251 to 255 are for Philips internal purposes only. They are considered as a set of
registers for the identification of individual members and some key parameters in a family of devices.

MSB LSB

DATA

FUNCTION

The following sub-sections provide a detailed description of the slave transmitter registers.

1999 Dec 20 77

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.4.1 DEVICE STATUS REGISTER

Table 85 Subaddress 0

BIT NAME VALUE DESCRIPTION

7 (MSB) P2IN − This bit reflects the status of the corresponding general purpose port of pin P2

(see Section 10.3.2).

6 P1IN − This bit reflects the status of the corresponding general purpose port of pin P1

(see Section 10.3.2).
5B5−don’t care
4B4−don’t care
3B3−don’t care
2 IDDUA − This bit is logic 1 if an FM dual-language signal has been identified. When

neither IDSTE nor IDDUA are set, the received signal has to be assumed to be

FM mono.
1 IDSTE − This bit is logic 1 if an FM stereo signal has been identified.

0 (LSB) POR − Power fail bit: the power supply for the digital part of the device, V

temporarily been lower than the specified lower limit. If this is detected an

initialization of the TDA9870A has to be carried out to ensure a reliable

operation.

DDD2

, has

10.4.2 REGISTER 1
Subaddress 1: These bits have not been assigned to a function. These bits are reserved for future extensions.

10.4.3 REGISTER 2
Subaddress 2: These bits have not been assigned to a function. These bits are reserved for future extensions.

10.4.4 REGISTER 3
Subaddress 3: These bits have not been assigned to a function. These bits are reserved for future extensions.

10.4.5 REGISTER 4
Subaddress 4: These bits have not been assigned to a function. These bits are reserved for future extensions.

1999 Dec 20 78

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.4.6 LEVEL READ-OUT REGISTERS
These two bytes constitute a word that provides data from

a location that has been specified with the monitor select
register. The most significant byte of the data is stored at
subaddress 5.

If peak-level monitoring has been selected, the peak-level
monitoring register is cleared and monitoring resumes
after its contents has been transferred to these two bytes.

Table 86 Subaddresses 5 and 6

SUB-

ADDRESS

5 7 (MSB) most significant bit or sign bit

6 7 (MSB)

10.4.7 SIF LEVEL REGISTER
When the SIF AGC is on, bits B4 to B0 of this register

contain a number that gives an indication of the SIF input
level. That number corresponds to the AGC gain register
setting (see Section 10.3.1).

BIT DESCRIPTION

6
5
4
3
2
1

0 (LSB)

6
5
4
3
2
1

0 (LSB) least significant bit

Table 87 Subaddress 7

BIT NAME VALUE DESCRIPTION

7 (MSB) B7 X bit not assigned

6 B6 X bit not assigned
5 B5 X bit not assigned
4B4 −indication of SIF
3B3
2B2
1B1

0 (LSB) B0

10.4.8 TEST REGISTER 3
This register contains, as a binary number, the highest

memory address used for the Coefficient RAM (CRAM,
expert mode).

Table 88 Subaddress 251

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

01111111

10.4.9 T
This register contains, as a binary number, the highest

subaddress used for slave receiver registers.

Table 89 Subaddress 252

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00101101

EST REGISTER 2

input level

When the SIF AGC is off, this register returns the contents
of the AGC gain register.

1999 Dec 20 79

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

10.4.10 TEST REGISTER 1
This register contains, as a binary number, the highest

subaddress used for slave transmitter (status) registers.

Table 90 Subaddress 253

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00000111

10.4.11 D

EVICE IDENTIFICATION CODE

There will be several devices in the digital TV sound
processorfamily.Thisbyteisusedtoidentifytheindividual
family members.

Table 91 Subaddress 254

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00100010

10.4.12 S

OFTWARE IDENTIFICATION CODE

It is likely that during the life time of this family of devices
several versions of the DSP software will be made, e.g., to
accommodate new application concepts, respond to
customer wishes, etc. This byte is used to identify the
different releases.

Table 92 Subaddress 255

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

00000010

10.5 Expert mode

In addition to the slave receiver and slave transmitter
modes previously described, there is a special ‘expert’
mode that gives direct write access to the internal CRAM
of the DSP.

In this mode, transferred data contains 12-bit coefficients.
As these coefficients bypass on-chip coefficient look-up
tables for many functions, they directly influence the
processing of signals within the DSP.

This mode must be used with great care. It can be used to
create user-defined characteristics, such as a tone control
with different corner frequencies or special boost/cut
characteristics to correct the low-frequency loudspeaker
and/or cabinet frequency responses.

As the coefficients do not fit into one data byte, they have
to be split and arranged (see Table 95). The most
significant bit is transferred first.

The general format described in Table 95 shows the
minimum number of data bytes required, i.e. two bytes for
the transfer of a single coefficient.

Should more than one coefficient be sent, then the CRAM
address will be automatically incremented after each
coefficient, resulting in writing the sequence of coefficients
into successive memory locations, starting at
CRAM ADDRESS. A transmission can start with any valid
CRAM address. If two coefficients are to be transferred,
they are arranged as shown in Table 96.

With any odd number of coefficients to be transferred, the
least significant nibble of the last byte is regarded as
containing don’t care data.

As the transfer of coefficients cannot be accomplished
within one audio sample period, it is necessary that
receivedcoefficientsbebufferedandmadeactive all at the
same time to avoid audio signal transients. The receive
buffer is designed to store up to 8 coefficients in addition
to the CRAM address. Each byte that fits into the buffer is
acknowledged with ACK (acknowledge). If an attempt is
made to write more coefficients than the buffer can store,
the device acknowledges with NACK (not acknowledge)
and any further coefficients are ignored. Coefficients that
are already in the receive buffer remain intact.

An expert mode transfer ends when the I

2

C-bus STOP
condition or a repeated START condition has been
detected. Only those coefficients that have been received
during the last transmission will then be copied from the
buffer to the CRAM.

To make efficient and correct use of the expert mode, it is
recommended to transfer all coefficients for any one
function in a single transmission.

There is no checking of memory addresses and the
automatic incrementing of addresses does not stop at the
highestusedCRAMaddress.Theuserofthisexpertmode
must be fully acquainted with the relevant procedures.

More information concerning the functions of this device,
such as the number of coefficients per function, their
default values, memory addresses, etc., can be supplied
on request at a later date.

1999 Dec 20 80

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

Table 93 General format for entering the expert mode and writing coefficients into the TDA9870A

S SLAVE

ADDRESS

Table 94 Explanation of Table 93

BIT FUNCTION

S START condition
SLAVE ADDRESS 7-bit device address
0 data direction bit (write to device)
ACK acknowledge
10000000 pattern to enter the expert mode
CRAM ADDRESS start address of coefficient RAM to write to
DATA data byte containing part of a coefficient
P STOP condition

Table 95 General format (notes 1, 2 and 3)

BYTE DATA DESCRIPTION

1 data byte aaaaaaaa2MST of 1st coefficient
2 data byte aaaaXXXX1LST of 1st coefficient

Notes

1. X = don’t care.

2. MST = most significant third.

3. LST = least significant third.

0 ACK 10000000 ACK CRAM

ADDRESS

ACK DATA ACK DATA ACK P

Table 96 Transfer of two coefficients

BYTE DATA DESCRIPTION

1 data byte aaaaaaaa2MST of 1st coefficient
2 data byte aaaabbbb1LST of 1st coefficient + 1 MST of 2nd coefficient
3 data byte bbbbbbbb2LST of 2nd coefficient

1999 Dec 20 81

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

11 I2S-BUS DESCRIPTION

The feature interface of the TDA9870A contains two serial
audio inputs and outputs and associated clock signals.
It can be used to supply, for example, audio signals from
received TV programs to a digital audio output device
(AES/EBU format), or import serial audio signals from
other sources for reproduction through the TV set’s
loudspeakerand/orheadphonechannels.Apartfromsuch
simple data input or output, it is also possible to run audio
signals through an external DSP, which performs some
additional functions, such as room simulation, Dolby
Surround Pro Logic etc. and feed those signals back into
the loudspeaker and/or headphone channels of the
TDA9870A.

Two serial audio formats are supported at the feature
interface, i.e. the I2S-bus format and a very similar
MSB-aligned format. The difference is illustrated in Fig.9.

In both formats the left audio channel of a stereo sample
pair is output first and is placed on the serial data line (SDI
for input, SDO for output) when the Word Select line (WS)
is LOW. Data is written at the trailing edge of SCK and
read at the leading edge of SCK. The most significant bit
is sent first.

At power-up, the outputs of the feature interface are
3-stated to reduce EMC and allow for combinations with
other ICs. If output is desired, it has to be activated by
means of an I2C-bus command.

When the output is enabled, the serial audio data can be
taken from pins SDO1 and SDO2. Depending on the
signal source, switch and matrix positions, the output can
be either mono, stereo or dual language sound on either
output.

Apart from just feeding a digital audio device, such as a
DAC or an AES/EBU transmitter, the serial data outputs
can be connected directly to the serial inputs (loop-back
connection) or first to an external device, e.g. a feature
DSP such as the SAA7710 and then back to the serial
inputs. In all of these configurations, the SCK and WS
clocks will be generated by the TDA9870A, which then is

2

the I

S-bus master.

The serial data inputs, SDI1 and SDI2, are active at all
times, independent of the serial data outputs being on or
off. When the serial data outputs are off (either after
power-up or via the appropriate I2C-bus command) serial
dataandclocksWS and SCK from a separate digital audio
source can be fed into the TDA9870A, be processed and
output in accordance with internal selector positions,
provided that the following criteria are met:

• 32 kHz audio sample frequency

• 32 clock bits per sample

• External timing and data synchronized to TDA9870A.

In such cases, the external source is the I2S-bus master
and the TDA9870A is the I2S-bus slave.

To support synchronization of external devices or as a
master clock for them, a system clock output, SYSCLK, is
available from the TDA9870A. At power-up it is off. It can
be enabled and the output frequency set via an I2C-bus
command. Available output frequencies are

8.192, 12.288, 16.384 and 24.576 MHz.

The word select output is clocked with the audio sample
frequency at 32 kHz. The serial clock output (SCK) is
clocked at a frequency of 2.048 MHz. This means, that
there are 64 clock pulses per pair of stereo output
samples, or 32 clock pulses per sample. Depending again
on the signal source, the number of significant bits on the
serial data outputs, SDO1 and SDO2, is between
14 and 18.

1999 Dec 20 82

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

handbook, full pagewidth

SCK

WS

SD LSB MSB

handbook, full pagewidth

SCK

WS

SD LSB MSB

LSB MSB

MGK112

one sample

a. I2S-bus format.

LSB MSB

MGK113

one sample

b. MSB-aligned format.

Fig.9 Serial audio interface formats.

1999 Dec 20 83

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

12 APPLICATION INFORMATION

handbook, full pagewidth

SIFSAT

SIFTV

+5 V

R2

1.5 Ω

C1

4.7 µF

C2

47 pF

C4

47 pF

C5
47 µF

24.576 MHz

C7

470 nF

C8

470 nF

C9

470 nF

10 kΩ

C3

100 nF

C6

1 µF

ADDR1

V

V

R1

ADDR2

V

V

CRESET

V

XTALO

SYSCLK

TEST1

MONOIN

TEST2

EXTIR

SCL

SDA

SSA1

DEC1

SIF2

V

ref1

SIF1

SSD1

DDD1

SSD4

XTALI

SCK

WS

SDO2

SDO1

SDI2

SDI1

EXTIL

i.c.

1 (57)

1

2 (58)

2

3 (59)

3

4 (60)

4

5 (61)

5

6 (62)

6

7 (63)

7

I

ref

8 (64)

8

P1

9 (1)

9

10 (2)

10

11 (3)

11

12 (4)

12

13 (5)

13

14 (6)

14

15 (7)

15

16 (8)

16

17 (9)

17

18 (10)

18

19 (11)

19

P2

20 (12)

20

21 (13)

21

22 (14)

22

23 (15)

23

24 (16)

24

25 (17)

25

26 (18)

26

27 (19)

27

28 (20)

28

29 (21)

29

30 (22)

30

31 (23)

31

32 (24)

32

The pin numbers given in parenthesis refer to the TDA9870AH version.

TDA9870A

(TDA9870AH)

(56) 64

(55) 63

(54) 62

(53) 61

(52) 60

(51) 59

(50) 58

(49) 57

(48) 56

(47) 55

(46) 54

(45) 53

(44) 52

(43) 51

(42) 50

(41) 49

(40) 48

(39) 47

(38) 46

(37) 45

(36) 44

(35) 43

(34) 42

(33) 41

(32) 40

(31) 39

(30) 38

(29) 37

(28) 36

(27) 35

(26) 34

(25) 33

MHB596

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

V

DDD2

LORi.c.

LOL

MOL

MOR

V

DDA

AUXOL

AUXOR

V

SSA3

PCAPL

PCAPR

V

ref3

SCOL2

SCOR2

V

SSA4

V

SSD2

SCOL1

SCOR1

V

ref2

i.c.

i.c.

V

SSA2

i.c.

i.c.

V

ref(n)

V

ref(p)

V

DEC2

SCIL2

SCIR2

V

SSD3

SCIL1

SCIR1

C35

C31

C29

C28

C26

C24

R6

15 kΩ

R3

15 kΩ

10 nF

47 µF

C16

47 µF

C15
47 µF

15 kΩ

C23

C21

R5

15 kΩ

R4

47 µF

10 nF

10 nF

47 µF

10 nF

10 nF

2.2 µF

270 Ω

2.2 µF

2.2 µF

2.2 µF

C19

C17

2.2 µF

R7

C13

330 nF

C11

330 nF

R19

1.5 Ω

C33

C30

C27

C22

10 nF

C34

2.2 µF

2.2 µF

2.2 Ω

2.2 µF

C20

2.2 µF

C18

2.2 µF

C12

330 nF

C10

330 nF

C32

R8

C25

C14

4.7 µF

+5 V

+5 V

Fig.10 Schematic for measurements.

1999 Dec 20 84

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

handbook, full pagewidth

POWER

0 V

SIFSAT

SIFTV

+5 V

100 Ω

C2
470 nF

C3

47 pF

C5

47 pF

R5

1 Ω

C8

470 nF

C9

470 nF

+5 V

47 µFC1

R1

R2

100 Ω

R4

2.2 kΩ
L3

L4

C6
470 nF

24.576 MHz

R6

2.2 kΩ

L6

L7

C10

470 nF

i.c.

1 (57)

2 (58)

ADDR1

SCL

SDA

V

SSA1

V

DEC1

I

SIF2

V

ref1

SIF1

ADDR2

V

SSD1

V

DDD1

CRESET

V

SSD4

XTALI

XTALO

SYSCLK

SCK

WS

SDO2

SDO1

SDI2

SDI1

TEST1

MONOIN

TEST2

EXTIR

EXTIL

3 (59)

4 (60)

5 (61)

6 (62)

7 (63)

ref

8 (64)

P1

9 (1)

10 (2)

11 (3)

12 (4)

13 (5)

14 (6)

15 (7)

16 (8)

17 (9)

18 (10)

19 (11)

P2

20 (12)

21 (13)

22 (14)

23 (15)

24 (16)

25 (17)

26 (18)

27 (19)

28 (20)

29 (21)

30 (22)

31 (23)

32 (24)

L1

L2

R3

10 kΩ

C4

100 nF

L5

C7

1 µF

L8

L1 to L9 are ferrite beads.
The pin numbers given in parenthesis refer to the TDA9870AH version.

TDA9870A

(TDA9870AH)

(56) 64

(55) 63

(54) 62

(53) 61

(52) 60

(51) 59

(50) 58

(49) 57

(48) 56

(47) 55

(46) 54

(45) 53

(44) 52

(43) 51

(42) 50

(41) 49

(40) 48

(39) 47

(38) 46

(37) 45

(36) 44

(35) 43

(34) 42

(33) 41

(32) 40

(31) 39

(30) 38

(29) 37

(28) 36

(27) 35

(26) 34

(25) 33

MHB597

V

DDD2

LORi.c.

LOL

MOL

MOR

V

DDA

AUXOL

AUXOR

V

SSA3

PCAPL

PCAPR

V

ref3

SCOL2

SCOR2

V

SSA4

V

SSD2

SCOL1

SCOR1

V

ref2

i.c.

i.c.

V

SSA2

i.c.

i.c.

V

ref(n)

V

ref(p)

V

DEC2

SCIL2

SCIR2

V

SSD3

SCIL1

SCIR1

L9

C42

C40

C38

C36

C34 10 nF

C32

C31 10 nF

C30

C28

10 nF

C26

47 µF

C24

C22

C20

C18

C16
47 µF

R10

15 kΩ

R9

15 kΩ

R8

15 kΩ

R7

15 kΩ

470 pF

470 pF

10 nF

470 nF

10 nF

470 pF

470 pF

470 pF

470 pF

R11

270 Ω

330 nF

470

nF

C39

2.2 µF

2.2 µF

10 nF

C14

C12

330 nF

R13

1 Ω

2.2 µF

C35

C33

C27

C23

2.2 µF

C19

2.2 µF

330 nF

330 nF

C13

C11

C41

2.2 µF

C37

2.2 µF

R12

2.2 Ω

C29

2.2 µF

C25

2.2 µF

C21

2.2 µF

C17

47 µF

C15
470 nF

+5 V

+5 V

Fig.11 Schematic for application.

1999 Dec 20 85

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

13 PACKAGE OUTLINES

SDIP64: plastic shrink dual in-line package; 64 leads (750 mil)

SOT274-1

seating plane

L

Z

64

1

pin 1 index

D

A

2

A

A

1

e

b

w

b

1

33

32

M

E

c

M

(e )

M

E

1

H

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

A

A

UNIT b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

5.84

OUTLINE

VERSION

SOT274-1 MS-021

12

min.

max.

4.57

0.51

IEC JEDEC EIAJ

1.3

0.8

b

1

0.53

0.40

REFERENCES

0.32

0.23

cEe M

(1) (1)

D

58.67

57.70

1999 Dec 20 86

17.2

16.9

1

L

M

E

3.2

19.61

2.8

19.05

EUROPEAN

PROJECTION

20.96

19.71

e

w

H

0.181.778 19.05

ISSUE DATE

95-02-04
99-12-27

max.

1.73

(1)

Z

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm

c

y

X

A

48 33

49

pin 1 index

64

1

32

Z

E

e

A

H

E

E

2

A

A

1

w M

b

p

17

16

detail X

SOT393-1

(A )

3

θ

L

p

L

w M

b

e

p

D

H

D

Z

D

B

v M

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.00

0.25

0.10

2.75

2.55

0.25

UNIT A1A2A3b

cE

p

0.45

0.23

0.30

0.13

(1)

(1) (1)(1)

D

14.1

13.9

eH

14.1

13.9

0.8

17.45

16.95

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT393-1 MS-022

1999 Dec 20 87

v M

A

B

E

17.45

16.95

LL

p

1.03

0.73

0.16 0.100.161.60

H

D

EUROPEAN

PROJECTION

Z

D

1.2

0.8

Zywv θ

E

o

1.2

7

o

0.8

0

ISSUE DATE

97-08-04
99-12-27

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

14 SOLDERING

14.1 Introduction

Thistextgivesaverybriefinsighttoa complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when
through-holeandsurfacemountcomponents are mixedon
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.

14.2 Through-hole mount packages

14.2.1 SOLDERING BY DIPPING OR BY SOLDER WAVE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

14.2.2 MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the

package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

14.3 Surface mount packages

14.3.1 REFLOW SOLDERING
Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboardbyscreenprinting,stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

stg(max)

). If the

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

14.3.2 WAVE SOLDERING
Conventional single wave soldering is not recommended

forsurfacemountdevices(SMDs)orprinted-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

14.3.3 MANUAL SOLDERING

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Dec 20 88

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

14.4 Suitability of IC packages for wave, reflow and dipping soldering methods

MOUNTING PACKAGE

Through-hole mount DBS, DIP, HDIP, SDIP, SIL suitable

WAVE REFLOW

(2)

− suitable

(1)

DIPPING

Surface mount BGA, SQFP not suitable suitable −

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP,

not suitable

(3)

suitable −

SMS

(4)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

, SO, SOJ suitable suitable −

(4)(5)

suitable −

(6)

suitable −

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1999 Dec 20 89

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

15 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

16 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

17 PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1999 Dec 20 90

Philips Semiconductors Product specification

Digital TV Sound Processor (DTVSP) TDA9870A

NOTES

1999 Dec 20 91

Philips Semiconductors – a w orldwide compan y

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Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

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Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract,isbelievedtobeaccurateand reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/02/pp92 Date of release: 1999 Dec 20 Document order number: 9397 750 06064