Datasheet TDA9853H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA9853H

2

I

C-bus controlled economic BTSC
stereo decoder and audio
processor

Product specification
File under Integrated Circuits, IC02

2000 Dec 11

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

FEATURES

• Voltage Controlled Amplifier (VCA) noise reduction
circuit

• Stereo or mono selectable at the AF outputs

• Stereo pilot PLL circuit with ceramic resonator

• Automatic pilot cancellation

• I2C-bus transceiver.

Audio processor

• Selector for internal and external signals (line in)

• Automatic Volume Level (AVL) control
(control range +6 to −15 dB)

• Volume control (control range +12 to −63 dB)

• Mute control via I2C-bus

• 4 fixed tone settings.

ORDERING INFORMATION

GENERAL DESCRIPTION

The TDA9853H is a bipolar-integrated BTSC stereo
decoder and audio processor for application in TV sets,
VCRs and multimedia PCs.

TDA9853H

TYPE

NUMBER

TDA9853H QFP44 plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 × 14 × 2.2 mm SOT205-1

NAME DESCRIPTION VERSION

PACKAGE

2000 Dec 11 2

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

V

o(rms)

α

csL,R

THD

S/N signal-to-noise ratioat line out

V

I, O(rms)

AVL AVL control range −15 − +6 dB
G

c

L

linear

L

bass(max)

L

bass(min)

L

treble(max)

L

treble(min)

supply voltage 7.8 8 9 V
supply current 25 33 45 mA
output voltage (RMS value) composite input voltage 250 mV (RMS)

− 500 − mV

for 100% modulation L + R

stereo channel separation

(25 kHz deviation); f
14% modulation; fL= 300 Hz; fR= 3 kHz 15 20 − dB

mod

= 300 Hz

L and R
total harmonic distortion

L,R

100% modulation L or R; f

= 1 kHz − 0.2 1 %

mod

L and R

2

C-bus; referenced to 500 mV

and at AF output

mono via I
output signal; volume 0 dB

CCIR 468-2 weighted; quasi peak 50 60 − dB
DIN noise weighting filter (RMS value) − 73 − dBA

signal handling (RMS value) THD < 0.5% 2 −−V

volume control range −63 − +12 dB
linear tone control − 0 − dB
tone control with maximum

bass
tone control with minimum

bass
tone control with maximum

treble
tone control with minimum

treble

referenced to linear position;
f

=20Hz

mod

referenced to linear position;
f

=20Hz

mod

referenced to linear position;
f

=20kHz

mod

referenced to linear position;
f

=20kHz

mod

10 12 − dB

3.5 5 − dB

68−dB

−−1.5 − dB

2000 Dec 11 3

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2000 Dec 11 4

C3

C2

R1

C4

Q1

C6C5

handbook, full pagewidth

External Input Right

(EIR)

C7

C8

C9

C10

C11

C12

BLOCK DIAGRAM

Philips Semiconductors Product specification

decoder and audio processor

I

2

C-bus controlled economic BTSC stereo

composite
baseband

input

C1

COMP

R2

FDO

R3

FDI

CP2CP1C

342

4

STEREO DECODER

35

33

DETECTOR

VOLTAGE CONTROLLED

AND

AMPLIFIER

32
BPU

C22C23

C

AV

29

AUTOMATIC

VOLUME

AND

LEVEL CONTROL

I2C-BUS

TRANSCEIVER

MAD

SCL SDA

DGND

VAR VIR

37383940

11
VAL VIL

VOLUME

RIGHT

CONTROL

VOLUME

LEFT

CONTROL

C16

TC1R21TC2R

2423

TONE

RIGHT

CONTROL

TONE

LEFT

CONTROL

10

TC1L13TC2L

C15

BCR
19

20

18

16

14

15
BCL

C14

C13

OUTR

OUTL

MHB789

41

V

CC

C

MO

5

DEMATRIX

MODE SELECT

SUPPLY

28
V

CAP

C19

CER

PH

432

L + R

L − R

31
C

W

C21

30
TW

C20

AND

C
6

AGND36V

LOR

SS

25

27

9
LOL

ref

External Input Left

(EIL)

LIR
26

INPUT

SELECT

FILTER

AND

REFERENCE

8
LIL

C17C18

TDA9853H

7
R

FR

R4

TDA9853H

Fig.1 Block diagram.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

Component list

Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.

COMPONENT VALUE TYPE REMARK

C1 2.2 µF electrolytic 63 V
C2 220 nF foil
C3 2.2 µF electrolytic 63 V
C4 220 nF foil
C5 2.2 µF electrolytic 63 V
C6 2.2 µF electrolytic 63 V
C7 2.2 µF electrolytic 63 V
C8 4.7 µF electrolytic 63 V ±10%
C9 2.2 µF electrolytic 63 V
C10 3.3 nF foil
C11 150 pF foil
C12 56 nF foil
C13 56 nF foil
C14 150 pF foil
C15 3.3 nF foil
C16 2.2 µF electrolytic 63 V
C17 2.2 µF electrolytic 63 V
C18 100 µF electrolytic 16 V
C19 100 µF electrolytic 16 V
C20 10 µF electrolytic 63 V
C21 1 µF electrolytic 63 V
C22 4.7 nF foil
C23 22 nF foil
R1 3.3 kΩ
R2 15 kΩ
R3 1.3 kΩ
R4 100 kΩ
Q1 CSB503F58 radial leads

CSB503JF958 alternative as SMD

2000 Dec 11 5

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
C

P2

C

P1

COMP 4 composite input signal
C

MO

C

SS

R

FR

LIL 8 line input; left channel
LOL 9 line output; left channel
VIL 10 volume control input; left channel
VAL 11 AVL output; left channel
n.c. 12 not connected
TC1L 13 treble capacitor 1; left channel
TC2L 14 treble capacitor 2; left channel
BCL 15 bass capacitor; left channel
OUTL 16 left channel output
n.c. 17 not connected
OUTR 18 right channel output
BCR 19 bass capacitor; right channel
TC2R 20 treble capacitor 2; right channel
TC1R 21 treble capacitor 1; right channel
n.c. 22 not connected
VAR 23 AVL output; right channel

2 connector 2 for pilot detector capacitor
3 connector 1 for pilot detector capacitor

5 capacitor for DC-decoupling mono
6 capacitor for DC-decoupling stereo
7 resistor for filter reference

TDA9853H

SYMBOL PIN DESCRIPTION

VIR 24 volume control input; right channel
LOR 25 line output; right channel
LIR 26 line input; right channel
V

ref

V

CAP

C

AV

TW 30 capacitor timing
C

W

BPU 32 band-pass filter upper corner

FDO 33 fixed de-emphasis output
n.c. 34 not connected
FDI 35 fixed de-emphasis input
AGND 36 analog ground
DGND 37 digital ground
SDA 38 serial data input/output
MAD 39 programmable address bit

SCL 40 serial clock input
V

CC

C

PH

CER 43 ceramic resonator
n.c. 44 not connected

27 reference voltage (0.5VCC)
28 capacitor for electronic filtering of

supply

29 capacitor for AVL

31 capacitor for VCA and band-pass filter

lower corner frequency

frequency

(module address)

41 supply voltage
42 capacitor for phase detector

2000 Dec 11 6

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

n.c.

CER

handbook, full pagewidth

n.c.

C

P2

C

P1

COMP

C

MO

C

SS

R

FR
LIL

LOL

VIL

VAL

44

1
2
3
4
5
6
7
8

9
10
11

CPHVCCSCL

43

42

41

40

TDA9853H

MAD
39

SDA
38

DGND
37

AGND
36

FDI
35

n.c.
34

TDA9853H

33

FDO

32

BPU

31

C

W

30

TW

29

C

AV

28

V

CAP

27

V

ref

26

LIR

25

LOR

24

VIR

23

VAR

12

13

14

15

n.c.

TC1L

TC2L

BCL

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION
Stereo decoder

The composite signal is fed into a pilot detector/pilot
cancellation circuit and into the MPX demodulator. The
main L + R signal passes a 75 µs fixed de-emphasis filter
andisfedinto the dematrix circuit. Thedecodedsub-signal
L − R is applied to the Volume Controlled Amplifier (VCA)
circuit. To generatethe pilot signalthe stereo demodulator
uses a PLL circuit including a ceramic resonator.

Mode selection

The L − R signal is fed via the internal VCA circuit to the
dematrix/switching circuit. Mode selection is achieved via
the I2C-bus (see Table 9).

The dematrix outputs can be muted via the I2C-bus
(see Table 14).

16

17

18

19

20

21

22

MHB790

OUTL

n.c.

OUTR

BCR

TC2R

TC1R

n.c.

Automatic volume level control

The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from
an input voltage range between 0.1 to 1.1 V (RMS). The
circuitadjustsvariationsinmodulationduringbroadcasting
and because of changes in the programme material; this
functioncan be switchedoff. To avoid audibleplops during
the permanent operation of the AVL circuit a soft blending
scheme has been applied between the different gain
stages. A capacitor (4.7 µF) at pin CAV determines the
attack and decay time constants. In addition the ratio of
attack and decay times can be changed via the I2C-bus.

Integrated filters

The filter functions necessary for stereo demodulation are
provided on-chip using transconductor circuits. The filter
frequencies are controlled bythe filter reference circuit via
the external resistor R4.

2000 Dec 11 7

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

Audio processor

SELECTOR
Theselectorenablesthe selection of either theinternalline

output signals LOR and LOL (dematrix output) or the
external line input signals LIR and LIL (see Table 16). The
input signal capability of the line inputs (LIR/LIL) is
2 V (RMS). The output of the selector is DC-coupled to the
automatic volume level control circuit.

VOLUME
The volume control range is from +12 dB to −63 dB in

steps of 1 dB and ends with a mute step (see Table 8).
Balance control is achieved by the independent volume
control of each channel.

BASS FUNCTION
A single external 56 nF capacitor for each channel in

combinationwith a linearoperational amplifier andinternal
resistors provides a bass range of +12 dB for high bass
and +5 dB for low bass.

TDA9853H

TREBLE FUNCTION
Two external capacitors C15 = 3.3 nF and C14 = 150 pF

for each channel in combination with a linear operational
amplifier and internal resistors provide a treble range of
+8 dB for high treble and −1.5 dB for low treble.

MUTE
The mute functioncan be activatedindependently with the

last step of volume control at the left or right output. By
setting the general mute bit GMU the audio outputs OUTL
and OUTR are muted.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

SDA, VSCL

V

n

T

amb

T

stg

V

es

supply voltage − 9.5 V
voltage at pins SDA and SCL referenced

to GND
voltage of all other pins to GND 0 V

VCC≤ 9V −0.3 +V
V

>9V −0.3 +9 V

CC

CC

CC

V

V
ambient temperature −20 +70 °C
storage temperature −65 +150 °C
electrostatic handling voltage note 1 −200 +200 V

note 2 −2000 +2000 V

Notes

1. Machine model class B, equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (‘0 Ω’ is actually

0.75 µH+10Ω).

2. Human body model class B, equivalent to discharging a 100 pF capacitor through a 1500 Ω series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 70 K/W

2000 Dec 11 8

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

CHARACTERISTICS

All voltages are measured relative to GND; VCC=8V; Rs= 600 Ω; AC-coupled; RL=10kΩ; CL= 2.5 nF; f
mono signal; composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); pilot 50 mV (RMS);
Gv= 0 dB; linear tone control; AVL off; T

=25°C; see Fig.1; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CC

I

CC

V

ref

supply voltage 7.8 8 9 V
supply current 25 33 45 mA
internal reference voltage at

pin V

ref

0.45VCC0.5V

CC

0.55VCCV

Input stage

V

i(max)(rms)

maximum input voltage

2 −−V

(RMS value)

Z

i

input impedance 20 25 32 kΩ

Stereo decoder

HR headroom for L + R, L and R f
V

pil(rms)

nominal stereo pilot voltage

= 300 Hz; THD < 15% 9 −−dB

mod

− 50 − mV

(RMS value)

V

th(on)(rms)

pilot threshold voltage, stereo

−− 35 mV

on (RMS value)

V

th(off)(rms)

pilot threshold voltage, stereo

15 −−mV

off (RMS value)
hys hysteresis − 2.5 − dB
V

o(rms)

α

cs(L,R)

THD

L,R

S/N signal-to-noise ratio at line

output voltage (RMS value) 100% modulation L + R;

f

= 300 Hz

mod

stereo channel separation

L and R

total harmonic distortion

L and R

output and AF output

14% modulation; fL= 300 Hz;
fR= 3 kHz

100% modulation L or R;
f

= 1 kHz

mod

2

mono via I

C-bus; referenced

to 500 mV output signal

CCIR 468-2 weighted;

− 500 − mV

15 20 − dB

− 0.2 1 %

50 60 − dB

quasi peak
DIN noise weighting filter

− 73 − dBA

(RMS value)

α

mute

mute attenuation atLOL, LOR,

VAL and VAR

100% modulation L + R;
f

= 300 Hz; mute via bit E6

mod

63 −−dB

Stereo decoder, oscillator (VCXO); note 1
f

∆f

∆f

o

fr

cr

nominal VCXO output

frequency (32fH)

spread of free-running

frequency

with nominal ceramic
resonator

with nominal ceramic
resonator

− 503.5 − kHz

500 − 507 kHz

capture range frequency nominal pilot ±190 ±265 − Hz

mod

= 1 kHz

2000 Dec 11 9

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Audio control part; input pins VIL and VIR to pins OUTL and OUTR

V

O

Z

i

Z

o

R

L

C

L

V

i(max)(rms)

DC output voltage 0.45VCC0.5V

CC

volume input impedance 25 30 38 kΩ

output impedance − 80 120 Ω

output load resistance 5 −−kΩ

output load capacitance 0 − 2.5 nF

maximum input voltage

THD < 0.5% tbf 2 − V

(RMS value)
THD total harmonic distortion 1 V (RMS) input voltage − 0.05 − %
V

no

noise output voltage CCIR 468-2 weighted;

quasi peak

G

=10dB − 110 220 µV

v

=0dB − 33 50 µV

G

v

mute position − 10 −µV

G

c

volume control range maximum boost − 12 − dB

maximum attenuation − 63 − dB

G

step

∆G

a

∆G

L

α

m

V

DC(OS)

step resolution − 1 − dB

step error between adjoining

step

= +12 to −15 dB and

G

v

Gv= −16 to −63 dB; note 2

−− 0.5 dB

attenuator set error Gv= +12 to −50 dB −− 2dB

G

=−51 to −63 dB −− 3dB

v

gain tracking error Gv= +12 to −50 dB −− 2dB

mute attenuation 80 −−dB

DC step offset between any

adjacent step

DC step offset between any

step to mute

Gv= +12 to 0 dB − 0.2 10 mV
G

=0to−63 dB −− 5mV

v

G

= +12 to 0 dB − 215mV

v

=−1to−63 dB − 110mV

G

v

Tone control part

L

linear

L

bass(max)

L

bass(min)

L

treble(max)

L

treble(min)

linear tone control − 0 − dB

tone control with maximum

bass

tone control with minimum

bass

tone control with maximum

treble

tone control with minimum

treble

referenced to linear position;
f

=20Hz

mod

referenced to linear position;
f

=20Hz

mod

referenced to linear position;
f

= 20 kHz

mod

referenced to linear position;
f

= 20 kHz

mod

10 12 − dB

3.5 5 − dB

68 −dB

−−1.5 − dB

0.55VCCV

2000 Dec 11 10

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VCA

I

s

nominal timing current for

nominal release rate of VCA

detector
Rel

rate

nominal detector release rate nominal timing current and

Automatic volume level control

G

v

G

step

voltage gain maximum boost; note 3 5 6 7 dB

equivalent step width between

the input stages(soft switching

system)
V

i(rms)

V

o(AVL)(rms)

input voltage (RMS value) maximum boost; note 3 − 0.1 − V

output voltage in AVL

operation (RMS value)
V

offset(DC)

DC offset voltage between

different gain steps

R

att

discharge resistors for attack

time constant

I

dec

charge current for decay time normal mode; CCD = 0; note 6 1.6 2 2.4 µA

Selector internal and external

Z

i

α

s

input impedance 16 20 25 kΩ

input isolation of one selected

source to the other input
V

i(max)(rms)

maximum input voltage

(RMS value)
G

v

voltage gain, selector − 0 − dB

Line output; pins LOL and LOR

V

o(rms)

nominal output voltage

(RMS value)
HR

o

Z

o

V

O

R

L

C

L

output headroom 9 −−dB

output impedance − 80 120 Ω

DC output voltage 0.45VCC0.5V

output load resistance 5 −−kΩ

output load capacitance −− 2.5 nF

Is can be measured at pin TW

6.5 8 9.5 µA

via current meter connected to

0.5VCC+1V

− 125 − dB/s

external capacitor values

maximum attenuation; note 3 14 15 16 dB

− 1.5 − dB

maximum attenuation; note 3 − 1.125 − V

160 200 250 mV

voltage at pin C

AV

−− 20 mV

6 to 5.83 Vor 5.83 to 5.61 V or

5.61 to 4.83 Vor 4.83 to 2.1 V;
note 4

AT1 = 0; AT2 = 0; note 5 340 420 520 Ω
AT1 = 1; AT2 = 0; note 5 590 730 910 Ω
AT1 = 0; AT2 = 1; note 5 0.96 1.2 1.5 kΩ
AT1 = 1; AT2 = 1; note 5 1.7 2.1 2.6 kΩ

Power-on speed-up; CCD = 1;

− 30 −µA

note 6

Vi=1V; fi= 1 kHz 70 76 − dB
V

=1V; fi= 12.5 kHz 70 76 − dB

i

THD < 0.5% − 2 − V

100% modulation − 500 − mV

CC

0.55VCCV

2000 Dec 11 11

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Monitor output; pins VAL and VAR

V

O

R

L

C

L

DC output voltage − 0.5V

CC

output load resistance 5 −−kΩ

output load capacitance with 100 Ω in series −− 2.5 nF

Muting at power supply voltage drop for OUTR and OUTL

∆V

CC

supply voltage drop for mute

− V

CAP

active
Power-on reset; note 7
V

POR(start)

start of reset voltage increasing supply voltage −− 2.5 V

decreasing supply voltage − tbf − V

V

POR(end)

Digital part (I

V

IH

V

IL

I

IH

I

IL

V

OL

end of reset voltage increasing supply voltage − tbf − V

2

C-bus pins); note 8

HIGH-level input voltage 3 − V

LOW-level input voltage −0.3 − +1.5 V

HIGH-level input current −10 − +10 µA

LOW-level input current −10 − +10 µA

LOW-level output voltage IIL=3mA −− 0.4 V

Notes

1. The oscillator isdesigned to operatetogether withMurata resonator CSB503F58or CSB503JF958 as SMD.Change
of the resonator supplier is possible, but the resonator specification must be close to the specified ones.

2. 1.5 dB step error between −15 and −16 dB.

3. The AVL input voltage is internal. It corresponds to the output voltage OUTL and OUTR at AVL off.

4. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.

5. Attack time constant = C

C

CAV

6.

Decay time

a) Example: C

=

---------------------------------------------------------------------------------

= 4.7 µF; I

CAV

× R

CAV

0.76 V× 10





I

dec

dec

with C

att

G1–

---------­20

–

= C8 (see Fig.1).

CAV

G2–

---------­20

10

=2µA; G1= −9 dB; G2=+6dB→ decay time results in 4.14 s.

7. When reset is active the GMU bit (mute) is set and the I2C-bus receiver is in the reset position.

8. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency
maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated
between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification.
Information about the I2C-bus can be found in brochure

“I2C-bus and how to use it”

(order number 9398 393 40011).

9. Maximum 9 V if VCC>9V.

− V

− 0.7 − V

(9)

CC

V

2000 Dec 11 12

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

12

handbook, full pagewidth

gain
(dB)

8

4

0

−4
10

(1)

(3)

2

10

10

TDA9853H

MHB791

(2)

(4)

3

4

10

f (Hz)

5

10

(1) Maximum bass.
(2) Maximum treble.
(3) Minimum bass.
(4) Minimum treble.

Fig.3 Tone control.

2000 Dec 11 13

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

I2C-BUS PROTOCOL

2

C-bus format to read (slave transmits data)

I

S SLAVE ADDRESS R/

Table 1 Explanation of I

S START condition; generated by the master
Standard SLAVE ADDRESS (MAD) 1011011; pin MAD not connected
Pin programmable SLAVE ADDRESS 1011010; pin MAD connected to ground
R/

W logic 1 (read); generated by the master
A acknowledge; generated by the slave
DATA slave transmits an 8-bit data word
AN acknowledge not; generated by the master
P STOP condition; generated by the master

Table 2 Definition of the transmitted bytes after read condition

2

C-bus format to read (slave transmits data)

NAME DESCRIPTION

W A DATA AN P

TDA9853H

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

YYYYYYPONR STP

Table 3 Bit functions of Table 2

BIT FUNCTION

STP stereo pilot identification (stereo received = 1)
PONR Power-on reset; if PONR = 1, then Power-on reset is detected
Y indefinite

2

I

C-bus format to write (slave receives data)

S SLAVE ADDRESS R/

2

Table 4 Explanation of I

NAME DESCRIPTION

S START condition
Standard SLAVE ADDRESS 101 101 1; pin MAD not connected
Pin programmable SLAVE ADDRESS 101 101 0; pin MAD connected to ground
R/

W logic 0 (write)
A acknowledge; generated by the slave
SUBADDRESS (SAD) see Table 5
DATA see Table 6
P STOP condition

C-bus format to write (slave receives data)

W A SUBADDRESS A DATA A P

2000 Dec 11 14

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.

Table 5 Subaddress definition (second byte after slave address)

FUNCTION

Volume right 00000000
Volume left 00000001
Control 1 00000010
Control 2 00000011

Note

1. Significant subaddress bits.

Table 6 Data definition (third byte after slave address)

FUNCTION

Volume right 0 B6 B5 B4 B3 B2 B1 B0
Volume left 0 C6 C5 C4 C3 C2 C1 C0
Control 1 0 E6 E5 E4 E3 E2 E1 E0
Control 2 0 0 0 F4 F3 F2 F1 F0

MSB LSB

D7 D6 D5 D4 D3 D2 D1

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

(1)

D0

(1)

Table 7 Bit functions of Table 6

BITS SYMBOL FUNCTION

B0 to B6 VR0 to VR6 volume control right
C0 to C6 VL0 to VL6 volume control left
E0 STEREO mode selection for line out
E1 GMU mute control for OUTL and OUTR
E2 AVLON AVL on/off
E3 CCD increased AVL decay current on/off
E4 and E5 AT1 and AT2 attack time at AVL
E6 LMU line out mute on/off
F0 and F1 TONE selection between four fixed tone controls
F2 MODE selection between intern and extern
F3 MONO forced mono on/off at OUTL and OUTR
F4 LITO linear tone control on/off

2000 Dec 11 15

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

Table 8 Volume setting

FUNCTION

Gv(dB)

121111011
111111010
101111001

91111000
81110111
71110110
61110101
51110100
41110011
31110010
21110001
11110000
01101111

−11101110

−21101101

−31101100

−41101011

−51101010

−61101001

−71101000

−81100111

−91100110

−101100101

−111100100

−121100011

−131100010

−141100001

−151100000

−161011111

−171011110

−181011101

−191011100

−201011011

−211011010

−221011001

−231011000

−241010111

−251010110

V6 V5 V4 V3 V2 V1 V0

DATA

2000 Dec 11 16

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

FUNCTION

G

(dB)

v

−261010101

−271010100

−281010011

−291010010

−301010001

−311010000

−321001111

−331001110

−341001101

−351001100

−361001011

−371001010

−381001001

−391001000

−401000111

−411000110

−421000101

−431000100

−441000011

−451000010

−461000001

−471000000

−480111111

−490111110

−500111101

−510111100

−520111011

−530111010

−540111001

−550111000

−560110111

−570110110

−580110101

−590110100

−600110011

−610110010

−620110001

−630110000

Mute 0 101111

V6 V5 V4 V3 V2 V1 V0

DATA

2000 Dec 11 17

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

Table 9 Mode setting

FUNCTION MODE

LOL LOR

Left right logic 1 (stereo

Mono mono logic 1 (stereo

Mono mono logic 0 (no

Mono mono logic 0 (no

Table 10 Mute setting

FUNCTION DATA

MUTE CONTROL FOR

OUTR AND OUTL

Forced mute at OUTR and OUTL 1
No forced mute at OUTR and OUTL 0

Table 11 AVLON bit setting

FUNCTION DATA

Automatic volume control on 1
Automatic volume control off 0

Table 12 CCD bit setting

FUNCTION DATA

AVL CURRENT E3

Increased load current 1
Load current for normal AVL decay time 0

Table 13 AVL attack time; seeChapter “Characteristics”

note 5

FUNCTION DATA

R

(Ω)E5E4

att

420 0 0

730 0 1
1200 1 0
2100 1 1

READABLE BIT

D0/STP

received)

received)

stereo received)

stereo received)

AVL E2

SETTING BIT

E0/STEREO

E1

1

0

1

0

TDA9853H

Table 14 Line out mute setting

FUNCTION DATA

MUTE LINE OUTPUT E6

Line output mute 1
Line output active 0

Table 15 Tone setting

FUNCTION DATA

TONE F1 F0

Maximum bass and
maximum treble

Maximum bass and
minimum treble

Minimum bass and
maximum treble

Minimum bass and
minimum treble

Table 16 Selector setting

FUNCTION DATA

MODE INTERNAL/EXTERNAL F2

External left and right 1
Internal left and right 0

Table 17 Mono setting

FUNCTION DATA

MONO AT OUTL AND OUTR F3

Forced mono 1
No forced mono 0

Table 18 Linear setting

FUNCTION DATA

MODE TONE F4

Linear 1
Tone 0

11

10

01

00

2000 Dec 11 18

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

INTERNAL PIN CONFIGURATIONS

+

2

8.5kΩ12

Fig.4 Pin 2: CP2.

kΩ

MHB792

TDA9853H

3

+

3.5 kΩ

MHB793

Fig.5 Pin 3: CP1.

4

+

25 kΩ

25 kΩ

25 kΩ

50 pF

100 pF

Fig.6 Pin 4: COMP.

1 kΩ

MHB794

+

Fig.7 Pin 5: CMO; pin 6: CSS.

+

5, 6

10 kΩ 10 kΩ

4 V

8, 26

MHB795

+

MHB796

7

Fig.8 Pin 7: RFR.

2000 Dec 11 19

20 kΩ

MHB797

Fig.9 Pin 8: LIL; pin 26: LIR.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

9, 25

+

4 V

MHB798

4 V

30 kΩ

4 V

TDA9853H

10, 24

+

MHB799

Fig.10 Pin 9: LOL; pin 25: LOR.

11, 23

+

80 Ω

4 V

MHB800

Fig.11 Pin 10: VIL; pin 24: VIR.

13, 14

4 V

20, 21

+

5.4 kΩ

12 kΩ

+

MHB801

Fig.12 Pin 11: VAL; pin 23: VAR.

2000 Dec 11 20

Fig.13 Pin 13: TC1L; pin 14: TC2L; pin 20: TC2R;

pin 21: TC1R.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

15, 19

4 V

+

28.5 kΩ

9.5 kΩ

4 V

MHB802

Fig.14 Pin 15: BCL; pin 19: BCR.

27

TDA9853H

16, 18+

80 Ω

MHB803

Fig.15 Pin 16: OUTL; pin 18: OUTR.

+

28

3.4
kΩ

3.4
kΩ

Fig.16 Pin 27: V

+

4.7 kΩ
300 Ω

5 kΩ

MHB804

.

ref

29

MHB805

Fig.17 Pin 28: V

.

CAP

30

+

MHB806

MHB807

Fig.18 Pin 29: CAV.

2000 Dec 11 21

Fig.19 Pin 30: TW.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

31

+

6 kΩ

MHB808

Fig.20 Pin 31: CW.

TDA9853H

+

Fig.21 Pin 32: BPU; pin 35: FDI.

35

+

16 kΩ

MHB809

32

33

+

MHB810

Fig.22 Pin 33: FDO.

39

+

MHB812

1.8 kΩ

38

1.8 kΩ

MHB811

Fig.23 Pin 38: SDA.

40

5 V

1.8 kΩ

MHB813

Fig.24 Pin 39: MAD (I2C-bus address switch).

2000 Dec 11 22

Fig.25 Pin 40: SCL.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

41

+

MHB814

Fig.26 Pin 41: VCC.

42

+

10 kΩ 10 kΩ

Fig.27 Pin 42: CPH.

TDA9853H

4 V

MHB815

43

+

3 kΩ

Fig.28 Pin 43: CER.

MHB816

2000 Dec 11 23

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm

c

y

X

33 23

34

Z

22

E

A

TDA9853H

SOT205-1

e

w M

b

p

B

v M

scale

(1)

eH

H

19.2

1

18.2

e

pin 1 index

2.3

2.1

b

0.25

12

11

Z

w M

p

D

H

D

0.50

0.25

0.35

0.14

D

0 5 10 mm

(1) (1)(1)

D

14.1

14.1

13.9

13.9

44

1

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.60

0.25

0.05

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

v M

D

E

A

B

E

19.2

18.2

H

E

LL

2.0

1.2

A

p

A

2

A

1

detail X

Z

D

0.152.35 0.10.3

2.4

1.8

(A )

3

L

p

L

Zywv θ

E

o

2.4

7

o

1.8

0

θ

OUTLINE
VERSION

SOT205-1

IEC JEDEC EIAJ

133E01

REFERENCES

2000 Dec 11 24

EUROPEAN

PROJECTION

ISSUE DATE

97-08-01
99-12-27

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder and audio processor

SOLDERING
Introduction to soldering surface mount packages

Thistext gives a verybriefinsightto a complextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for
certainsurfacemount ICs, but itisnotsuitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardbyscreen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

TDA9853H

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on foursides,thefootprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering,the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

If wave soldering is used the following conditions must be
observed for optimal results:

2000 Dec 11 25

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP andTSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

SOLDERING METHOD

WAVE REFLOW

(2)

(3)(4)
(5)

suitable

suitable
suitable

(1)

.

2000 Dec 11 26

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9853H

decoder and audio processor

DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification Thisdata sheet contains preliminary data, and supplementary data will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or at anyotherconditions above those giveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warranty that such applicationswillbe
suitable for the specified use without further testing or
modification.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expectedto result inpersonal injury. Philips
Semiconductorscustomersusing or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of theseproducts,conveysno licence or title
under any patent, copyright, or mask work right to these
products,and makes no representationsor warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

(1)

2

PURCHASE OF PHILIPS I

2000 Dec 11 27

C COMPONENTS

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C components conveys a license under the Philips’ I2C patent to use the

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PTPhilips Development Corporation, SemiconductorsDivision,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

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04547-130 SÃO PAULO, SP, Brazil,
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Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

70

Printed in The Netherlands 753504/01/pp28 Date of release: 2000 Dec 11 Document order number: 9397 750 07474