Datasheet TDA9852H, TDA9852 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA9852

2

I

C-bus controlled BTSC
stereo/SAP decoder and audio
processor

Preliminary specification
Supersedes data of 1996 Feb 28
File under Integrated Circuits, IC02

1997 Mar 11

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

FEATURES

• Quasi alignment-free application due to automatic
adjustment of channel separation via I2C-bus

• High integration level with automatically tuned
integrated filters

• Input level adjustment I2C-bus controlled

• Alignment-free SAP processing

• dbx noise reduction circuit

• Power supply

• I2C-bus transceiver.

Stereo decoder

• Stereo pilot PLL circuit with ceramic resonator,
automatic adjustment procedure for stereo channel
separation, two pilot thresholds selectable via I

Audio processor

2

C-bus.

TDA9852

GENERAL DESCRIPTION

The TDA9852 is a bipolar-integrated BTSC stereo
decoder with hi-fi audio processor (I
application in TV sets, VCRs and multimedia.

2

C-bus controlled) for

• Selector for internal and external signals (line in)

• Automatic volume level control
(control range +6 to −15 dB)

• Interface for external noise reduction circuits

• Volume control (control range +16 to −71 dB)

• Special loudness characteristic automatically controlled

in combination with volume setting (control range 28 dB)

• Audio signal zero crossing detection between any
volume step switching

• Mute control at audio signal zero crossing

2

• Mute control via I

ORDERING INFORMATION

TYPE

NUMBER

TDA9852 SDIP42 plastic shrink dual in-line package; 42 leads (600 mil) SOT270-1
TDA9852H QFP44

C-bus.

PACKAGE

NAME DESCRIPTION VERSION

plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm

SOT307-2

1997 Mar 11 2

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

LICENSE INFORMATION

A license is required for the use of this product. For further information, please contact

COMPANY BRANCH ADDRESS

THAT Corporation Licensing Operations 734 Forest St.

Marlborough, MA 01752
USA
Tel.: [phone]
Fax: [phone]

Tokyo Office 405 Palm House, 1-20-2 Honmachi

Shibuya-ku, Tokyo 151
Japan
Tel.: [phone]
Fax: [phone]

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

V

comp(rms)

V

oR,L(rms)

G

LA

α

cs

THD
V

I, O(rms)

AVL control range −15 − +6 dB
G

C

L

B

S/N signal-to-noise ratio line out (mono); V

S/N signal-to-noise ratio audio section; V

supply voltage 8.0 8.5 9.0 V
supply current − 75 95 mA
input signal voltage (RMS value) 100% modulation L + R; fi= 300 Hz − 250 − mV
output signal voltage (RMS value) 100% modulation L + R; fi= 300 Hz − 500 − mV
input level adjustment control −3.5 − +4.0 dB
stereo channel separation fL= 300 Hz; fR= 3 kHz 25 35 − dB
total harmonic distortion L + R fi= 1 kHz − 0.2 − %

L,R

signal handling (RMS value) THD < 0.5% 2 −−V

volume control range −71 − +16 dB
maximum loudness boost fi=40Hz − 17 − dB

= 0.5 V (RMS)

o

CCIR noise weighting filter

− 60 − dB

(peak value)
DIN noise weighting filter

− 73 − dBA

(RMS value)

= 2 V (RMS);

o

gain = 0 dB

CCIR noise weighting filter

− 94 − dB

(peak value)
DIN noise weighting filter

− 107 − dBA

(RMS value)

1997 Mar 11 3

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

BLOCK DIAGRAM

OUTR

42

(38)

OUT

RIGHT

C12

R3

R2

C11

C9

C8C28

C7

(EIR)

External Input Right

C20

C16

Q1

CERAMIC

C5

C4

C3

41

40

VIR

39

C10

38

37

5

35

C6

34

36

LIR

33

LOR

32

31

30

RESONATOR

MURATA

CSB503F58

29

28

27

R1

C2

26

(37)

(36)

RIGHT

VOLUME

LOUDNESS

(35)
(34)

(33)

TDA9852

(44)

(31)

(30)

(32)

(29)

(28)

(27)

(26)

(25)

(24)

(23)

STEREO DECODER

(22)

CONTROL

ZERO

CROSSING

EFFECTS

AUTOMATIC

VOLUME AND

LEVEL CONTROL

INPUT

SELECT

+

SELECT

LINEOUT

DEMATRIX

SAP

SWITCH

STEREO/

INPUT

LEVEL

ADJUST

24

(20)

C1

COMP

OUTL

1

(40)

OUT

LEFT

LEFT

VOLUME

CONTROL

LOUDNESS

C

2

I

LOGIC

TRANSCEIVER

SUPPLY

ADJUST

STEREO

DBX

SAP

DEMODULATOR

(41)

(42)

(43)
(18)

(17)

(1)

(21)
(19)
(3)

(4)

(2)

(5)
(6)

(7)
(8)

(9)
(11)

(10)

(12)

(13)

(14)

2

3

4

22

21

(15) (16) (39)
20

6

25
23
8

9

7

10
11

12
13

14
16

15

17

18

19

MHA309

n.c.

C14

VIL

LIL

LOL

R6

C29

C26

SDA SCL

C27

R7

C19

C18C17

R5

R4

C30

C34

C15

C49

C47

C25

C24
C23

C22

C21

AGND DGND

CC

V

(EIL)

External Input Left

TDA9852

handbook, full pagewidth

Fig.1 Block diagram.

The numbers given in parenthesis refer to the TDA9852H version.

1997 Mar 11 4

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

Component list

Electrolytic capacitors ±20%; foil or ceramic capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.

COMPONENTS VALUE TYPE REMARK

C1 10 µF electrolytic 63 V
C2 470 nF foil
C3 4.7 µF electrolytic 63 V
C4 220 nF foil
C5 10 µF electrolytic 63 V; I
C6 2.2 µF electrolytic 16 V
C7 2.2 µF electrolytic 63 V
C8 15 nF foil ±5%

C9 15 nF foil ±5%
C10 2.2 µF electrolytic 16 V
C11 8.2 nF foil or ceramic ±5% SMD 2220/1206
C12 150 nF foil ±5%
C14 150 nF foil ±5%
C15 100 µF electrolytic 16 V
C16 4.7 µF electrolytic 63 V
C17 4.7 µF electrolytic 63 V
C18 100 nF foil
C19 10 µF electrolytic 63 V
C20 4.7 µF electrolytic 63 V
C21 47 nF foil ±5%
C22 1 µF electrolytic 63 V
C23 1 µF electrolytic 63 V
C24 10 µF electrolytic 63 V ±10%
C25 10 µF electrolytic 63 V ±10%
C26 2.2 µF electrolytic 16 V
C27 2.2 µF electrolytic 63 V
C28 4.7 µF electrolytic 63 V ±10%
C29 2.2 µF electrolytic 16 V
C30 8.2 nF foil or ceramic ±5% SMD 2220/1206
C34 100 µF electrolytic 16 V
C47 220 µF electrolytic 25 V
C49 100 nF foil or ceramic SMD 1206

R1 2.2 kΩ−

R2 20 kΩ−

R3 2.2 kΩ−

R4 20 kΩ−

R5 2.2 kΩ−

R6 8.2 kΩ− ±2%

leak

< 1.5 µA

1997 Mar 11 5

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

COMPONENTS VALUE TYPE REMARK

R7 160Ω− ±2%

Q1 CSB503F58 radial leads

CSB503JF958 alternative as SMD

PINNING

SYMBOL

SDIP42 QFP44

OUTL 1 40 output, left channel
LDL 2 41 input loudness, left channel
VIL 3 42 input volume, left channel
EOL 4 43 output effects, left channel
C

AV

V

ref

5 44 automatic volume control capacitor

6 1 reference voltage 0.5V
LIL 7 2 input line control, left channel
AVL 8 3 input automatic volume control, left channel
SOL 9 4 output selector, left channel
LOL 10 5 output line control, left channel
C

TW

C

TS

C

W

C

S

11 6 capacitor timing wideband for dbx
12 7 capacitor timing spectral for dbx
13 8 capacitor wideband for dbx

14 9 capacitor spectral for dbx
VEO 15 10 variable emphasis output for dbx
VEI 16 11 variable emphasis input for dbx
C

NR

C

M

C

DEC

17 12 capacitor noise reduction for dbx

18 13 capacitor mute for SAP

19 14 capacitor DC-decoupling for SAP
GND 20 − ground
AGND − 15 analog ground
DGND − 16 digital ground
SDA 21 17 serial data input/output (I
SCL 22 18 serial clock input (I
V

CC

23 19 supply voltage
COMP 24 20 composite input signal
V
C
C
C
C

CAP

P1
P2
PH
ADJ

25 21 capacitor for electronic filtering of supply

26 22 capacitor for pilot detector

27 23 capacitor for pilot detector

28 24 capacitor for phase detector

29 25 capacitor for filter adjustment
CER 30 26 ceramic resonator
C

MO

31 27 capacitor DC-decoupling mono

PINS

DESCRIPTION

CC

2

C-bus)

2

C-bus)

TDA9852

1997 Mar 11 6

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL

SDIP42 QFP44

C

SS

32 28 capacitor DC-decoupling stereo/SAP
LOR 33 29 output line control, right channel
SOR 34 30 output selector, right channel
AVR 35 31 input automatic volume control, right channel
LIR 36 32 input line control, right channel
C

PS2

C

PS1

37 33 capacitor 2 pseudo function

38 34 capacitor 1 pseudo function
EOR 39 35 output effects, right channel
VIR 40 36 input volume, right channel
LDR 41 37 input loudness, right channel
OUTR 42 38 output, right channel
n.c. − 39 not connected

PINS

DESCRIPTION

handbook, full pagewidth

V

AVL

SOL

LOL

C

C

C

VEO

VEI

ref

LIL

TW

TS

C

CAVEOL
44

1
2
3
4
5
6
7
8

W

9

S

10
11

12

NR

C

VIL

LDL

OUTL

n.c.

OUTR

LDR

VIR

43

42

41

40

39

38

37

36

TDA9852H

13

14

15

16

17

18

19

20

M

C

DEC

C

AGND

DGND

SDA

SCL

CC

V

COMP

EOR

35

21

CAP

V

PS1

C

34

22

P1

C

33
32
31
30
29
28
27
26
25
24
23

MHA696

C

PS2

LIR
AVR
SOR
LOR
C

SS

C

MO

CER
C

ADJ

C

PH

C

P2

Fig.2 Pin configuration (QFP-version).

1997 Mar 11 7

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

handbook, halfpage

OUTL

LDL

EOL
C

V

AVL

SOL

LOL

C

C

C

VEO

VEI

C

C

DEC

GND

SDA

VIL

AV

ref

LIL

TW

TS

C

NR
C

1
2
3
4
5
6
7
8

9
10
11

TDA9852

12
13

W

14

S

15
16
17
18

M

19
20

MHA310

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2221

OUTR
LDR
VIR
EOR
C

PS1

C

PS2

LIR
AVR
SOR
LOR
C

SS

C

MO

CER
C

ADJ

C

PH

C

P2

C

P1

V

CAP

COMP
V

CC

SCL

TDA9852

FUNCTIONAL DESCRIPTION
Stereo decoder

NPUT LEVEL ADJUSTMENT

I
The composite input signal is fed to the input level

adjustment stage. The control range is from

−3.5 to +4.0 dB in steps of 0.5 dB. The subaddress
control 3 of Tables 5 and 6 and the level adjust setting of
Table 21 allows an optimum signal adjustment during the
set alignment. The maximum input signal voltage is
2 V (RMS).

TEREO DECODER

S
The output signal of the level adjustment stage is coupled

to a low-pass filter which suppresses the baseband noise
above 125 kHz. The composite signal is then fed into a
pilot detector/pilot cancellation circuit and into the MPX
demodulator. The main L + R signal passes a 75 µs fixed
de-emphasis filter and is fed into the dematrix circuit.
The decoded sub-signal L − R is sent to the stereo/SAP
switch. To generate the pilot signal the stereo demodulator
uses a PLL circuit including a ceramic resonator.
The stereo channel separation is adjusted by an automatic
procedure to be performed during set production. For a
detailed description see Section “Adjustment procedure”.
The stereo identification can be read by the I2C-bus
(see Table 2). Two different pilot thresholds
(data STS = 1; STS = 0) can be selected via the I2C-bus
(see Table 19).

DEMODULATOR

SAP
The composite signal is fed from the output of the input

level adjustment stage to the SAP demodulator circuit
through a 5fH (fH= horizontal frequency) band-pass filter.
The demodulator level is automatically controlled.
The SAP demodulator includes internal noise and field
strength detectors that mute the SAP output in the event of
insufficient signal conditions. The SAP identification signal
can be read by the I2C-bus (see Table 2).

Fig.3 Pin configuration (SDIP-version).

1997 Mar 11 8

WITCH

S
The stereo/SAP switch feeds either the L − R signal or the

SAP demodulator output signal via the internal dbx noise
reduction circuit to the dematrix/switching circuit. Table 12
shows the different switch modes provided at the output
pins LOR and LOL.

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

dbx DECODER
The circuit includes all blocks required for the noise

reduction system in accordance with the BTSC system
specification. The output signal is fed through a 73 µs fixed
de-emphasis circuit to the dematrix block.

I

NTEGRATED FILTERS

The filter functions necessary for stereo and SAP
demodulation and part of the dbx filter circuits are provided
on-chip using transconductor circuits. The required filter
accuracy is attained by an automatic filter alignment
circuit.

Audio processor

ELECTOR

S
The selector allows selecting either the internal line out

signals LOR or LOL (dematrix output) or the external line
in signals LIR and LIL and combines the left and right
signals in several modes (see Tables 5 and 6 for
subaddress and Table 11 for data). The input signal
capability of the line inputs (LIR/LIL) is 2 V (RMS).
The output of the selector is AC-coupled to the automatic
volume level control circuit via pins SOR/SOL and
AVR/AVL to avoid offset voltages.

UTOMATIC VOLUME LEVEL CONTROL

A
The automatic volume level stage controls its output

voltage to a constant level of typically 200 mV (RMS) from
an input voltage range of 0.1 to 1.1 V (RMS). The circuit
adjusts variations in modulation during broadcasting and
due to changes in the programme material. The function
can be switched off. To avoid audible ‘plops’ during the
permanent operation of the AVL circuit a soft blending
scheme has been applied between the different gain
stages. A capacitor (4.7 µF) at pin CAV determines the
attack and decay time constants. In addition the ratio of
attack and decay time can be changed via I2C-bus
(see Table 15). At power on, the discharged 4.7 µF
capacitor at CAV must be loaded by the internal decay
current. If AVL is chosen, this would result in an attenuated
AVL gain for about 10 seconds after poweron. This can be
speeded up by choosing via I2C-bus an increased charge
current (about 10 times higher) for about the first
2 seconds after power on (see Table 6, CCD bit in
control 1 and Table 18).

TDA9852

E

FFECTS

The audio processor section offers the following mode
selections: linear stereo, pseudo stereo, spatial stereo and
forced mono.The spatial mode provides an antiphase
crosstalk of 30% or 52% (switchable via I2C-bus;
see Table 10).

V

OLUME/LOUDNESS

The volume control range is from +16 dB to −71 dB in
steps of 1 dB and ends with a mute step (see Table 8).
Balance control is achieved by the independent volume
control of each channel. The volume control blocks
operate in combination with the loudness control. The filter
is linear when maximum gain for volume control is
selected. The filter characteristic changes automatically
over a range of 28 dB down to a setting of −12 dB.
At −12 dB volume control the maximum loudness boost is
obtained. The filter characteristic is determined by external
components. The proposed application provides a
maximum boost of 17 dB for bass and 4.5 dB for treble.
The loudness may be switched on or off via I2C-bus
control (see Table 9). The left and right volume control
stages include two independent zero crossing detectors.
A change in volume is automatically activated but not
executed. The execution is enabled at the next zero
crossing of the signal. If a new volume step is activated
before the previous one has been processed, the previous
value will be executed first, and then the new value will be
activated. If no zero crossing occurs the next volume
transmission will enforce the last activated volume setting.

The zero crossing is realized between adjoining steps and
between any steps, but not from any step to mute. In this
case the GMU bit is needed to use. In case only one
channel has to be muted, two steps are necessary.
The first step is a transmission of any step to −71 dB and
the second step is the−71 dB step to mute mode. The step
of −71 dB to mute mode has no zero crossing but this is
not relevant.

1997 Mar 11 9

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

MUTE
The mute function can be activated independently with last

step of volume control at the left or right output. By setting
the general mute bit GMU via the I2C-bus all outputs are
muted. All channels include an independent zero cross
detector. The zero crossing mute feature can be selected
via bit TZCM:

TZCM = 0: forced mute with direct execution
TZCM = 1: execution in time with signal zero crossing.

In the zero cross mode a change in the GMU polarity is
activated but not executed. The execution is enabled at
the next zero crossing of the signal. To avoid a large delay
of mute switching, when very low frequencies are
processed, or the output signal amplitude is lower than the
DC offset voltage, the following I
needed:

a first transmission for mute execution
a second transmission about 100 ms later, which must

switch the zero crossing mode to forced mute
(TZCM = 0)

a third transmission to reactivate the zero crossing
mode (TZCM = 1). This transmission can take place
immediately, but must follow before the next mute
execution.

Adjustment procedure

COMPOSITE INPUT LEVEL ADJUSTMENT
Feed in from FM demodulator the composite signal with

100% modulation (25 kHz deviation) L + R; fi= 300 Hz.
Set input level control via I2C-bus monitoring line out
(500 mV ±20 mV). Store the setting in a non-volatile
memory.

UTOMATIC ADJUSTMENT PROCEDURE

A

2

C-bus transmissions are

TDA9852

• Effects, AVL, loudness off.

• Line out setting bits: STEREO = 1, SAP = 0

(see Table 12)

• Selector setting SC0, SC1, SC2 = 0, 0, 0 (see Table 11)

• Start adjustment by transmission ADJ = 1 in register

ALI3; the decoder will align itself

• After 1 second minimum stop alignment by transmitting
ADJ = 0 in register ALI3 read the alignment data by an

2

I

C-bus read operation from ALR1 and ALR2
(see Chapter “I2C-bus protocol”) and store it in a
non-volatile memory; the alignment procedure
overwrites the previous data stored in ALI1 and ALI2

• Disconnect the capacitors of external inputs from
ground.

M

ANUAL ADJUSTMENT

Manual adjustment is necessary when no dual tone
generator is available (e.g. for service).

• Spectral and wideband data have to be set to 10000
(middle position for adjustment range)

• Composite input L = 300 Hz; 14% modulation

• Adjust channel separation by varying wideband data

• Composite input L = 3 kHz; 14% modulation

• Adjust channel separation by varying spectral data

• Iterative spectral/wideband operation for optimum

adjustment

• Store data in non-volatile memory.

IMING CURRENT FOR RELEASE RATE

T
Due to possible internal and external spreading, the timing

current can be adjusted via I2C-bus, see Table 20, as
recommended by dbx.

• Capacitors of external inputs LIL and LIR must be
grounded at EIL and EIR

• Composite input signal L = 300 Hz, R = 3.1 kHz,
14% modulation for each channel; volume gain +16 dB
via I2C-bus

1997 Mar 11 10

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

Requirements for the composite input signal to ensure correct system performance

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

COMP

L+R(rms)

composite input level for 100%
modulation L + R; 25 kHz
deviation; fi= 300 Hz;
RMS value

∆COMP composite input level

spreading under operating
conditions

Z

o

f

lf

f

hf

THD

L,R

output impedance note 1 − low-ohmic 5 kΩ
low frequency roll-off 25 kHz deviation L + R; −2dB −− 5Hz
high frequency roll-off 25 kHz deviation L + R; −2 dB 100 −−kHz
total harmonic distortion L + R fi= 1 kHz; 25 kHz deviation −− 0.5 %

S/N signal-to-noise ratio

L + R/noise

α

SB

side band suppression mono
into unmodulated SAP carrier;
SAP carrier/side band

α

SP

spectral spurious attenuation
L + R/spurious

measured at COMP 162 250 363 mV

= −20 to +70 °C; aging;

T

amb

−0.5 − +0.5 dB

power supply influence

= 1 kHz; 125 kHz deviation;

f

i

−− 1.5 %

note 2
CCIR 468-2 weighted quasi

peak; L + R; 25 kHz deviation;

= 1 kHz; 75 µs de-emphasis

f

i

critical picture modulation;

44 −−dB

note 3
with sync only 54 −−dB

mono signal: 25 kHz deviation,

46 −−dB
fi= 1 kHz; side band: SAP
carrier frequency ±1 kHz

50 Hz to 100 kHz;
mainly n × fH; no de-emphasis;
L + R; 25 kHz deviation,
f = 1 kHz as reference

n = 1, 5 35 −−dB
n = 4, 6 40 −−dB
n = 2, 3 26 −−dB

Notes

1. Low-ohmic preferred, otherwise the signal loss and spreading at COMP, caused by Z

and the composite input

o

impedance (see Chapter “Characteristics”, Section “Input level adjustment control”) must be taken into account.

2. In order to prevent clipping at over-modulation
(maximum deviation in the BTSC system for 100% modulation is 73 kHz).

3. For example colour bar or flat field white; 100% video modulation.

1997 Mar 11 11

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

CC

V

n

T

amb

T

stg

V

es

Note

1. Human body model: C = 100 pF; R = 1.5 kΩ; V = 2 kV; Charge device model: C = 200 pF; R = 0 Ω; V = 300 V.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

supply voltage 0 9.5 V
voltage of all other pins to pin V

CC

0VCCV
operating ambient temperature −20 +70 °C
storage temperature −65 +150 °C
electrostatic handling; note 1

thermal resistance from junction to ambient in free air

SOT270-1 43 K/W
SOT307-2 60 K/W

1997 Mar 11 12

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

CHARACTERISTICS

All voltages are measured relative to GND; VCC= 8.5 V; Rs= 600 Ω; RL=10kΩ; CL= 2.5 nF; AC-coupled; fi= 1 kHz;
T

=25°C; gain control Gv= 0 dB; balance in mid position; loudness off; see Fig.1; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

General

V

CC

I

CC

V

ref

Input level adjustment control

G

LA

G

step

V

i(rms)

Z

i

Stereo decoder

MPX

L+R(rms)

MPX

L−R

MPX

(max)

MPX

pilot(rms)

ST

on(rms)

ST

off(rms)

Hys hysteresis − 2.5 − dB
OUT

L+R

α

cs

supply voltage 8.0 8.5 9.0 V
supply current − 75 95 mA
internal reference voltage at

pin V

ref

− 4.25 − V

input level adjustment control −3.5 − +4.0 dB
step resolution − 0.5 − dB
maximum input voltage level

2 −−V

(RMS value)
input impedance 29.5 35 40.5 kΩ

input voltage level for 100%
modulation L + R; 25 kHz
deviation (RMS value)

input voltage level for 100%

input level adjusted via I2C-bus
(L + R; fi= 300 Hz);
monitoring LINE OUT

− 250 − mV

− 707 − mV

modulation L − R; 50 kHz
deviation (peak value)

maximum headroom for L + R,

f

< 15 kHz; THD < 15% 9 −−dB

mod

L, R
nominal stereo pilot voltage

− 50 − mV

level (RMS value)
pilot threshold voltage stereo

on (RMS value)
pilot threshold voltage stereo

off (RMS value)

output voltage level for 100%
modulation L + R at LINE OUT

data STS = 1 −− 35 mV
data STS = 0 −− 30 mV
data STS = 1 15 −−mV
data STS = 0 10 −−mV

input level adjusted via I2C-bus

480 500 520 mV
(L + R; fi= 300 Hz);
monitoring LINE OUT

stereo channel separation L/R
at LINE OUT

aligned with dual tone 14%
modulation for each channel;
see Section “Adjustment
procedure” in Chapter
“Functional description”

= 300 Hz; fR= 3 kHz 25 35 − dB

f

L

= 300 Hz; fR= 8 kHz 20 30 − dB

f

L

= 300 Hz; fR= 10 kHz 15 25 − dB

f

L

1997 Mar 11 13

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

L, R

THD

L,R

S/N signal-to-noise ratio mono mode; CCIR 468-2

Stereo decoder, oscillator (VCXO); note 1
f

o

f

of

∆f

H

L, R frequency response 14% modulation;

f

= 300 Hz L or R

ref

=50Hzto10kHz −3 −−dB

f

i

= 12 kHz −−3 −dB

f

i

total harmonic distortion L, R
at LINE OUT

modulation L or R
1% to 100%; fi= 1 kHz

weighted; quasi peak;
500 mV output signal

nominal VCXO output
frequency (32fH)

spread of free-running
frequency

with nominal ceramic
resonator

with nominal ceramic
resonator

capture range frequency
(nominal pilot)

− 0.2 1.0 %

50 60 − dB

− 503.5 − kHz

500.0 − 507.0 kHz

±190 ±265 − Hz

SAP demodulator; note 2
SAP

i(rms)

nominal SAP carrier input
voltage level (RMS value)

SAP

on(rms)

threshold voltage SAP on
(RMS value)

SAP

off(rms)

threshold voltage SAP off

(RMS value)
SAP
SAP

hys
LEV

hysteresis − 2 − dB

SAP output voltage level at

LINE OUT

f

res

frequency response 14% modulation;

THD total harmonic distortion f

15 kHz frequency deviation of

− 150 − mV

intercarrier

−− 85 mV

35 −−mV

mode selector in position
SAP/SAP; f

= 300 Hz;

mod

− 500 − mV

100% modulation

−3 −−dB

50 Hz to 8 kHz; f

= 1 kHz − 0.5 2.0 %

i

= 300 Hz

ref

1997 Mar 11 14

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LINE OUT at pins LOL and LOR

V

o(rms)

HEAD

o

Z

o

V

O

R

L

C

L

α

ct

∆V

ST-SAP

nominal output voltage

(RMS value)

output headroom 9 −−dB

output impedance − 80 120 Ω

DC output voltage 0.45VCC0.5V

output load resistance 5 −−kΩ

output load capacitance −− 2.5 nF

crosstalk L, R into SAP 100% modulation; fi= 1 kHz;

crosstalk SAP into L, R 100% modulation; f

output voltage difference if

switched from L, R to SAP

100% modulation − 500 − mV

CC

0.55VCCV

50 75 − dB
L or R; mode selector switched
to SAP/SAP

= 1 kHz;

i

50 70 − dB
SAP; mode selector switched
to stereo

250 Hz to 6.3 kHz −− 3dB

dbx noise reduction circuit

t

adj

I

s

stereo adjustment time see Section “Adjustment

nominal timing current for
nominal release rate of
spectral RMS detector

∆I

s

I

s range

I

t

spread of timing current −15 − +15 %
timing current range 7 steps via I2C-bus −±30 − %
timing current for release rate

of wideband RMS detector

Rel

rate

nominal RMS detector
release rate

−− 1s
procedure” in Chapter
“Functional description”

Is can be measured at pin C

− 24 −µA

TS

via current meter connected to

1

⁄2VCC+1V

−

1

⁄3I

s

−µA

nominal timing current and
external capacitor values

wideband − 125 − dB/s
spectral − 381 − dB/s

1997 Mar 11 15

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Circuit section from pins LIL and LIR to pins OUTL and OUTR; note 3

B roll-off frequencies C

THD total harmonic distortion V

RR ripple rejection V

α

ct

crosstalk between bus inputs
and signal outputs

V

no

α

cs

noise output voltage CCIR 468-2 weighted; quasi

channel separation Vi=1V; fi= 1 kHz 75 −−dB

Effect controls

α
α

spat1
spat2

anti-phase crosstalk by spatial
effect

ϕ phase shift by pseudo-stereo see Fig.4 −− −−

, C7, C10, C26, C27 and

6

C29= 2.2 µF; Zi = Z

i(min)

low frequency (−3 dB) −− 20 Hz
high frequency (−0.5 dB) 20 −−kHz

= 1000 mV; Gv= 0 dB;

i

− 0.2 0.5 %
AVL on

V

= 2000 mV; Gv= 0 dB;

i

− 0.2 0.5 %
AVL on

V

= 1000 mV; Gv= 0 dB;

i

− 0.02 − %
AVL off

= 2000 mV; Gv= 0 dB;

V

i

− 0.02 − %
AVL off

< 200 mV; fi= 100 Hz 47 50 − dB

r(rms)

notes 4 and 5 − 110 − dB

− 40 80 µV
peak; AVL off; loudness off;
Gv=0dB

measured in dBA; AVL off;
loudness off; G

=1V; fi= 12.5 kHz 75 −−dB

V

i

=0dB

v

− 8 −µV

− 52 − %

− 30 − %

1997 Mar 11 16

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Automatic volume level control (AVL)

Z

i

V

i(rms)

G

v

G

step

V

iop(rms)

V

o(rms)

V

DC OFF

R

att

I

dec

input impedance 8.8 11.0 13.2 kΩ
maximum input voltage

THD < 0.2% 2 tbf − V

(RMS value)
gain, maximum boost 5 6 7 dB
maximum attenuation 14 15 16 dB
equivalent step width between

− 1.5 − dB

the input stages
(soft switching system)

input level at maximum boost

− 0.1 − V

(RMS value)
input level at maximum

− 1.125 − V

attenuation (RMS value)
output level in AVL operation

see Fig.5 160 200 250 mV

(RMS value)
DC offset between different

gain steps

voltage at pin C

6.50 to 6.33 V or

AV

−− 6mV

6.33 to 6.11 V or

6.11 to 5.33 V or

5.33 to 2.60 V; note 6

discharge resistors for attack
time constant

AT1 = 0; AT2 = 0; note 7 340 420 520 Ω
AT1 = 1; AT2 = 0; note 7 590 730 910 Ω
AT1 = 0; AT2 = 1; note 7 0.96 1.2 1.5 kΩ
AT1 = 1; AT2 = 1; note 7 1.7 2.1 2.6 kΩ

charge current for decay time normal mode; CCD = 0; note 8 1.6 2.0 2.4 µA

power-on speed-up; CCD = 1;

− tbf −µA
note 8

Selector from pins LOL, LOR, LIL and LIR to pins SOL and SOR

Z

α

V

i

s

i(rms)

input impedance 16 20 24 kΩ
input isolation of one selected

source to the other input
maximum input voltage

Vi=1V; fi= 1 kHz 86 96 − dB
V

=1V; fi= 12.5 kHz 80 96 − dB

i

THD < 0.5% 2 2.3 − V

(RMS value)

V

DC OFF

DC offset voltage at selector
output by selection of any
inputs

Z

o

R

L

C

L

G

v

output impedance − 80 120 Ω
output load resistance 5 −−kΩ
output load capacitance 0 − 2.5 nF
voltage gain, selector − 0 − dB

1997 Mar 11 17

−− 25 mV

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Audio control part; input pins VIL and VIR to pins OUTX and OUTS

Z

i

Z

o

R

L

C

L

V

i(rms)

V

no

G

c

G

step

∆G

a

∆G

L

α

m

V

DC OFF

Loudness control part

L

B

L

G

Muting at power supply drop for OUTR and OUTS

V

CC-DROP

Power-on reset; note 9
V

RESET(STA)

V

RESET(END)

volume input impedance 8.0 10.0 12.0 kΩ
output impedance − 80 120 Ω
output load resistance 5 −−kΩ
output load capacitance 0 − 2.5 nF
maximum input voltage

THD < 0.5% 2.0 2.15 − V

(RMS value)
noise output voltage CCIR 468-2 weighted;

quasi peak

=16dB − 110 220 µV

G

v

=0dB − 33 50 µV

G

v

mute position − 10 −µV

total continuous control range maximum boost − 16 − dB

maximum attenuation − 71 − dB

step resolution − 1 − dB
step error between adjoining

−− 0.5 dB

step
attenuator set error Gv= +16 to −50 dB −− 2dB

=−51 to −71 dB −− 3dB

G

v

gain tracking error Gv= +16 to −50 dB −− 2dB
mute attenuation 80 −−dB
DC step offset between any

adjacent step
DC step offset between any

step to mute

Gv= +16 to 0 dB − 0.2 10.0 mV

=0to−71 dB −− 5mV

G

v

= +16 to +1 dB − 215mV

G

v

=0to−71 dB − 110mV

G

v

maximum loudness boost loudness on; referred to

loudness off; boost is
determined by external
components; see Fig.6

=40Hz − 17 − dB

f

i

= 10 kHz − 4.5 − dB

f

i

loudness control range −12 − +16

supply drop for mute active − V

− 0.7 − V

CAP

start of reset voltage increasing supply voltage −− 2.5 V

decreasing supply voltage 4.2 5 5.8 V

end of reset voltage increasing supply voltage 5.2 6 6.8 V

1997 Mar 11 18

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2

Digital part (I

V

IH

V

IL

I

IH

I

IL

V

OL

Notes to the characteristics

1. The oscillator is designed to operate together with MURAT A resonator CSB503F58. Change of the resonator supplier
is possible, but the resonator specification must be close to CSB503F58.

2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain.

3. Frequency range 20 Hz to 20 kHz; select in to input line control; effects: linear stereo.

4. Crosstalk:

5. The transmission contains:
a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics
b) Clock frequency = 50 kHz
c) Repetition burst rate = 400 Hz
d) Maximum bus signal amplitude = 5 V (p-p).

6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.

7. Attack time constant = CAV× R

Decay time

8.
Example: C

9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I
is in the reset position.

10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz.
Information about the I2C-bus can be found in the brochure
(order number 9398 393 40011).

C-bus pins); note 10

HIGH level input voltage 3 − V

CC

V
LOW level input voltage −0.3 − +1.5 V
HIGH level input current −10 − +10 µA
LOW level input current −10 − +10 µA
LOW level output voltage IIL=3mA −− +0.4 V

V

20 log

bus(p-p)

-------------------- ­V

o(rms)

.

att

G1–



----------



C

0.76 V× 10

AV

=

-------------------------------------------------------------------------------

= 4.7 µF; I

AV

dec

20




I

dec

=2µA; G1= −9 dB; G2=+6dB→ decay time results in 4.14 s.

G2–

---------­20

10

–

2

C-bus receiver

“The I2C-bus and how to use it”

1997 Mar 11 19

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

I2C-BUS PROTOCOL

2

C-bus format to read (slave transmits data)

I

S SLAVE ADDRESS R/

2

Table 1 Explanation of I

S START condition; generated by the master
Standard SLAVE ADDRESS (MAD) 101 101 1

W 1 (read); generated by the master

R/
A acknowledge; generated by the slave
DATA slave transmits an 8-bit data word
MA acknowledge; generated by the master
P STOP condition; generated by the master

Table 2 Definition of the transmitted bytes after read condition

FUNCTION BYTE

Alignment read 1 ALR1 Y SAPP STP A14 A13 A12 A11 A10
Alignment read 2 ALR2 Y SAPP STP A24 A23 A22 A21 A20

C-bus format to read (slave transmits data)

NAME DESCRIPTION

W A DATA MA DATA P

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

Table 3 Function of the bits in Table 2

BITS FUNCTION

STP stereo pilot identification (stereo received = 1)
SAPP SAP pilot identification (SAP received = 1)
A1X to A2X stereo alignment read data
A1X for wideband expander
A2X for spectral expander
Y indefinite

The master generates an acknowledge when it has received the first data word ALR1, then the slave transmits the next
data word ALR2. Afterwards the master generates an acknowledge, then the slave begins transmitting the first data word
ALR1 etc. until the master generates no acknowledge and transmits a STOP condition.

1997 Mar 11 20

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

I2C-bus format to write (slave receives data)

S SLAVE ADDRESS R/

Table 4 Explanation of I

S START condition
Standard SLAVE ADDRESS (MAD) 101 101 1

W 0 (write)

R/
A acknowledge; generated by the slave
SUBADDRESS (SAD) see Table 5
DATA see Table 6
P STOP condition

If more than 1 byte of DATA is transmitted, then auto-increment is performed, starting from the transmitted subaddress
and auto-increment of subaddress in accordance with the order of Table 5 is performed.

Table 5 Subaddress second byte after MAD

2

C-bus format to write (slave receives data)

NAME DESCRIPTION

W A SUBADDRESS A DATA A P

FUNCTION REGISTER

Volume right VR 0 0 0 0 0 0 0 0
Volume left VL 0 0 0 0 0 0 0 1
Control 1 (note 1) CON1 0 0 0 0 0 1 0 1
Control 2 CON2 0 0 0 0 0 1 1 0
Control 3 CON3 0 0 0 0 0 1 1 1
Alignment 1 ALI1 0 0 0 0 1 0 0 0
Alignment 2 ALI2 0 0 0 0 1 0 0 1
Alignment 3 ALI3 0 0 0 0 1 0 1 0

Note

1. In auto-increment mode it is necessary to insert 3 dummy data words between volume left and control 1.

Table 6 Definition of third byte, third byte after MAD and SAD

FUNCTION REGISTER

Volume right VR 0 VR6 VR5 VR4 VR3 VR2 VR1 VR0
Volume left VL 0 VL6 VL5 VL4 VL3 VL2 VL1 VL0
Control 1 CON1 GMU AVLON LOFF CCD 0 SC2 SC1 SC0
Control 2 CON2 SAP STEREO TZCM 1 LMU EF2 EF1 EF0
Control 3 CON3 0 0 0 0 L3 L2 L1 L0
Alignment 1 ALI1 0 0 0 A14 A13 A12 A11 A10
Alignment 2 ALI2 STS 0 0 A24 A23 A22 A21 A20
Alignment 3 ALI3 ADJ AT1 AT2 0 1 TC2 TC1 TC0

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

1997 Mar 11 21

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

Table 7 Function of the bits in Table 6

BITS FUNCTION

VR0 to VR6 volume control right
VL0 to VL6 volume control left
GMU mute control for all outputs (generate mute)
AVLON AVL on/off
CCD increased AVL decay current on/off
LOFF switch loudness on/off
SC0 to SC2 selection between line in and line out
STEREO, SAP mode selection for line out
TZCM zero cross mode in mute operation (right and left output stage)
LMU mute control for line out
EF0 to EF2 selection between mono, stereo linear, spatial stereo and pseudo mode
L0 to L3 input level adjustment
ADJ stereo adjustment on/off
A1X to A2X stereo alignment data
A1X for wideband expander
A2X for spectral expander
AT1 and AT2 attack time at AVL
TC0 to TC2 timing current alignment data
STS stereo level switch

Table 8 Volume setting

FUNCTION

(dB)

G

v

161111111
151111110
141111101
131111100
121111011
111111010
101111001

91111000
81110111
71110110
61110101
51110100
41110011
31110010
21110001
11110000

V6 V5 V4 V3 V2 V1 V0

DATA

1997 Mar 11 22

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

FUNCTION

(dB)

G

v

01101111

−11101110

−21101101

−31101100

−41101011

−51101010

−61101001

−71101000

−81100111

−91100110

−101100101

−111100100

−121100011

−131100010

−141100001

−151100000

−161011111

−171011110

−181011101

−191011100

−201011011

−211011010

−221011001

−231011000

−241010111

−251010110

−261010101

−271010100

−281010011

−291010010

−301010001

−311010000

−321001111

−331001110

−341001101

−351001100

−361001011

−371001010

−381001001

V6 V5 V4 V3 V2 V1 V0

DATA

1997 Mar 11 23

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

FUNCTION

(dB)

G

v

−391001000

−401000111

−411000110

−421000101

−431000100

−441000011

−451000010

−461000001

−471000000

−480111111

−490111110

−500111101

−510111100

−520111011

−530111010

−540111001

−550111000

−560110111

−570110110

−580110101

−590110100

−600110011

−610110010

−620110001

−630110000

−640101111

−650101110

−660101101

−670101100

−680101011

−690101010

−700101001

−710101000

Mute 0 1 00111

V6 V5 V4 V3 V2 V1 V0

DATA

1997 Mar 11 24

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

Table 9 Loudness setting

CHARACTERISTIC DATA LOFF

With loudness 0
Linear 1

Table 10 Effects setting

FUNCTION

Stereo linear on 000
Pseudo on 001
Spatial stereo;

30% anti-phase crosstalk
Spatial stereo;

50% anti-phase crosstalk
Forced mono 1 1 1

EF2 EF1 EF0

010

011

DATA

TDA9852

Table 11 Selector setting

FUNCTION

Inputs LOR and LOL 0 0 0
Inputs LOR and LOR 0 0 1
Inputs LOL and LOL 0 1 0
Inputs LOL and LOR 0 1 1
Inputs LIR and LIL 1 0 0
Inputs LIR and LIR 1 0 1
Inputs LIL and LIL 1 1 0
Inputs LIL and LIR 1 1 1

Note

1. Input connected to outputs SOR and SOL.

(1)

SC2 SC1 SC0

DATA

Table 12 Switch setting at line out

LINE OUT SIGNALS AT DATA

LOL LOR STEREO SAP

SAP SAP SAP received 1 1
Mute mute no SAP received 1 1
Left right STEREO received 1 0
Mono mono no STEREO received 1 0
Mono SAP SAP received 0 1
Mono mute no SAP received 0 1
Mono mono independent 0 0

Table 13 Zero cross detection setting

Direct mute control 0
Mute control delayed until the next zero crossing 1

Table 14 Mute setting

FUNCTION

Forced mute at OUTR, OUTL and OUTS 1 forced mute at LOR and LOL 1
Audio processor controlled outputs 0 stereo processor controlled outputs 0

INTERNAL SWITCH, READABLE BITS: STP, SAPP

TRANSMISSION STATUS

FUNCTION DATA TZCM

DATA

GMU

FUNCTION

SETTING BITS

DATA

LMU

1997 Mar 11 25

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

Table 15 AVL attack time

FUNCTION

= 420 Ω 00

R

att

= 730 Ω 10

R

att

= 1200 Ω 01

R

att

= 2100 Ω 11

R

att

Table 16 ADJ bit setting

FUNCTION DATA

Stereo decoder operation mode 0
Auto adjustment of channel separation 1

Table 17 AVLON bit setting

FUNCTION DATA

Automatic volume control off 0
Automatic volume control on 1

Table 18 CCD bit setting

DATA

AT1 AT2

TDA9852

Table 21 Level adjust setting

G

L

(dB)

L3 L2 L1 L0

+4.0 1111
+3.5 1110
+3.0 1101
+2.5 1100
+2.0 1011
+1.5 1010
+1.0 1001
+0.5 1000

0.0 0111

−0.5 0110

−1.0 0101

−1.5 0100

−2.0 0011

−2.5 0010

−3.0 0001

−3.5 0000

DATA

FUNCTION DATA

Load current for normal AVL decay time 0
Increased load current 1

Table 19 STS bit setting (pilot threshold stereo on)

FUNCTION DATA

≤ 35 mV 1

ST

on

ST

≤ 30 mV 0

on

Table 20 Timing current setting

FUNCTION

RANGE

I

S

TC2 TC1 TC0

DATA

+30% 1 0 0
+20% 1 0 1
+10% 1 1 0
Nominal 0 1 1

−10% 0 1 0

−20% 0 0 1

−30% 0 0 0

1997 Mar 11 26

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

Table 22 Alignment data for expander in read register ALR1 and ALR2 and in write register ALI1 and ALI2

DATA

FUNCTION

Gain increase 11111

Nominal gain 10000

Gain decrease 01110

D4

AX4

11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001

01111

01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000

D3

AX3

D2

AX2

D1

AX1

D0

AX0

1997 Mar 11 27

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

phase

(degree)

−100

−200

−300

−400

0

(1)

(2)

(3)

2

10

10

handbook, full pagewidth

TDA9852

MHA311

3

10

4

10

f (Hz)

5

10

(1) see Table 23.
(2) see Table 23.
(3) see Table 23.

Fig.4 Pseudo (phase in degrees) as a function of frequency (left output).

Table 23 Explanation of curves in Fig.4

CURVE

CAPACITANCE AT PIN C

(nF)

1 15 15 normal
2 5.6 47 intensified
3 5.6 68 more intensified

PS1

CAPACITANCE AT PIN C

(nF)

PS2

EFFECT

1997 Mar 11 28

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

300

handbook, full pagewidth

V

o(rms)
(mV)

(1) V
(2) V
(3) V

250

200

160

100

10

CAV
o max(rms)
o min(rms)

−2

AVL measured at pin EOL/EOR.
Y1 axis output level in AVL operation with typically 200 mV.
Y2 axis V

DC voltage at pin CAV corresponds with typical gain steps in range of +6 to −15 dB.

CAV

10

Fig.5 Automatic level control diagram.

(1)

(2)

(3)

−1

TDA9852

MHA312

7

V

CAV
(V)

6

5

4

3

2

1

1

V

I(rms)

(V)

10

25

handbook, full pagewidth

(dB)

15

dB (VQX 0)

V

5

−5

−15

−25

−35

10 10

2

10

3

f (Hz)

Fig.6 Volume control with loudness (including low roll-off frequency).

MHA313

16
14

9
4

−1

−6

−11

parameter: volume gain setting (dB)

−16

−21

−26

−31

−36

4

10

1997 Mar 11 29

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

INTERNAL PIN CONFIGURATIONS

+

Fig.7 Pins OUTL, SOL, SOR and OUTR.

+

10.58 kΩ

1 4.25 V

80 Ω

MHA314

3 4.25 V

4.8 kΩ

2 4.25 V

1.33 kΩ

Fig.8 Pins LDL and LDR.

+

4 4.25 V

TDA9852

+

MHA315

Fig.9 Pins VIL and VIR.

5

+

MHA318

MHA316

15
kΩ

Fig.10 Pins EOL and EOR.

6

+

3.4
kΩ

3.4
kΩ

6.8
kΩ

MHA317

MHA319

Fig.11 Pin CAV.

1997 Mar 11 30

Fig.12 Pin V

ref

.

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

7 4.25 V

+

20 kΩ 20 kΩ

Fig.13 Pins LIL and LIR.

10

+

4.25 V

MHA320

8

4.25 V

+

1.75 kΩ

MHA321

Fig.14 Pins AVL and AVR.

11

TDA9852

1

2

3

8

5 kΩ

MHA322

Fig.15 Pins LOL and LOR.

4.25 V

13

+

6

kΩ

MHA324

+

MHA323

Fig.16 Pins CTW and CTS.

15

+

MHA325

Fig.17 Pins CW and CS.

1997 Mar 11 31

Fig.18 Pin VEO.

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

16

+

600 Ω

MHA326

Fig.19 Pin VEI.

+

18

TDA9852

4.25 V

17

+

10

kΩ

Fig.20 Pin CNR.

19 4.25 V

MHA327

MHA328

Fig.21 Pin CM.

5 V

21

1.8 kΩ

MHA330

+

20 kΩ 20 kΩ

Fig.22 Pin C

22 5 V

1.8 kΩ

MHA331

DEC

MHA329

.

Fig.23 Pin SDA.

1997 Mar 11 32

Fig.24 Pin SCL.

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

23

apply +8.5 V to this pin

+

MHA332

Fig.25 Pin VCC.

TDA9852

24 4.25 V

+

30

kΩ

Fig.26 Pin COMP.

MHA333

+

+

25

4.7
kΩ

300 Ω

5 kΩ

Fig.27 Pin V

27 4.25 V

8.5
kΩ

CAP

12
kΩ

.

MHA334

MHA336

26 4.25 V

+

3.5
kΩ

MHA335

Fig.28 Pin CP1.

28 4.25 V

+

Fig.29 Pin CP2.

1997 Mar 11 33

10 kΩ 10 kΩ

Fig.30 Pin CPH.

MHA337

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

+

29

Fig.31 Pin C

ADJ

MHA338

.

TDA9852

30

+

3

kΩ

Fig.32 Pin CER.

MHA339

31 4.25 V

+

10 kΩ 10 kΩ

MHA340

Fig.33 Pins CMO and CSS.

38

+

15

kΩ

Fig.34 Pins C

PS1

and C

MHA341

PS2

.

1997 Mar 11 34

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

PACKAGE OUTLINES

SDIP42: plastic shrink dual in-line package; 42 leads (600 mil)

D

seating plane

L

Z

e

TDA9852

SOT270-1

M

E

A

2

A

A

1

w M

b

1

c

(e )

M

1

H

42

pin 1 index

1

DIMENSIONS (mm are the original dimensions)

A

A

A

UNIT b

max.

mm

5.08 0.51 4.0

12

min.

max.

b

1.3

0.8

0.53

0.40

b

22

E

21

0 5 10 mm

scale

cEe M

1

0.32

0.23

(1) (1)

D

38.9

38.4

14.0

13.7

1

L

M

E

3.2

15.80

2.9

15.24

17.15

15.90

e

w

H

0.181.778 15.24

Z

max.

1.73

(1)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

SOT270-1

IEC JEDEC EIAJ

REFERENCES

1997 Mar 11 35

EUROPEAN

PROJECTION

ISSUE DATE

90-02-13
95-02-04

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

22

Z

E

TDA9852

SOT307-2

e

w M

b

p

pin 1 index

44

1

w M

b

0.25

p

D

H

0.40

0.20

D

D

0.25

10.1

0.14

9.9

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

12

11

Z

D

B

v M

0 2.5 5 mm

scale

(1)

(1) (1)(1)

eH

H

10.1

9.9

12.9

0.8 1.3

12.3

D

v M

H

E

E

A

B

LLpQZywv θ

E

12.9

12.3

0.95

0.55

A

2

A

A

1

detail X

0.85

0.75

0.15 0.10.15

Q

(A )

3

θ

L

p

L

Z

E

D

1.2

0.8

1.2

0.8

o

10

o

0

OUTLINE
VERSION

SOT307-2

IEC JEDEC EIAJ

REFERENCES

1997 Mar 11 36

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-02-04

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

SDIP

OLDERING BY DIPPING OR BY WA VE

S
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

R
Apply a low voltage soldering iron (less than 24 V) to the

lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

QFP

REFLOW SOLDERING
Reflow soldering techniques are suitable for all QFP

packages.
The choice of heating method may be influenced by larger

plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

(order code 9398 652 90011).

). If the

stg max

“Quality

(order code 9398 510 63011).

TDA9852

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary from
50 to 300 seconds depending on heating method. Typical
reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheat for 45 minutes at 45 °C.

WAVE SOLDERING
Wave soldering is not recommended for QFP packages.

This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured. Maximum permissible solder
temperature is 260 °C, and maximum duration of package
immersion in solder is 10 seconds, if cooled to less than
150 °C within 6 seconds. Typical dwell time is 4 seconds
at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Mar 11 37

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP

TDA9852

decoder and audio processor

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1997 Mar 11 38

Philips Semiconductors Preliminary specification

I2C-bus controlled BTSC stereo/SAP
decoder and audio processor

NOTES

TDA9852

1997 Mar 11 39

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]/xxx
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180,

Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547047/1200/02/pp40 Date of release: 1997 Mar 11 Document order number: 9397 750 01766