Datasheet TDA9851T, TDA9851 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA9851

2

I

C-bus controlled economic BTSC

stereo decoder

Product specification
File under Integrated Circuits, IC02

1997 Nov 12

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9851

decoder

FEATURES

• Voltage Controlled Amplifier (VCA) noise reduction
circuit

• Stereo or mono selectable at the AF outputs

• Stereo pilot PLL circuit with ceramic resonator

• Automatic pilot cancellation

• Automatic Volume Level (AVL) control (+6 to −15 dB)

• I2C-bus transceiver.

GENERAL DESCRIPTION

The TDA9851 is a bipolar-integrated BTSC stereo
decoder for application in TV sets, VCRs and multimedia
PCs.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

I

CC

V

o(rms)

α

csL,R

THD

S/N signal-to-noise ratio mono mode; referenced to 500 mV

supply voltage 8 9 9.5 V
supply current − 30 40 mA
output voltage (RMS value) composite input voltage

− 500 − mV
250 mV (RMS) for
100% modulation L + R
(25 kHz deviation); f

stereo channel separation
L and R

total harmonic distortion L and R 100% modulation L or R;

L,R

14% modulation; fL= 300 Hz;

= 3 kHz

f

R

f

= 1 kHz

mod

mod

= 300 Hz

− 20 − dB

− 0.2 1.0 %

output signal

CCIR 468-2 weighted;

50 60 − dB

quasi peak
DIN noise weighting filter

− 73 − dBA

(RMS value)

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA9851 SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1
TDA9851T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1997 Nov 12 2

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

BLOCK DIAGRAM

OUTL

OUTR

12

13

n.c.

AV

1611

C

LEVEL

VOLUME

AUTOMATIC

C7

SDA

24

C-BUS

2

I

AND

FILTER

SCL

1

23

TRANSCEIVER

10

REFERENCE

DGND

FR

R

TDA9851

MHA969

R4

ook, full pagewidth

C3

C6

C5

Q1

C4

C2

R1

SS

C

MO

C

89

4

CER

PH

3

C

P2

6

C

P1

5

C

AND

DEMATRIX

MODE SELECT

L + R

STEREO DECODER

7COMP

C1

TDA9851

L − R

21FDI

SUPPLY

AND

VOLTAGE

DETECTOR

20FDO

R2

14

21522

AMPLIFIER

CONTROLLED

19 18 17

R3

ref

AGND V

CAP

V

TW

W

BPU C

C9

C15

C14

C10 C11 C13

V

CC

Fig.1 Block diagram.

composite

baseband

input

1997 Nov 12 3

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

Component list

Electrolytic capacitors ±20%; foil capacitors ±10%; resistors ±5%; unless otherwise specified; see Fig.1.

COMPONENT VALUE TYPE REMARK

C1 2.2 µF electrolytic 63 V
C2 220 nF foil

C3 2.2 µF electrolytic 63 V
C4 220 nF foil
C5 2.2 µF electrolytic 63 V
C6 2.2 µF electrolytic 63 V
C7 4.7 µF electrolytic 63 V ±10%
C9 22 nF foil
C10 4.7 nF foil
C11 1 µF electrolytic 63 V
C13 10 µF electrolytic 63 V
C14 100 µF electrolytic 16 V
C15 100 µF electrolytic 16 V
R1 3.3 kΩ
R2 15 kΩ
R3 1.3 kΩ
R4 100 kΩ
Q1 CSB503F58 radial leads

CSB503JF958 alternative as SMD

TDA9851

1997 Nov 12 4

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

PINNING

SYMBOL PIN DESCRIPTION

2

SCL 1 serial clock input (I
V

CC

C

PH

2 supply voltage

3 capacitor for phase detector
CER 4 ceramic resonator
C

P1

C

P2

5 capacitor for pilot detector

6 capacitor for pilot detector
COMP 7 composite input signal
C

MO

C

SS

R

FR

8 capacitor DC-decoupling mono

9 capacitor DC-decoupling stereo

10 resistor for filter reference
n.c. 11 not connected
OUTL 12 output, left channel
OUTR 13 output, right channel
V
V

C

ref
CAP

AV

14 reference voltage 0.5V

capacitor for electronic filtering of

15

supply

16 automatic volume control capacitor
TW 17 capacitor timing
C

W

BPU

capacitor for VCA and band-pass filter

18

lower corner frequency
band-pass filter upper corner

19

frequency
FDO 20 fixed de-emphasis output
FDI 21 fixed de-emphasis input
AGND 22 analog ground
DGND 23 digital ground
SDA 24 serial data input/output (I

C-bus)

CC

2

C-bus)

handbook, halfpage

SCL

1

V

2

CC

C

3

PH

CER

4

C

5

P1

C

6

P2

COMP

C

MO

C

SS

R

FR

n.c.

OUTL

7
8

9
10
11
12

TDA9851

MHA968

Fig.2 Pin configuration.

TDA9851

SDA

24

DGND

23

AGND

22

FDI

21

FDO

20
19

BPU
C

18

W

TW

17

C

16

AV

V

15

CAP

V

14

ref

OUTR

13

1997 Nov 12 5

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

FUNCTIONAL DESCRIPTION
Stereo decoder

The composite signal is fed into a pilot detector/pilot
cancellation circuit and into the MPX demodulator.
The main L + R signal passes a 75 µs fixed de-emphasis
filter and is fed into the dematrix circuit. The decoded
sub-signal L − R is sent to the VCA circuit. To generate the
pilot signal the stereo demodulator uses a PLL circuit
including a ceramic resonator.

Mode selection

The L − R signal is fed via the internal VCA circuit to the
dematrix/switching circuit. Mode selection is achieved via

2

C-bus.

the I

Automatic volume level control

The automatic volume level stage controls its output
voltage to a constant level of typically 200 mV (RMS) from

TDA9851

an input voltage range between 0.1 to 1.1 V (RMS).
The circuit adjusts variations in modulation during
broadcasting and because of changes in the programme
material. The function can be switched off. To avoid
audible plops during the permanent operation of the AVL
circuit a soft blending scheme has been applied between
the different gain stages. A capacitor (4.7 µF) at pin C
determines the attack and decay time constants.
In addition the ratio of attack and decay times can be
changed via the I2C-bus.

Integrated filters

The filter functions necessary for stereo demodulation are
provided on-chip using transconductor circuits. The filter
frequencies are controlled by the filter reference circuit via
the external resistor R4.

AV

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

, V

SDA

SCL

V

n

T

amb

T

stg

V

es

supply voltage 0 9.9 V
voltage of SDA and SCL to GND VCC<9V 0 V

≥ 9V09V

V

CC

voltage of all other pins to GND 0 V

CC

CC

operating ambient temperature Tj< 125 °C −20 +70 °C
storage temperature −65 +150 °C
electrostatic handling note 1 −−V

Note

1. Machine model class B.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air

TDA9851 (SOT234-1; SDIP24) 55 K/W
TDA9851T (SOT137-1; SO24) 90 K/W

V

V

1997 Nov 12 6

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9851

decoder

CHARACTERISTICS

All voltages are measured relative to GND; VCC=9V; Rs= 600 Ω; AC-coupled; RL=10kΩ; CL= 2.5 nF; f
mono signal; composite input voltage 250 mV (RMS) for 100% modulation L + R (25 kHz deviation); T

amb

see Fig.1; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CC

I

CC

supply voltage 8 9 9.5 V
supply current − 30 40 mA

Input stage

V

i(max)(rms)

maximum input voltage

2 −−V

(RMS value)

Z

i

input impedance 20 25 30 kΩ

Stereo decoder

HR headroom for L + R, L and R f
V

pil(rms)

nominal stereo pilot voltage

= 300 Hz; THD < 15% 9 −−dB

mod

− 50 − mV

(RMS value)

V

th(on)(rms)

pilot threshold voltage

−− 35 mV

stereo on (RMS value)

V

th(off)(rms)

pilot threshold voltage

15 −−mV

stereo off (RMS value)
hys hysteresis − 2.5 − dB
V

o(rms)

α

csL,R

THD

L,R

output voltage (RMS value) 100% modulation L + R;

f

= 300 Hz

mod

stereo channel separation

L and R

total harmonic distortion

L and R

14% modulation; fL= 300 Hz;
fR= 3 kHz

100% modulation L or R;
f

= 1 kHz

mod

− 500 − mV

− 20 − dB

− 0.2 1.0 %

S/N signal-to-noise ratio mono mode; referenced to

500 mV output signal

CCIR 468-2 weighted;

50 60 − dB

quasi peak
DIN noise weighting filter

− 73 − dBA

(RMS value)

= 1 kHz

mod

=25°C;

Stereo decoder, oscillator (VCXO); note 1
f

∆f

∆f

o

fr

cr

nominal VCXO output

frequency (32fH)

spread of free-running

frequency

with nominal ceramic
resonator

with nominal ceramic
resonator

capture range frequency nominal pilot ±190 ±265 − Hz

1997 Nov 12 7

− 503.5 − kHz

500.0 − 507.0 kHz

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9851

decoder

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Outputs OUTL and OUTR

Z

o

V

O

R

L

C

L

α

ct

VCA

I

s

Rel

rate

output impedance − 80 120 Ω

DC output voltage 0.45VCC0.5V

output load resistance

5 −−kΩ

CC

0.55VCCV

(AC-coupled)

output load capacitance −− 2.5 nF

crosstalk SAP into L and R 100% modulation;

f

= 1 kHz; SAP;

mod

50 70 − dB

mode selector switched to
stereo

nominal timing current for

nominal release rate of VCA

detector

nominal detector release rate nominal timing current and

Is can be measured at pin TW
via current meter connected to

0.5VCC+1V

6.5 8 9.5 µA

− 125 − dB/s

external capacitor values

Automatic volume level control

G

v

G

step

voltage gain maximum boost; note 2 5 6 7 dB

equivalent step width between

the input stages (soft switching

system)
V

iop(rms)

V

o(rms)

input voltage (RMS value) maximum boost; note 2 − 0.1 − V

output voltage in AVL

operation (RMS value)
V

offset(DC)

DC offset voltage between

different gain steps

R

att

discharge resistors for attack

time constant

I

dec

charge current for decay time normal mode; CCD = 0; note 5 1.6 2.0 2.4 µA

maximum attenuation; note 2 14 15 16 dB

− 1.5 − dB

maximum attenuation; note 2 − 1.125 − V

160 200 250 mV

voltage at pin C

AV

−− 20 mV

7.0 to 6.83 V or

6.83 to 6.61 V or

6.61 to 5.83 V or

5.83 to 3.1 V; note 3
AT1 = 0; AT2 = 0; note 4 340 420 520 Ω
AT1 = 1; AT2 = 0; note 4 590 730 910 Ω
AT1 = 0; AT2 = 1; note 4 0.96 1.2 1.5 kΩ
AT1 = 1; AT2 = 1; note 4 1.7 2.1 2.6 kΩ

power-on speed-up; CCD = 1;

− 30 −µA

note 5

Muting at power supply voltage drop for OUTR and OUTL

∆V

CC

supply voltage drop for mute

active

1997 Nov 12 8

− V

− 0.7 − V

CAP

Philips Semiconductors Product specification



I2C-bus controlled economic BTSC stereo

TDA9851

decoder

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Power-on reset; note 6

V

POR(start)

V

POR(end)

Digital part (I

V

IH

V

IL

I

IH

I

IL

V

OL

Notes to the characteristics

1. The oscillator is designed to operate together with Murata resonator CSB503F58 or CSB503JF958 as SMD. Change
of the resonator supplier is possible, but the resonator specification must be close to the specified ones.

2. The AVL input voltage is internal. It corresponds to the output voltage OUTL and OUTR at AVL off.

3. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.

4. Attack time constant = C

5.

Decay time

Example: C

6. When reset is active the GMU bit (mute) is set and the I

7. The AC characteristics are in accordance with the I2C-bus specification for standard mode (clock frequency
maximum 100 kHz). A higher frequency, up to 280 kHz, can be used if all clock and data times are interpolated
between standard mode (100 kHz) and fast mode (400 kHz) in accordance with the I2C-bus specification.
Information about the I2C-bus can be found in brochure

start of reset voltage increasing supply voltage −− 2.5 V

decreasing supply voltage 4.2 5 5.8 V

end of reset voltage increasing supply voltage 5.2 6 6.8 V

2

C-bus pins); note 7

HIGH-level input voltage 3 − VCC≤ 9V
LOW-level input voltage −0.3 − +1.5 V
HIGH-level input current −10 − +10 µA
LOW-level input current −10 − +10 µA
LOW-level output voltage IIL=3mA −− 0.4 V

× R

CAV

C

=

----------------------------------------------------------------------------------

CAV

0.76 V× 10

CAV

= 4.7 µF; I

dec

.

att

G1–

----------



20



G2–

---------­20

10

–



I

dec

=2µA; G1= −9 dB; G2=+6dB→ decay time results in 4.14 s.

2

C-bus receiver is in the reset position.

“I2C-bus and how to use it”

(order number 9398 393 40011).

1997 Nov 12 9

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9851

decoder

I2C-BUS PROTOCOL

2

C-bus format to read (slave transmits data)

I

S SLAVE ADDRESS R/

Table 1 Explanation of I

S START condition; generated by the master
Standard SLAVE ADDRESS (MAD) 101 101 1
R/

W logic 1 (read); generated by the master
A acknowledge; generated by the slave
DATA slave transmits an 8-bit data word
P STOP condition; generated by the master

Table 2 Definition of the transmitted bytes after read condition

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

YYYYYYYSTP

2

C-bus format to read (slave transmits data)

NAME DESCRIPTION

W A DATA P

Table 3 Function of the bits in Table 2

BITS FUNCTION

STP stereo pilot identification (stereo received = 1)
Y indefinite

2

C-bus format to write (slave receives data)

I

S SLAVE ADDRESS R/

Table 4 Explanation of I

S START condition
Standard SLAVE ADDRESS (MAD) 101 101 1
R/

W logic 0 (write)
A acknowledge; generated by the slave
DATA see Table 5
P STOP condition

Table 5 Definition of the DATA (second byte after MAD)

MSB LSB

2

C-bus format to write (slave receives data)

NAME DESCRIPTION

W A DATA A P

D7 D6 D5 D4 D3 D2 D1 D0

0 0 AT2 AT1 CCD AVLON GMU STEREO

1997 Nov 12 10

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

Table 6 Function of the bits in Table 5

BITS FUNCTION

STEREO mode selection stereo or mono
GMU mute control OUTL and OUTR
AVLON AVL on/off
CCD increased AVL decay current on/off
AT1 and AT2 attack time at AVL

Table 7 Mode setting

FUNCTION MODE

OUTL OUTR

Left right 1 (stereo

Mono mono 1 (stereo

Mono mono 0 (no stereo

Mono mono 0 (no stereo

READABLE BIT

STP

received)

received)

received)

received)

SETTING BIT

STEREO

1

0

1

0

TDA9851

Table 9 AVLON bit setting

FUNCTION DATA

Automatic volume control on 1
Automatic volume control off 0

Table 10 CCD bit setting

FUNCTION DATA

Load current for normal AVL decay time 0
Increased load current 1

Table 11 AVL attack time

R

att

(Ω)

420 0 0

730 1 0
1200 0 1
2100 1 1

DATA

AT1 AT2

Table 8 Mute setting

FUNCTION

Forced mute at OUTR and OUTL 1
No forced mute at OUTR and OUTL 0

DATA

GMU

1997 Nov 12 11

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

INTERNAL PIN CONFIGURATIONS

1

1.8 kΩ

MHA971

Fig.3 Pin 1; SCL.

TDA9851

2

+

MHA972

Fig.4 Pin 2; VCC.

3

+

10 kΩ 10 kΩ

Fig.5 Pin 3; CPH.

5

+

3.5 kΩ

MHA973

MHA975

4

+

3 kΩ

MHA974

Fig.6 Pin 4; CER.

+

6

8.5kΩ12
kΩ

Fig.7 Pin 5; CP1.

1997 Nov 12 12

MHA976

Fig.8 Pin 6; CP2.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

7

+

25 kΩ

25 kΩ

Fig.9 Pin 7; COMP.

25 kΩ

50 pF

100 pF

MHA977

TDA9851

8, 9

+

10 kΩ 10 kΩ

MHA978

Fig.10 Pin 8; CMO and pin 9; CSS.

12, 13+

1 kΩ

+

10

MHA979

Fig.11 Pin 10; RFR.

14

3.4
kΩ

3.4
kΩ

80 Ω

MHA980

Fig.12 Pin 12; OUTL and pin 13; OUTR.

+

15

4.7 kΩ
300 Ω

5 kΩ

MHA981

Fig.13 Pin 14; V

ref

.

1997 Nov 12 13

Fig.14 Pin 15; V

MHA982

CAP.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

16

+

MHA983

Fig.15 Pin 16; CAV.

18

+

Fig.16 Pin 17; TW.

+

21

TDA9851

17

MHA984

+

6 kΩ

Fig.17 Pin 18; CW.

20

MHA985

Fig.18 Pin 19; BPU and pin 21; FDI.

16 kΩ

24

1.8 kΩ

+

19

MHA986

+

MHA987

MHA988

Fig.19 Pin 20; FDO.

1997 Nov 12 14

Fig.20 Pin 24; SDA.

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

APPLICATION INFORMATION

OUTR

ref

V

CAP

V

AV

C

n.c. OUTL

FR

R

SS

C

TDA9851

MHA970

R4

C9

C11 C13 C7 C14 C15

C10

R3

R2

SDA

TW

W

C

SDA DGND AGND FDI FDO BPU

MO

C5 C6

C1

COMP C

input

baseband

C2

C3

SCL

Q1

C4

composite

R1

CC

V

Fig.21 Application circuit.

P2

TDA9851

24 23 22 21 20 19 18 17 16 15 14 13

C

P1

CER C

PH

SCL C

12 3456789101112

handbook, full pagewidth

1997 Nov 12 15

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

PACKAGE OUTLINES

SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)

D

seating plane

L

Z

24

e

b

b

13

TDA9851

SOT234-1

M

E

A

2

A

A

1

w M

1

c

(e )

M

1

H

pin 1 index

1

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE
VERSION

SOT234-1

A

min.

4.7 0.51 3.8

A

12

max.

IEC JEDEC EIAJ

1.3

0.8

b

0.53

0.40

cEe M

1

0.32

0.23

REFERENCES

(1) (1)

D

22.3

21.4

12

9.1

8.7

E

(1)

Z

L

3.2

2.8

EUROPEAN

PROJECTION

M

10.7

10.2

E

12.2

10.5

e

1

w

H

0.181.778 10.16

ISSUE DATE

92-11-17
95-02-04

max.

1.6

1997 Nov 12 16

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

SO24: plastic small outline package; 24 leads; body width 7.5 mm

D

c

y

Z

24

13

TDA9851

SOT137-1

E

H

E

A

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

A

max.

2.65

0.10

A1A2A

0.30

2.45

0.10

2.25

0.012

0.096

0.004

0.089

0.25

0.01

b

3

p

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

15.6

15.2

0.61

0.60

12

w M

b

p

scale

eHELLpQ

7.6

1.27

7.4

0.30

0.050

0.29

10.65

10.00

0.419

0.394

A

1.4

0.055

Q

2

A

1

detail X

1.1

1.1

0.4

0.043

0.016

1.0

0.043

0.039

0.25

0.01

L

p

L

(A )

0.25 0.1

0.01

A

3

θ

ywv θ

Z

0.9

0.4

0.035

0.004

0.016

o

8

o

0

OUTLINE
VERSION

SOT137-1

IEC JEDEC EIAJ

075E05 MS-013AD

REFERENCES

1997 Nov 12 17

EUROPEAN

PROJECTION

ISSUE DATE

95-01-24
97-05-22

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo
decoder

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

SDIP

SOLDERING BY DIPPING OR BY WA VE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

(order code 9398 652 90011).

). If the

stg max

TDA9851

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

AVE SOLDERING

W
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

1997 Nov 12 18

Philips Semiconductors Product specification

I2C-bus controlled economic BTSC stereo

TDA9851

decoder

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C COMPONENTS

2

C components conveys a license under the Philips’ I2C patent to use the

1997 Nov 12 19

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547047/1200/01/pp20 Date of release: 1997 Nov12 Document order number: 9397 750 02702