Datasheet TDA9321H Datasheet (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

TDA9321H

C-bus controlled TV input

processor

Preliminary speciﬁcation Supersedes data of 1998 Dec 16 File under Integrated Circuits, IC02

2000 Sep 25

Page 2

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

FEATURES

• Multistandard Vision IF (VIF) circuit with Phase-Locked Loop (PLL) demodulator

• Sound IF (SIF) amplifier with separate input for single reference Quasi SplitSound (QSS) mode and separate Automatic Gain Control (AGC) circuit

• AM demodulator without extra reference circuit

• Switchable group delay correction circuit which can be

used to compensate the group delay pre-correction of the B/G TV standard in multistandard TV receivers

• Several (I2C-bus controlled) switch outputs which can be used to switch external circuits such as sound traps, etc.

• Flexible source selection circuit with 2 external CVBS inputs, 2 Luminance (Y) and Chrominance (C) (or additional CVBS) inputs and 2 independently switchable outputs

• Comb filter interface with CVBS output and Y/C input

• Integrated chrominance trap circuit

• Integrated luminance delay line with adjustable delay

time

• Integratedchrominance band-pass filter with switchable centre frequency

• Multistandard colour decoder with 4 separate pins for crystal connection and automatic search system

• PALplus helper demodulator

• Possible blanking of the helper signals for PALplus and

EDTV-2

• Internal baseband delay line

• Two linear RGB inputs with fast blanking; the

RGB signals are converted to YUV signals before they are supplied to the outputs; one of the RGB inputs can also be used as YUV input

• Horizontal synchronization circuit with switchable time constant for the PLL and Macrovision/subtitle gating

• Horizontal synchronization pulse output or clamping pulse input/output

• Vertical count-down circuit

• Vertical synchronization pulse output

• Two-level sandcastle pulse output

• I2C-bus control of various functions

• Low dissipation.

TDA9321H

GENERAL DESCRIPTION

The TDA9321H (see Fig.1) is an input processor for ‘High-end’ television receivers. It contains the following functions:

• Multistandard IF amplifier with PLL demodulator

• QSS-IF amplifier and AM sound demodulator

• CVBS and Y/C switch with various inputs and outputs

• Multistandardcolourdecoderwhichcan also decode the

PALplus helper signal

• Integrated baseband delay line (64 µs)

• Sync processor which generates the horizontal and

vertical drive pulses for the feature box (100 Hz applications) or display processor (50 Hz applications).

The supply voltage for the TDA9321H is 8 V.

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA9321H QFP64 plastic quad ﬂat package; 64 leads (lead length 1.95 mm);

PACKAGE

SOT319-2

body 14 × 20 × 2.8 mm

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Supply

supply voltage (pins VP1and VP2) 7.2 8.0 8.8 V supply current (pins VP1and VP2) − 120 − mA

Input signals

i(VIF)(rms)

i(SIF)(rms)

i(CVBS/Y)(p-p)

i(C)(p-p)

i(RGB)(p-p)

VIF ampliﬁer sensitivity (RMS value) − 35 −µV SIF ampliﬁer sensitivity (RMS value) − 100 −µV CVBS or Y input signal (peak-to-peak value) − 1.0 − V chrominance input signal (burst amplitude) (peak-to-peak value) − 0.3 − V RGB input signal (peak-to-peak value) − 0.7 − V

Output signals

o(VIFO)(p-p)

o(CVBSPIP)(p-p)

o(CVBSTXT)(p-p)

o(TAGC)

o(QSS)(rms)

o(AM)(rms)

o(V)(p-p)

o(U)(p-p)

o(Y)(b-w)

o(hor)

o(ver)

o(sc)(p-p)

demodulated CVBS output signal (peak-to-peak value) − 2.5 − V CVBS output signal for Picture-In-Picture (peak-to-peak value) − 1.0 − V CVBS output signal for teletext (peak-to-peak value) − 2.0 − V tuner AGC output current 0 − 5mA QSS output signal (RMS value) − 100 − mV demodulated AM sound output signal (RMS value) − 600 − mV

−Voutput signal (peak-to-peak value) − 1.05 − V

−U output signal (peak-to-peak value) − 1.33 − V

Youtput signal (black-to-white value) − 1.0 − V horizontal pulse output − 5 − V vertical pulse output − 5 − V subcarrier output signal (peak-to-peak value) − 200 − mV

2000 Sep 25 3

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BLOCK DIAGRAM

Philips Semiconductors Preliminary speciﬁcation

C-bus controlled TV input processor

SOUND

TRAP

VIFVCO1

VIFVCO2

TAGC

VIFO

GDI

GDO

CVBS

AV1

CVBS1

AV2

CVBS2

SW0

CVBS/Y3

SW1

CVBS/Y4

VIF1 VIF2

8 62

AFC TOP

12 13

int

15 16 17 18 19 20 21

22 23 24

DEC

VIF

VIF AMPLIFIER

AND PLL

DEMODULATOR

AGC/AFC

VIDEO AMPLIFIER

MUTE

mute

GROUP DELAY

CORRECTION

CVBSPIP

CVBSTXT

SIF1

VIFPLL

SIF AMPLIFIER

QSS MIXER

AM DEMODULATOR

switch control

VIDEO SWITCHES

AND

CONTROL

26 CVBSCF

COMB FILTER

AGC

SIF2 64

25 SYS1

DEC 1

27 SYS2

SIF

Y/CVBS

28 YCF

QSS/AM 5

29 CCF

VP2DEC

SUPPLY

TDA9321H

IDENT

VIDEO

IDENTIFICATION

AUTOMATIC

CHROMINANCE

CONTROL

DETECTOR

9 GND1

Y/C

DIG

31 GND2

DEC 35

44 GND3

subcarrier

GENERATOR

HORIZONTAL

PULSE

VCO AND

PLL

SYNC

SEPARA TOR

CLOCHE

FILTER

BANDPASS

FILTER

REFO

HA/CLP59SCO

PH1LF

VA 61

VERTICAL

DIVIDER

VERTICAL

SYNC

SEPARATOR

SYNC

IN-LOCK

DETECTOR

FILTER

TUNING

hue

PAL/NTSC

PLL

HUE CONTROL

XTALB

XTALA

5756555430

XTALC

XTALD

52 LFBP

SCL47SDA 46

I2C-BUS

TRANSCEIVER

Y-delay

Y-DELA Y

Y-SWITCH

AND TRAPS

SECAM

DECODER

SYSTEM

IDENTIFICATION

helper

SECAM SWITCH

DEMODULATOR

GI1RI138BI139RGB1 37

RGB MATRIX

Y/U/V

SWITCH

BASEBAND DELAY LINE

PAL(NTSC)/

PAL/NTSC

B-YR-Y

MGR473

RI2

GI2

BI2

RGB2

DEC

SEC

TDA9321H

Fig.1 Block diagram.

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

PINNING

SYMBOL PIN DESCRIPTION

DEC

SIF

VIF1 2 VIF input 1 VIF2 3 VIF input 2 DEC

VIF

QSS/AM 5 combined QSS and AM sound output VIFPLL 6 VIF PLL ﬁlter VIFVCO1 7 VIF VCO tuned circuit 1 VIFVCO2 8 VIF VCO tuned circuit 2 GND1 9 main supply ground VIFO 10 VIF output V

GDI 12 group delay correction input GDO 13 group delay correction output CVBS

int

AV1 15 AV input 1 CVBS1 16 CVBS input 1 AV2 17 AV input 2 CVBS2 18 CVBS input 2 SW0 19 switch output bit 0 (I CVBS/Y3 20 CVBS or luminance input 3 C3 21 chrominance input 3 SW1 22 switch output bit 1 (I CVBS/Y4 23 CVBS or luminance input 4 C4 24 chrominance input 4 SYS1 25 system output 1 for comb ﬁlter CVBSCF 26 CVBS output for comb ﬁlter SYS2 27 system output 2 for comb ﬁlter YCF 28 luminance input from comb ﬁlter CCF 29 chrominance input from comb ﬁlter REFO 30 reference output (subcarrier) GND2 31 digital supply ground CVBSPIP 32 CVBS output for Picture-In-Picture

1 SIF AGC decoupling

4 VIF AGC decoupling

11 positive supply 1 (+8 V)

14 internal CVBS input

C-bus)

TDA9321H

SYMBOL PIN DESCRIPTION

DEC

DIG

CVBSTXT 34 CVBS output for teletext DEC

RI1 36 red input 1 GI1 37 green input 1 BI1 38 blue input 1 RGB1 39 RGB insertion input 1 RGB2 40 RGB insertion input 2 RI2 41 red input 2 GI2 42 green input 2 BI2 43 blue input 2 GND3 44 ground 3 V

SCL 46 serial clock input (I SDA 47 serial data input/output (I AS 48 address select input (I YO 49 luminance output UO 50 U-signal output VO 51 V-signal output LFBP 52 loop ﬁlter burst phase detector DEC

SEC

XTALA 54 crystal A (4.433619 MHz) XTALB 55 crystal B (3.582056 MHz) XTALC 56 crystal C (3.575611 MHz) XTALD 57 crystal D (3.579545 MHz) PH1LF 58 phase 1 loop ﬁlter SCO 59 sandcastle pulse output HA/CLP 60 horizontal pulse output or clamp pulse

VA 61 vertical pulse output TAGC 62 tuner AGC output SIF1 63 SIF input 1 SIF2 64 SIF input 2

33 digital supply decoupling

35 band gap decoupling

45 positive supply 2 (+8 V)

C-bus)

53 SECAM PLL decoupling

input/output

C-bus)

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

handbook, full pagewidth

SIF2

SIF1

TAGCVAHA/CLP

DEC

QSS/AM

VIFPLL VIFVCO1 VIFVCO2

CVBS

CVBS1

CVBS2

SIF

VIF1 VIF2

VIF

GND1

VIFO

GDI

GDO

int

AV1

AV2

SW0

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

SCO

PH1LF

TDA9321H

XTALD 57

XTALC 56

XTALB 55

XTALA 54

SEC

DEC

LFBP 52

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

VO UO YO AS SDA SCL V

GND3 BI2 GI2 RI2 RGB2 RGB1 BI1 GI1 RI1 DEC

BG CVBSTXT DEC

DIG

TDA9321H

CVBS/Y3

SW1

SYS1

CVBS/Y4

Fig.2 Pin configuration.

2000 Sep 25 6

SYS2

CVBSCF

YCF

CCF

REFO

GND2

MGR474

CVBSPIP

Page 7

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

FUNCTIONAL DESCRIPTION Vision IF ampliﬁer

The VIF amplifier contains three AC-coupled control stages with a total gain control range higher than 66 dB. The sensitivity of the circuit is comparable with that of modern IF-ICs.

The video signal is demodulated by a PLL carrier regenerator, which contains a frequency detector and a phase detector. During acquisition, the frequency detectortunesthe VCO to thecorrectfrequency.The initial adjustment of theoscillator is realized via theI2C-bus. The switching between SECAM L and L’ can also be realized via the I2C-bus. After lock-in, the phase detector controls the VCO so that a stable phase relationship between the VCO and the input signal is achieved. The VCO operates at twice the IF frequency. The reference signal for the demodulator is obtained by means of a frequency divider circuit. To get good performance for phase modulatedcarriersignals,the control speed of the PLLcan be increased by bit FFI.

TDA9321H

The input of the ident circuit is connected to pin 14 (see Fig.3). This has the advantage that the ident circuit can also be activated when a scrambled signal is received (descrambler connected between the IF video output (pins 10 and 14). A second advantage is that the ident circuit can be usedwhen the VIF amplifieris not used(e.g. with built-in satellite tuners). The video ident circuit can also be used to identify the selected CBVS or Y/C signal. Theswitchingbetween the two modescanberealizedwith bit VIM.

The TDA9321H contains a group delay correction circuit which can be switched between the BG and a flat group delayresponse characteristic. This hastheadvantage that no compromise has to be made in multistandard receivers for the choice of the SAW filter. Both the input and output of the group delay correction circuit are externally available, so that the sound trap can be connected between the IF video output and the group delay correction input. The output signal of the correction circuit can be supplied to the video processing circuit and to the external SCART plug.

The AFC output is obtained by using the VCO control voltage of the PLL and can be read via the I2C-bus. For fast search tuning systems, the window of the AFC can be increased with a factor 3. The setting is realized with bit AFW.

The AGC detector operates on top sync and top white level. The demodulation polarity is switched via the I2C-bus. The AGC detector time constant capacitor is connected externally: mainly because of the flexibility of the application. The time constant of the AGC system during positive modulation is rather long, to avoid visible variationsof the signalamplitude. To improvethe speed of the AGC system, a circuit is included that detects whether the AGC detector is activated every frame period. When no action is detected during three field periods, the speed of the system is increased. For signals without peak white information, the system automatically switches to a gated black level AGC. Because a black level clamp pulse is required for this mode of operation, the circuit only switches to black level AGC in the internal mode.

The circuit contains a video identification (ident) circuit which is independent of the synchronization circuit. Therefore, search tuning is possible when the display section of the receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as the slower sync ident circuit (bit SL) and we recommend the use of both ident outputs to obtain a reliable search system. The ident output is supplied to the tuning system via the I2C-bus.

The IC has several(I2C-bus controlled) outputports which can be used to switch sound traps or other external components.

When the VIF amplifier is not used, the complete VIF amplifier can be switched off with bit IFO via the I2C-bus.

Sound circuit

The SIF amplifier is similar to the VIF amplifier and has a gain control range of approximately 66 dB. The AGC circuit is related to the SIF carrier levels (average level of AM or FM carriers) and ensures a constant signal amplitude of the AM demodulator and the QSS mixer.

The single referenceQSS mixer isrealized by a multiplier. This multiplier converts the SIF signal to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter to attenuate the residual video signals. With this system, a high performance hi-fi stereo sound processing can be achieved.

TheAM sound demodulator isrealized by amultiplier. The modulatedSIF signal is multipliedin phase withthe limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter to attenuate the carrier harmonics.

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

Video switches

The circuit has three CVBS inputs (one internal and two external inputs) and two Y/C inputs. The Y/C inputs can also be used as additional CVBS inputs. The switch configuration is given in Fig.3. The various sources are selected via the I2C-bus.

The circuit can be set in a mode in which it automatically detects whether a CVBS or a Y/C signal is supplied to the Y/C inputs. In this mode, the TV standard is first identified on the added Y/CVBS and the C input signal. Then, both chrominance input signal amplitudes are checked once andthe input signalwith the highestburst signal amplitude is selected. The result of the detection can be read via the I2C-bus.

The IC has two inputs (AV1 and AV2), which can be used to read the status levels of pin 8 of the SCART plug. The information is available in the output status byte 02 in bits D0 to D3.

The three outputs of the video switch (CVBSTXT, CVBSPIP and COMBCVBS) can be independently switched to the various input signals. The names are just arbitrary and it is for instance possible to use the COMBCVBS signal todrive the combfilter and the teletext decoder in parallel and to supply the CVBSTXT signal to the SCART plug (via an emitter follower).

For comb filter interfacing, the circuit has the COMBCVBS output,athird Y/C input, a referencesignaloutput (fsc)and two control pins which switch the comb filter to the standard of the incoming signal (as detected by the ident circuit of the colour decoder). When the comb filter is enabledby bit ECMB andasignal is recognizedwhich can be combed, the Y/C signals coming from the comb filter are automatically selected if the original source is a CVBS signal, indicated via the CMB-bit in output status byte 02 (D5). For signals which cannot be combed (like SECAM or Black-to-White signals) and for Y/C input signals,theY/C signalscoming from the comb filter arenot selected.

Chrominance and luminance processing

The circuits contain a chrominance bandpass, a SECAM cloche filter and a chrominance trap circuit. The filters are realized by means of gyrator circuits and they are automatically calibrated by comparing the tuning frequency with the crystal frequency of the decoder. The luminance delay line is also realized by means of gyrator circuits. The centre frequency of the chrominance bandpass filter is switchable via the I2C-bus so that the performance can be optimized for ‘front-end’ signals and external CVBS signals.

TDA9321H

The luminance output signal which is derived from the incoming CVBS or Y/C signal can be varied in amplitude bymeans of aseparate gain settingcontrol via theI2C-bus control bits GAI1 and GAI0. The gain variation which can be realized with these bits is −1 to +2 dB.

Colour decoder

The colour decoder can decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder contains an alignment-free crystal oscillator with four separate crystal pins, a killer circuit and two colour difference demodulators. The 90° phase shift for the reference signal is made internally.

Because it is possible to connect four different crystals to the colour decoder, all colour standards can be decoded without external switching circuits. Which crystals are connected to the decoder must be indicated via the I2C-bus. The crystal connection pins that are not used must be left open circuit.

The horizontal oscillator is calibrated by means of the crystal frequency of the colour PLL. For a reliable calibration, it is very important that crystal indication bits XA to XD are not corrupted. For this reason, the crystal bits can be read in the output bytes so that the software can check the I2C-bus transmission.

The ICs contain an Automatic Colour Limiting (ACL) circuit, which can be switched via the I2C-bus and which preventsoversaturationoccurringwhensignals with a high chrominance-to-burstratioarereceived. The ACL circuit is designed such that it only reduces the chrominance signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The ACL function is mainly intended for NTSC signals but it can also beused forPAL signals. For SECAM signals, the ACL function should be switched off.

The SECAM decoder contains an auto-calibrating PLL demodulator which has two references: the4.43 MHz sub-carrier frequency (which is obtained from the crystal oscillator which is used to tune the PLL to the desired free-running frequency) and the bandgap reference (to obtain the correctabsolute valueof the output signal). The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode.

The circuit can also decode the PALplus helper signal and can insert the various reference signals, set-ups and timing signals which are required for the PALplus decoder ICs.

The baseband delay line (TDA4665 function) is integrated.

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2000 Sep 25 9

VIM

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Philips Semiconductors Preliminary speciﬁcation

C-bus controlled TV input processor

VIDEO

IDENTIFICATION

14 16 18 20 21 23 28 2924

CVBS

int

CVBS1 CVBS2 C3 CVBS/Y4CVBS/Y3 C4 YCF CCF

ident

TDA9321H

+ + +

CVBSCF

to luminance/sync processing

to chrominance processing

CVBSPIP

MGR475

CVBSTXT

TDA9321H

Fig.3 Video switches and interfacing of video ident.

Page 10

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

RGB switch and matrix

The IC has two RGB inputs with fast switching. The switching of the various sources is controlled via the I2C-bus and the condition of the switch inputs can be read from the I2C-bus status bytes. If the RGB signals are not synchronous with the selected decoder input signal, an external clamp pulse has to be supplied to the HA/CLP input. The IC must be set in this mode via the I2C-bus. In this case, the VA pulse is suppressed by switching the VA output to a high impedance OFF state.

When an external RGB signal is mixed into the internal YUV signal, it is necessary to switch-off the PALplus demodulation. To detect the presence of a fast blanking, a circuit is added which forces the MACP and HD bits to zero if a blanking pulse is detected in two consecutive lines. This system is chosen to prevent switching off at every spike that is detected on the fast blanking input.

The IC can use input RGB1 as YUV input. This function can be enabled by bit YUV in subaddress 0A (D3). When switched to theYUV input, the input signals must have the same amplitude and polarity as the YUV output signals. The Y signal has to be supplied to the G1 input, the U signal to the B1 input and the V signal to the R1 input.

TDA9321H

If required, the IC can select the time constant, depending on the noise content of the incoming video signal.

The free-running frequency of the oscillator is determined by a digital control circuit, which is locked to the reference signal of the colour decoder. When the IC is switched on, the HA/CLP is suppressed and the oscillator is calibrated as soon as all sub-address bytes have been sent. When thefrequencyofthe oscillator is correct, the HA/CLPsignal is switched on again.

When the coincidence detector indicates an out-of-lock situation, the calibration procedure is repeated.

The VA pulse is obtained via a vertical countdown circuit. This circuit has various windows, depending on the incoming signal (50 or 60 Hz standard or no standard). The countdown circuit can be forced to various modes by means of the I2C-bus. To obtain short switching times of the countdown circuitduring a channelchange, the divider can be forced in the search window by means of bit NCIN.

C-BUS SPECIFICATION

The slave addresses of the ICs are given in Table 1. The circuit operates up to clock frequencies of 400 kHz.

Synchronization circuit

The sync separator is preceded by a controlled amplifier that adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage, which operates at 50% of the amplitude. The separated sync pulses are fed to the phase detector and to the coincidence detector. This detector detects whether the line oscillator is synchronized and can also be used for transmitter identification. This circuit can be made less sensitive by means of bit STM. This mode can be used during search tuning to avoid the tuning system from stopping at very weak input signals. The PLL has a very high static steepness so that the phase of the picture is independent of the line frequency.

Two conditions are possible for the horizontal output pulse:

• An HA pulse which has a phase and width that are identical to the incoming horizontal sync pulse

• A Clamp Pulse (CLP) which has a phase and width that are identical to the clamp pulse in the sandcastle pulse.

Signal HA/CLP is generated by an oscillator that runs at a frequency of 440 × fH. Its frequency is divided by 440 to lockthe first loopto the incomingsignal. The timeconstant of the loop can be forced by the I2C-bus (fast or slow).

Table 1 Slave addresses

A6 A5 A4 A3 A2 A1 A0 R/W

10001A111/0

Bit A1 is controlled via pin 48 (AS). When the pin is connected to ground, it is a logic 0; when connected to the positive supply line, it is a logic 1. When this pin is left open, it is connected to ground via an internal resistor.

Start-up procedure

Read the status bytes until POR = logic 0 and send all subaddress bytes. Check the bus transmission by reading output status bits SXA to SXD. This ensures good operation of the calibration system of the horizontal oscillator.Thehorizontal output signal is switched onwhen the oscillator is calibrated.

Read the status bytes each time before the data in the IC is refreshed. If POR = logic 1, the procedure mentioned above must be carried out to restart the IC. When this procedureis not followed,thehorizontal frequency may be incorrect after power-up or after a power dip.

The 00 to 0E subaddresses are valid. The FE and FF subaddresses are reserved for test purposes. The auto-increment mode is available for subaddresses.

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

Inputs and outputs Table 2 Input status bits

FUNCTION

Colour decoder 0 00 CM3 CM2 CM1 CM0 XD XC XB XA Colour decoder 1 01 MACP HOB HBC HD FCO ACL CB BPS Luminance 02 0 0 GAI1 GAI0 YD3 YD2 YD1 YD0 Hue control 03 0 0 A5 A4 A3 A2 A1 A0 Spare 04 0 0 0 0 0 0 0 0 Synchronization 0 05 FORF FORS FOA FOB 0 VIM POC VID Synchronization 1 06 0 0 0 0 BSY HO EMG NCIN Spare 07 0 0 0 0 0 0 0 0 Video switches 0 08 0 0 0 ECMB DEC3 DEC2 DEC1 DEC0 Video switches 1 09 0 PIP2 PIP1 PIP0 0 TXT2 TXT1 TXT0 RGB switch 0A 0 0 0 0 YUV ECL IE2 IE1 Output switches 0B 0 0 0 0 0 0 OS1 OS0 Vision IF 0C FFI IFO GD MOD AFW IFS STM VSW Tuner takeover 0D 0 0 A5 A4 A3 A2 A1 A0 Adjustment IF-PLL 0E L’FA A6 A5 A4 A3 A2 A1 A0

SUBADDRESS

(HEX)

D7 D6 D5 D4 D3 D2 D1 D0

DATA BYTE

TDA9321H

INPUT CONTROL BITS

Table 3 Colour decoder mode

CM3 CM2 CM1 CM0 DECODER MODE XTAL

0 0 0 0 PAL/NTSC/SECAM A 0 0 0 1 PAL/NTSC A 0010PAL A 0 0 1 1 NTSC A 0 1 0 0 SECAM A 0 1 0 1 PAL/NTSC B 0110PAL B 0 1 1 1 NTSC B 1 0 0 0 PAL/NTSC/SECAM A/B/C/D 1 0 0 1 PAL/NTSC C 1010PAL C 1 0 1 1 NTSC C 1 1 0 0 PAL/NTSC A/B/C/D 1 1 0 1 PAL/NTSC D 1110PAL D 1 1 1 1 NTSC D

Table 4 Crystal indication

XA to XD CONDITION

0 crystal not present 1 crystal present; note 1

Note

1. When a comb filter is used, the various crystals must be connected to the IC as indicated in the pinning diagram. This is required because the ident system switches automatically tothe comb filter when asignal is identified which can be combed (correct combinationofcolour standard and crystalfrequency). For applications without comb filter only the crystal on pin XTALA is important (4.43 MHz); to pins XTALB to XTALD an arbitrary3.5 MHz crystal can be connected.

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

Table 5 Motion Adaptive Colour Plus (MACP)

MACP MODE

0 internal 4.43 MHz trap used 1 external MACP chrominance ﬁltering used;

4.43 MHz trap bypassed and black set-up 200 mV; note 1

Note

1. The black set-up will only be present in a norm sync condition.

Table 6 Helper output blanking (PALplus/EDTV-2)

HOB HBC SNR BLANKING

(1)

10X 110off 111on

Note

1. X = don’t care.

Table 7 PALplus helper demodulation active

HD CONDITIONS

0 off 1 on; PALplus mode with helper set-up 400 mV

and black set-up 200 mV; note 1

Note

1. Black and helper set-up will only be present in a norm sync condition.

Table 8 Forced colour on

FCO MODE

0 not active 1 active

Table 9 Automatic colour limiting

ACL COLOUR LIMITING

0 not active 1 active

(1)

off

(1)

TDA9321H

Table 10 Chrominance band-pass centre frequency

CB CENTRE FREQUENCY

1 1.1 × f

Table 11 Bypass of chrominance baseband delay line

BPS DELAY LINE MODE

0 active 1 bypassed

Table 12 Gain luminance channel

GAI1 GAI0 GAIN SETTING

00−1dB 010dB 1 0 +1 dB 1 1 +2 dB

Table 13 Y-delay adjustment; notes 1 and 2

YD0 to YD3 Y-DELAY

YD3 YD3 × 160 ns YD2 YD2 × 160 ns YD1 YD1 × 80 ns YD0 YD0 × 40 ns

Notes

1. For an equal delay of the luminance and chrominance signal the delay must be set at a value of 280 ns (YD3 to YD0 = 1011). This is only valid for a CVBS signal without group delay distortions.

2. The total Y-delay is the addition of: YD3 + YD2 + YD1 + YD0.

Table 14 Forced ﬁeld frequency

FORF FORS FIELD FREQUENCY

0 0 auto (60 Hz when line not

0 1 forced 60 Hz; note 1 1 0 keep last detected ﬁeld frequency 1 1 auto (50 Hz when line not

synchronized)

2000 Sep 25 12

Note

1. When switched to this mode the divider will directly switch to forced 60 Hz only.

Page 13

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

Table 15 Phase 1 (ϕ1) time constant; see also Table 57

FOA FOB MODE

0 0 normal 0 1 slow 1 0 slow or fast 1 1 fast

Table 16 Video ident mode

VIM MODE

0 ident coupled to internal CVBS (pin 14) 1 ident coupled to selected CVBS

Table 17 Synchronization mode

POC MODE

0 active 1 not active

TDA9321H

Table 19 Blanked sync on pin YO

BSY CONDITIONS

0 unblanked sync; note 1 1 blanked sync

Note

1. Except for PALplus with black set-up.

Table 20 Condition of horizontal output

HO CONDITIONS

0 clamp pulse available on pin HA/CLP 1 horizontal pulse available on pin HA/CLP

Table 21 Enable ‘Macrovision/subtitle’ gating

EMG MODE

0 disable gating 1 enable gating

Table 18 Video ident mode

VID VIDEO IDENT MODE

0 ϕ 1 not active

loop switched-on and off

Table 22 Vertical divider mode

NCIN VERTICAL DIVIDER MODE

0 normal operation 1 switched to search window

2000 Sep 25 13

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

Table 23 Video switch control

(1)

ECMB

0000X 00010CVBS1 CVBS1 00011CVBS2 CVBS2 00100CVBS3 CVBS3 00101Y3/C3 Y3 + C3 00110CVBS4 CVBS4 00111Y4/C4 Y4 + C4 01100AUTO Y3/C3; note 3 CVBS3 or Y3 + C3 01110AUTO Y4/C4; note 3 CVBS4 or Y4 + C4 1000X 10010YCF/CCF CVBS1 10011YCF/CCF CVBS2 10100YCF/CCF CVBS3 10110YCF/CCF CVBS4 11100AUTO COMB3; note 4 CVBS3 or Y3 + C3 11110AUTO COMB4; note 4 CVBS4 or Y4 + C4

DEC3 DEC2 DEC1 DEC0 SELECTED SIGNAL SIGNAL TO COMB

(2)

CVBS

int

(2)

YCF/CCF CVBS

CVBS

int

TDA9321H

Notes

1. When bit ECMB = 1 the subcarrier frequency is present on pin 30. The YCF and CCFsignals coming from the comb filter are only switched on when a signal is received that can be combed.

2. X = don’t care.

3. AUTO YC means the decoder switches between CVBS and Y/C depending on the presence of the burst signal on these signals.

4. AUTO COMB means the decoder switches to Y/C mode if the burst is present on the C input and to the comb filter output if the burst is present on the CVBS signal.

Table 24 Video switch outputs Table 25 Enable YUV input (on RGB1 input)

TXT2

PIP2

00−CVBS

TXT1

PIP1

TXT0

PIP0

OUTPUT SIGNAL TXT

OUTPUT SIGNAL PIP

int

YUV MODE

0 RGB1 input active 1 YUV input active

0 1 0 CVBS1 0 1 1 CVBS2 1 0 0 CVBS3 101Y3+C3 1 1 0 CVBS4 111Y4+C4

Table 26 External RGB clamp mode

ECL MODE

0 off; internal clamp pulse used 1 on; external clamp pulse has to be supplied to

pin HA/CLP

2000 Sep 25 14

Page 15

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

Table 27 Enable fast blanking RGB1

IE1 FAST BLANKING

0 not active 1 active

Table 28 Enable fast blanking RGB2

IE2 FAST BLANKING

0 not active 1 active

Table 29 Output switches OS0 and OS1

OS0;

OS1

0 output = LOW 1 output = HIGH

Table 30 Fast ﬁlter IF-PLL

FFI CONDITIONS

0 normal time constant 1 fast time constant

Table 31 IF circuit not active

IFO MODE

0 normal operation of IFampliﬁer 1 IFampliﬁer switched off

Table 32 Group delay correction

GD GROUP DELAY CHARACTERISTIC

0 ﬂat 1 according to BG standard

CONDITIONS

TDA9321H

Table 33 Modulation standard

MOD MODULATION

0 negative 1 positive

Table 34 AFC window

AFW AFC WINDOW

0 normal 1 enlarged

Table 35 IF sensitivity

IFS IF SENSITIVITY

0 normal 1 reduced

Table 36 Search tuning mode

STM MODE

0 normal operation 1 reduced sensitivity of video ident circuit

Table 37 Video mute

VSW STATE

0 normal operation 1 VIF signal switched off

Table 38 PLL demodulator frequency shift

L’FA MODE

0 normal IF frequency 1 frequency shift for L’ standard

Table 39 Output status bits

FUNCTION

Output status bytes 00 POR X

Note

1. X = don’t care.

2000 Sep 25 15

SUBADDRESS

(HEX)

01 CD3 CD2 CD1 CD0 SXD SXC SXB SXA 02 IN1 IN2 CMB YC S2A S2B S1A S1B 03 ID3 ID2 ID1 ID0 IFI PL AFA AFB

D7 D6 D5 D4 D3 D2 D1 D0

(1)

DATA BYTE

(1)

SNR FSI SL IVW

Page 16

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

OUTPUT CONTROL BITS

Table 40 Power-on reset

POR MODE

0 normal 1 power-down

Table 41 Signal-to-noise ratio of sync signal

SNR SIGNAL-TO-NOISE RATIO

0 S/N > 20 dB 1 S/N < 20 dB

Table 42 Field frequency indication

FSI FREQUENCY

050Hz 160Hz

TDA9321H

Table 43 Phase 1 (ϕ1) lock indication

SL INDICATION

0 not locked 1 locked

Table 44 Condition vertical divider

IVW STANDARD VIDEO SIGNAL

0 no standard video signal 1 standard video signal in ‘narrow window’ or

standard TV norm (525 or 625 lines)

Table 45 Crystal indication (SXA to SXD)

SXAto

SXD

0 no crystal connected 1 crystal connected

CONDITIONS

Table 46 Colour decoder mode

CD3 CD2 CD1 CD0 STANDARD XTAL

0000no colour standard identiﬁed A/B/C/D 0001NTSC A 0010PAL A 0011NTSC B 0100PAL B 0101NTSC C 0110PAL C 0111NTSC D 1000PAL D 1001SECAM A 1010illegal forced mode; note 1 −

Note

1. This mode is generated when trying (e.g. via software control) to force the decoder to a standard with a crystal which is not connected to the IC.

2000 Sep 25 16

Page 17

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

Table 47 Indication RGB1/RGB2 insertion

IN1;

IN2

0 no insertion 1 full insertion

Table 48 Condition YCF/CCF inputs from comb ﬁlter

CMB CONDITION YCF/CCF INPUTS

0 not selected 1 selected

Table 49 Input signal condition; note 1

YC CONDITIONS

0 CVBS signal available 1 Y/C signal available

Note

1. During the search mode for the colour system, bit YC will indicate logic 1.

Table 50 Condition of AV1 and AV2 inputs

S1A;

S2A

0 0 no external source 0 1 external source with 4 : 3 input

1 0 external source with 16 : 9 input

S1B;

S2B

RGB INSERTION

CONDITIONS

signal

TDA9321H

Table 51 Output video identiﬁcation

IFI VIDEO SIGNAL

0 no video signal identiﬁed 1 video signal identiﬁed

Table 52 In-lock indication IF-PLL

PL CONDITIONS

0 PLL not locked 1 PLL locked

Table 53 AFC output

AFA AFB CONDITIONS

0 0 outside window; too low 0 1 outside window; too high 1 0 in window; below reference 1 1 in window; above reference

Table 54 IC version indication

ID3 ID2 ID1 ID0 IC TYPE

0001TDA9321HN1 1001TDA9321HN2

2000 Sep 25 17

Page 18

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

stg

amb

sld

supply voltage on pins VP1and V

storage temperature −25 +150 °C operating ambient temperature 0 70 °C soldering temperature for 5 s − 260 °C junction temperature − 150 °C electrostatic handling on all pins notes 1 and 2 −3000 +3000 V

− 9.0 V

notes 1 and 3 −300 +300 V

Notes

1. All pins are protected against ESD by means of internal clamping diodes.

2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.

3. Machine Model (MM): R = 0 Ω; C = 200 pF.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 50 K/W

QUALITY SPECIFICATION

Quality specification in accordance with

“SNW-FQ-611E”

Latch-up performance

At an ambient temperature of 70 °C all pins meet the following specification:

• Positive stress test: I

• Negative stress test: I

≥ 100 mA or V

trigger

≤−100 mA or V

trigger

≥ 1.5 × V

P(max)

≤−0.5 × V

P(max)

2000 Sep 25 18

Page 19

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

CHARACTERISTICS

VP=8V; T

=25°C; unless otherwise speciﬁed.

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pins V

tot

and VP2); note 1

supply voltage (pins VP1and VP2) 7.2 8.0 8.8 V supply current (pins VP1and VP2) − 120 140 mA total power dissipation − 960 − mW

Vision IF circuit

VISION IF AMPLIFIER INPUTS (PINS VIF1 AND VIF2) V

i(rms)

i(max)(rms)

i(dif)

∆G

input sensitivity (RMS value) note 2

= 38.90 MHz − 35 200 µV

i(VIF)

= 45.75 MHz − 35 200 µV

i(VIF)

= 58.75 MHz − 40 200 µV

i(VIF)

maximum input signal (RMS value) 150 200 − mV differential input resistance note 3 − 2 − kΩ differential input capacitance note 3 − 3 − pF

voltage gain control range 64 75 80 dB PLL DEMODULATOR (PLL FILTER ON PIN VIFPLL); note 4 f

PLL

cr(PLL)

acq(PLL)

∆f

/∆T VCO frequency dependency with

VCO

PLL frequency range 32 − 60 MHz

PLL catching range 2.0 2.7 3.3 MHz

PLL acquisition time −− 20 ms

notes 5 and 6 − 300 − kHz/K

temperature f

tune(VCO)

∆f

DAC

VCO tuning frequency range via I2C-bus 3.0 3.7 4.2 MHz

frequency variation per step of the

23 29 33 kHz

DAC (A0to A6) f

shift

frequency shift with bit L’FA − 5.5 − MHz VIDEO AMPLIFIER OUTPUT (PIN VIFO); note 7 V

o(z)

zero signal output level note 8

negative modulation 4.6 4.7 4.8 V

positive modulation 1.9 2.0 2.1 V V V ∆V

o(ts) o(w)

top-sync level negative modulation 1.9 2.0 2.1 V white level positive modulation 4.4 4.5 4.6 V difference in amplitude between

− 015%

negative and positive modulation

o(v)

bias(int)

video output impedance − 50 −Ω internal bias current of NPN

1.0 −−mA

emitter follower output transistor

source(max)

v(−3dB)

maximum source current −− 5mA

−3 dB bandwidth of demodulated

6 8 10 MHz

output signal

dif

differential gain note 9 −− 1.5 %

2000 Sep 25 19

Page 20

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

dif

vid

clamp

ins

differential phase notes 6 and 9 −− 2.5 deg video non-linearity note 10 − 35% white spot clamping level − 6.0 − V noise inverter clamping level note 11 − 1.5 − V noise inverter insertion level

note 11 − 2.7 − V

(identical to black level)

blue

intermodulation at ‘blue’ notes 6 and 12

f = 0.92 or 1.1 MHz 60 66 − dB

f = 2.66 or 3.3 MHz 60 66 − dB d

yellow

intermodulation at ‘yellow’ notes 6 and 12

f = 0.92 or 1.1 MHz 56 62 − dB

f = 2.66 or 3.3 MHz 60 66 − dB S/N S/N

∆V ∆V

UW rc rc(2H)

weighted signal-to-noise ratio notes 6 and 13 56 60 65 dB unweighted signal-to-noise ratio notes 6 and 13 49 53 − dB residual carrier signal note 6 − 5.5 − mV 2nd harmonic of residual carrier

note 6 − 2.5 − mV

signal

PSRR power supply ripple rejection at the output − 40 − dB VIF

AND TUNER AGC; note 14

Timing of VIF-AGC with a 2.2µF capacitor (pin DEC

VIF

)

MVI modulated video interference 60% AM for 1 to 100 mV;

0 to 200 Hz; system B/G

res

response time VIF input signal amplitude

increase of 52 dB; positive and negative modulation

VIF input signal amplitude decrease of 52 dB

negative modulation − 50 − ms positive modulation − 100 − ms

∆V

o(v)

leakage current of the capacitor on pin 4

change in video output signal

negative modulation −− 10 µA positive modulation −− 200 nA

capacitor on pin 4 is 0.5 µF −− 2% amplitude over1 vertical period for peak white AGC at positive modulation

Tuner takeover point adjustment (via I2C-bus)

strt(min)(rms)

strt(max)(rms)

∆V

max

minimum start level (RMS value) − 0.4 0.8 mV maximum start level (RMS value) 100 150 − mV maximum variation with

= 0to70°C − 68dB

amb

temperature

−− 10 %

− 2 − ms

2000 Sep 25 20

Page 21

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Tuner control output (pin TAGC)

o(max)

o(sat)

maximum output voltage maximum tuner gain; note 3 −− 9V output saturation voltage minimum tuner gain;

−− 300 mV

Io=2mA

o(max)

∆V

maximum output current swing 5 −−mA leakage current for RFAGC −− 1µA input signal variation for complete tuner control 0.5 2 4 dB

AFC OUTPUT (VIA I2C-BUS); note 15 RES

∆f

AFC

AFC resolution − 2 − bits window sensitivity normal window mode 55 65 90 kHz

enlarged window mode 175 195 270 kHz

IDEO IDENTIFICATION OUTPUT (VIA I

V t

delay time for identiﬁcation after the

C-BUS)

−− 10 ms AGC has stabilized on a new transmitter

Sound IF circuit

SOUND IF AMPLIFIER (PINS SIF1 AND SIF2) V

i(rms)

i(max)(rms)

i(dif)

∆G

ct(SIF-VIF)

input sensitivity (RMS value) FM mode (−3 dB) − 100 140 µV

maximum input signal (RMS value) FM mode 50 70 − mV

differential input resistance note 3 − 2 − kΩ differential input capacitance note 3 − 3 − pF voltage gain control range 64 −−dB crosstalk between inputs SIF

and VIF

QSS AND AM SOUND OUTPUT (PIN QSS/AM)

General

bias(int)

output resistance −− 250 Ω DC output voltage − 3.3 − V internal bias current of emitter

follower

sink(max)

source(max)

maximum AC and DC sink current − 0.7 − mA maximum AC and DC source

current

AM mode (−3 dB) − 200 300 µV

AM mode 80 140 − mV

50 −−dB

0.7 1.0 − mA

− 2.0 − mA

2000 Sep 25 21

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

QSS output signal

o(rms)

output signal amplitude

SC1 on; SC2 off 70 90 110 mV

(RMS value)

−3dB

∆V

r(SC)(rms)

−3 dB bandwidth 7.5 9 − MHz residual IF sound carrier

− 2 − mV

(RMS value)

S/N

weighted signal-to-noise ratio (SC1/SC2)

ratio of PC/SC1 at VIF input of 40 dB or higher; note 16

black picture 53/48 58/55 − dB white picture 52/47 55/53 − dB 6 kHz sine wave

44/42 48/46 − dB

(black-to-white modulation) 250 kHz sine wave

44/25 48/30 − dB

(black-to-white modulation) SC subharmonics

45/44 51/50 − dB

(f = 2.75 MHz ±3 kHz) SC subharmonics

46/45 52/51 − dB

(f = 2.87 MHz ±3 kHz)

AM output signal

o(rms)

output signal amplitude

54% modulation 500 600 700 mV

(RMS value) THD total harmonic distortion − 0.5 1.0 % B

−3dB

S/N

−3 dB bandwidth 100 125 − kHz

weighted signal-to-noise ratio 47 53 − dB

Video switches and comb ﬁlter interface

VIDEO SWITCHES FOR CVBS, Y AND C SIGNALS

Signal on pins CVBS

i(n)(p-p)

i(n)

source(max)

sup(n)

input voltage (peak-to-peak value) note 17 − 1.0 1.43 V

input current − 4 −µA

maximum source impedance −− 1.0 kΩ

suppression of non-selected

, CVBS1, CVBS2, CVBS/Y3 and CVBS/Y4

int

fi= 0 to 5 MHz; note 6 50 −−dB

signals

Signal on pins C3 and C4

i(n)(p-p)

i(n)

input voltage (peak-to-peak value) notes 3 and 18 − 0.3 1.0 V

input impedance − 50 − kΩ

2000 Sep 25 22

Page 23

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Signal on pin CVBSTXT

o(p-p)

output signal amplitude

1.6 2.0 2.4 V

(peak-to-peak value) V

∆V

/∆T black level dependency with

black level − 2.6 − V

− 4 − mV/K

temperature Z

output impedance −− 250 Ω

Signal on pin CVBSPIP

o(p-p)

output signal amplitude

0.8 1.0 1.2 V

(peak-to-peak value) V

∆V

/∆T black level dependency with

black level − 3.6 − V

− 9 − mV/K

temperature Z

output impedance −− 250 Ω COMB FILTER INTERFACE; note 19

Signal on pin CVBSCF

o(p-p)

output signal amplitude

0.8 1.0 1.2 V

(peak-to-peak value) Z

∆V

/∆T black level dependency with

output impedance −− 250 Ω

black level − 3.6 − V

− 9 − mV/K

temperature

Signal on pin YCF

V I

i(p-p)

input voltage (peak-to-peak value) − 1.0 1.43 V

input current − 4 −µA

Signal on pin CCF

Reference signal output (pin REFO);

o(p-p)

input voltage burst amplitude − 0.3 1.0 V

input impedance − 50 − kΩ

note 20

output signal amplitude

CL= 15 pF 0.2 0.25 0.3 V

(peak-to-peak value) V

O(en)

DC output level to enable

4.0 4.2 4.6 V

comb ﬁlter V

O(dis)

DC output level to disable comb

− 0.1 1.4 V

ﬁlter

Switching levels of SYS1 and SYS2 outputs (pins SYS1 and SYS2);

o(sink)

o(source)

HIGH-level output voltage 4.0 5.0 5.5 V

LOW-level output voltage − 0.1 0.4 V

output sink current 2 −−mA

output source current 2 −−mA

note 21

2000 Sep 25 23

Page 24

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DETECTION OF STATUS LEVELS OF SCART PLUG PIN 8; note 22 V

det(int-ext)

detection voltage between internal

2.0 2.2 2.4 V

and external (16 : 9) source V

det(ext-ext)

detection voltage betweenexternal

5.3 5.5 5.7 V

(16 : 9) and external (4 : 3) source R

input resistance 60 100 − kΩ

Chrominance and luminance ﬁlters and delay lines

CHROMINANCE TRAP CIRCUIT; note 23 f

trap

trap frequency f

±1% MHz

osc

during SECAM reception 4.3 ±1.5% MHz

−3dB

−3 dB bandwidth fSC= 3.58 MHz 2.6 2.8 3.0 MHz

= 4.43 MHz 3.2 3.4 3.6 MHz

during SECAM reception 2.9 3.1 3.3 MHz

CSR colour subcarrier rejection 26 −−dB C

HROMINANCE BAND-PASS CIRCUIT

centre frequency bit CB = 0 − f

bit CB = 1 − 1.1f

osc

band-pass quality factor − 3 −

− MHz

CLOCHE FILTER f

centre frequency 4.26 4.29 4.31 MHz B bandwidth 241 268 295 kHz

Y-

DELAY LINE

delay time bits YD3 to YD0 = 1011;

note 6

crystal A 490 520 550 ns crystal B, C or D 530 560 590 ns

d(tr)

tuning range delay time with respect to 520/560 ns;

−280 − +160 ns

12 settings; see Table 13

B bandwidth note 6 8 −−MHz G

ROUP DELAY CORRECTION (PINS GDI AND GDO); note 24

i(GDI)(p-p)

input signal amplitude on pin GDI

− 2.0 − V

(peak-to-peak value) I

i(GDI)

o(GDO)(p-p)

input current on pin GDI − 0.1 1.0 µA

output signal amplitude on

1.8 2.0 2.2 V

pin GDO (peak-to-peak value) V

o(GDO)

∆V

o(GDO)

output top-sync level on pin GDO − 2.4 − V

/∆T top-sync level on pin GDO

− 5 − mV/K

variation with temperature Z

o(GDO)

output impedance on pin GDO −− 250 Ω

2000 Sep 25 24

Page 25

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Colour demodulation part

CHROMINANCE AMPLIFIER CR

∆V

o(CRACC)

ck(on)

hys

ACC

ck(off)

ACC control range note 25 26 −−dB

change in amplitude of the output

signals over CR

ACC

−− 2dB

threshold colour killer ON colour killer from OFF to ON −40 −−35 dB

hysteresis colour killer OFF note 6

strong signal; S/N ≥ 40 dB − 3 − dB

noisy input signals − 1 − dB ACL CIRCUIT; note 26 C/C

ACL

ACL chrominance burst ratio when the ACL starts to

− 3.0 −

operate

REFERENCE PART

Phase-locked loop;

∆ϕ phase shift for a ±400 Hz deviation of the

note 27

catching range ±360 ±600 − Hz

−− 2 deg

oscillator frequency; note 6

Oscillator

fosc

temperaturecoefﬁcient of oscillator

note 6 −− 1 Hz/K

frequency

∆f

osc

oscillator frequency variation with

VP=8V±10%; note 6 −− 25 Hz

respect to the supply voltage

neg(min)

L(max)

minimum negative resistance −− 1.0 kΩ

maximum load capacitance −− 15 pF HUE CONTROL; note 28 CR

hue

∆hue/∆V

hue control range 63 steps; see Fig.4 ±35 ±40 − deg

hue dependency with respect to

VP±10%; note 6 − 0 − deg

the supply voltage ∆hue/∆T hue dependency with temperature T

= 0 to 70 °C; note 6 − 0 − deg

amb

DEMODULATORS

General

∆V/∆V spread of signal amplitude ratio

note 6 −1 − +1 dB

between standards

2000 Sep 25 25

Page 26

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

PAL/NTSC demodulator

(B-Y)(R-Y)

gain between both demodulators

1.60 1.78 1.96

(B − Y) and (R − Y) B

−3dB(dem)

∆V

o(rc)(p-p)

H/2(p-p)

−3 dB bandwidth of demodulators note 29 − 650 − kHz

residual carrier output

(peak-to-peak value)

H/2 ripple rejection (peak-to-peak

f=f

; (R − Y) output −− 5mV

osc

f=f

; (B − Y) output −− 5mV

osc

f=2f f=2f

; (R − Y) output −− 5mV

osc

; (B − Y) output −− 5mV

osc

at (R − Y) output −− 25 mV

value)

/∆T output voltage variation with

∆V

note 6 − 0.1 − %/K

temperature ∆V

/∆V

output voltage variation with

note 6 −− 0.3 dB/V

respect to the supply voltage

phase error in the demodulated

note 6 −− ±5 deg

signals

SECAM demodulator

blos

∆f

/∆T black level offset frequency

blos

black level offset frequency −− 7 kHz

−− 60 Hz/K

variation with temperature f

p/fz

pole frequency of de-emphasis 77 85 93 kHz

ratio pole and zero frequency − 3 − NL non-linearity −− 3% V

cal

calibration voltage 3 4 5 V

Baseband delay line

∆V

variation of output signal for adjacent time samples at

−0.1 − 0.1 dB

constant input signals

∆V

r(clk)(p-p)

residual clock signal (peak-to-peak

−− 5mV

value) t

delay delayed signal 63.94 64.0 64.06 µs

non-delayed signal 40 60 80 ns

∆V

difference in output amplitude when delay line is bypassed

−− 5%

or not (with bit BPS)

2000 Sep 25 26

Page 27

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

PALplus helper demodulator

o(helper)(p-p)

helper output voltage

610 686 770 mV

(peak-to-peak value) V

su(helper)

d(g)

e(dem)

sup

helper set-up amplitude only helper lines 22 and 23 380 400 420 mV

group delay within pass band −− 10 ns

demodulation phase error including H/2 phase error −− 5 deg

suppression for modulated helper in

−36 −−dB demodulated 0 to 1 MHz signal

∆V

residual signal at 4.43 MHz signal −36 −−dB THD total harmonic distortion in ACC −36 −−dB t

o(helper-Y)

offset

helper output timing to Youtput −− 10 ns

offset voltage for demodulated mid grey to

−− 5mV inserted mid grey level; mid grey line 23 to line 22

W(su)(helper)

helper set-up pulse width − 52.8 −µs delay between mid sync of input

and start of helper set-up delay between start of blackset-up

bits YD3 to YD0 = 1011;

− 8.6 −µs note 30

only lines 22 and 23 − 30.8 −µs

and start of helper set-up

helper(−3dB)

−3 dB bandwidth of helper

− 2.6 − MHz

baseband

RGB switch and YUV switch

RGB SWITCH (PINS RI1 TO BI1 AND RI2 TO BI2) V

i(p-p)

input signal amplitude (peak-to-peak value)

source(max)

∆V

bl(int-ext)

maximum source impedance −− 1.0 kΩ difference between black level of

internal and external signals at the

outputs I ∆t

input current no clamping; note 3 − 0.1 1 µA

delay difference between the three

channels

− 0.7 1.0 V

−− 10 mV

note 6 − 020ns

2000 Sep 25 27

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

YUV INPUTS (WHEN ACTIVATED) V

i(Y)(p-p)

Y input signal amplitude

− 1.0 − V

(peak-to-peak value) V

i(U)(p-p)

U input signal amplitude

− 1.33 − V

(peak-to-peak value) V

i(V)(p-p)

V input signal amplitude

− 1.05 − V

(peak-to-peak value) Z

source(max)

∆V

bl(int-ext)

maximum source impedance −− 1.0 kΩ

difference between black level of

−− 10 mV internal and external signals at the outputs

input current no clamping; note 3 − 0.1 1 µA

FAST BLANKING (PINS RGB1 AND RGB2) V

input voltage no data insertion −− 0.4 V

data insertion 0.9 −−V

i(max)

∆t

d(blank-RGB)

maximum input pulse −− 3.5 V input current −− 0.2 mA delay difference between blanking

note 6 −− tbf ns

and RGB signals

sup(int)

sup(ext)

d(blank-YUV)

suppression of internal YUV signals

suppression of external RGB signals

delay between blanking input and

data insertion; fi= 0 to 5 MHz; note 6

no data insertion; fi= 0 to 5 MHz; note 6

55 −−dB

−− tbf ns YUV outputs

LUMINANCE OUTPUT (PIN YO); note 31 V

o(p-p)

output signal amplitude

black-to-white − 1.0 − V

(peak-to-peak value)

∆V

bl(YUV-RGB)

output voltage during PALplus black-to-white − 0.8 − V difference in black level between

−− 10 mV YUV and RGB mode

RGB(−3dB)

output impedance −− 250 Ω output DC voltage level black level 2.8 3.0 3.2 V

−3 dB bandwidth of the RGB

7 −−MHz

switch circuit

S/N signal-to-noise ratio f V

su(bl)

W(su)(bl)

black set-up amplitude bit MACP = 1 or bit HD = 1 190 200 210 mV black set-up pulse width − 52.8 −µs delay between mid sync at input

= 0 to 5 MHz − 52 − dB

note 30 − 8.8 −µs

and black set-up

offset

offset voltage Ybl to re-inserted black −− 10 mV

2000 Sep 25 28

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

(Y/CVBS-YO)

gain from internal Y/CVBS to YO 1.35 1.43 1.50

bit MACP = 1 or bit HD = 1 1.08 1.14 1.20

AND VO SIGNAL OUTPUTS (PINS UO AND VO)

o(VO)(p-p)

output voltage on pin VO

standard EBU colour bar 0.88 1.05 1.25 V

(peak-to-peak value)

o(UO)(p-p)

output voltage on pin UO

standard EBU colour bar 1.12 1.33 1.58 V

(peak-to-peak value)

∆V

bl(YUV-RGB)

output impedance −− 250 Ω output DC voltage level 2.2 2.4 2.6 V difference in black level between

−− 10 mV YUV and RGB mode

COLOUR MATRIX FROM RGB TO YUV G gain

from RI to YO 0.40 0.43 0.46 from GI to YO 0.79 0.84 0.90 from BI to YO 0.15 0.16 0.17 from RI to UO 0.40 0.43 0.46 from GI to UO 0.79 0.84 0.90 from BI to UO 1.19 1.27 1.35 from RI to VO 0.94 1.00 1.07 from GI to VO 0.79 0.84 0.90 from BI to VO 0.15 0.16 0.17

Horizontal and vertical synchronization

YNC VIDEO INPUTS

V SL SL

sync

hor vert

sync pulse amplitude note 3 35 300 350 mV slicing level for horizontal sync note 32 50 55 60 % slicing level for vertical sync note 32 35 40 45 %

HORIZONTAL OSCILLATOR f

∆f

∆f frequency dependency with

free-running frequency − 15625 − Hz spread on free-running frequency −− ±2%

= 8.0 V ±10%; note 6 − 0.2 0.5 %

respect to the supply voltage

∆f

max

frequency variation with

= 0 to 70 °C; note 6 −− 80 Hz

amb

temperature

FIRST CONTROL LOOP (PIN PH1LF); note 33 f

hr(PLL)

cr(PLL)

PLL holding range −±0.9 ±1.2 kHz PLL catching range note 6 ±0.6 ±0.9 − kHz

S/N signal-to-noise ratio for the video input signal at

which the time constant is switched

hys

hysteresis at the switching point 2 3 4 dB

2000 Sep 25 29

15 17 19 dB

Page 30

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

sigma value of phase jitter in automatic mode; ±3 σ−− 5ns

HORIZONTAL PULSE OUTPUT AND CLAMP PULSE INPUT/OUTPUT (PIN HA/CLP)

Switched to HA output (bit HO = 1)

o(sink)

o(source)

HIGH-level output voltage I LOW-level output voltage I

o(source) o(sink)

= 2 mA 4.0 5.0 5.5 V

= 2mA − 0.2 0.4 V output sink current 2 −−mA output source current 2 −−mA pulse width at nominal horizontal

4.6 4.7 4.8 µs

frequency

delay between mid sync of input

note 30 0.3 0.45 0.6 µs

and mid HA pulse

Switched to CLP output (bit HO = 0)

pulse width at nominal horizontal

3.5 3.6 3.7 µs

frequency

delay between start of CLP pulse to start of black set-up

bit HD = 1 or bit MACP = 1; bits YD3 to YD0 = 1011; at

5.2 5.3 5.4 µs

nominal horizontal frequency

delay between mid sync of input

note 30 3.0 3.2 3.4 µs

and start CLP pulse

Switched to CLP input (bit ECL = 1)

W(clamp)

∆V

(clamp)(n)

LOW-level input voltage 0 − 0.6 V HIGH-level input voltage 2.4 − 5.5 V clamping pulse width 1.8 3.5 −µs clamping offset between pins UO

−− 10 mV

and VO

input impedance 3 −−MΩ

VERTICAL OSCILLATOR; note 34 f

free-running frequency 50 Hz mode − 50 − Hz

60 Hz mode − 60 − Hz

lock

frequency locking range 45 − 64.5 Hz

D/D divider ratio not locked − 625/525 − lines LR locking range 488 − 722 lines/

frame VERTICAL PULSE OUTPUT (PIN VA) V

o(sink)

o(source)

HIGH-level output voltage I LOW-level output voltage I

o(source) o(sink)

output sink current 2 −−mA output source current 2 −−mA pulse width fVA=50Hz − 2.5 − lines

= 2 mA 4.0 5.0 5.5 V

=2mA − 0.2 0.4 V

=60Hz − 3.0 − lines

2000 Sep 25 30

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

delaybetween startof verticalsync

note 35 − 37.7 −µs of input and positive edge of vertical pulse on pin VA

output impedance bit ECL = 1 3 −−MΩ

SANDCASTLE OUTPUT (PIN SCO)

General

o(sink)

zero level voltage 0 0.5 1.0 V output sink current − 0.5 − mA

Horizontal/vertical blanking

o(source)

W(h)

output voltage level 2.2 2.5 2.8 V output source current − 0.7 − mA horizontal blanking pulse width − 10 −µs delay between start horizontal

− 6.4 −µs

blanking and start clamping pulse

Clamping pulse

o(source)

output voltage level 4.2 4.5 4.8 V output source current − 0.7 − mA pulse width − 3.6 −µs delay between mid sync of input

note 30 3.0 3.2 3.4 µs and start of clamping pulse

C-bus control

SCL AND SDA INPUTS/OUTPUTS (PINS SCL AND SDA) V

OL(SDA)

input voltage range 0 − 5.5 V LOW-level input voltage −− 1.5 V HIGH-level input voltage 3.5 −−V LOW-level input current VIL=0V −− −10 µA HIGH-level input current VIH= 5.5 V −− 10 µA LOW-level output voltage on

OL(SDA)

=3mA −− 0.4 V

pin SDA

SW0 AND SW1 OUTPUTS (PINS SW0 AND SW1); note 36 V

O(sink)

O(source)

HIGH-level output voltage 4.0 5.0 5.5 V LOW-level output voltage − 0.2 0.4 V output sink current 2 −−mA output source current 2 −−mA

Notes to the characteristics

1. Thetwo supply pins VP1and VP2mustbe decoupled separatelybut they mustbe connected toa single powersupply to avoid too big differences between them.

2. On set AGC.

3. This parameter is not tested during production and is just given as application information for the designer of the television receiver.

2000 Sep 25 31

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

4. Loop filter bandwidth B level as f

5. The optimum temperature stability of the PLL can be obtained when a TOKO coil as given in Table 55 is applied.

6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period.

7. Measured at 10 mV (RMS) top sync input signal.

8. So called projected zero point, i.e. with switched demodulator.

9. Measured in accordance with the test line given in Fig.5. For the differential phase test the peak white setting is reduced to 87%.

The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level.

The differential phase is defined as the difference in degrees between the largest and smallest phase angle.

10. This figure is valid for the complete video signal amplitude (peak white-to-black). See Fig.6.

11. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal).

12. The input conditions and test set-up are given in Figs 8 and 9. The figures are measured with an input signal of 10 mV (RMS).

13. Measured at an inputsignalof 10 mV (RMS). The S/Nis the ratio ofblack-to-whiteamplitude with respect tothe black level noise voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.

14. The AGC response time also depends on the acquisition time of the PLL demodulator. The values given are valid when the PLL is in lock.

15. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value is valid only when bit PL = 1.

16. The weighted S/N ratio is measured under the following conditions: a) The VIF modulator must meet the following specifications:

• Incidental phase modulation for black-to-white jumps less than 0.5 degrees.

• QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio)

• Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).

b) The measurements must be carried out with the Siemens SAW filters G3962 for VIF and G9350 for SIF.

Input level for SIF at 10 mV (RMS) with 27 kHz deviation.

c) The PC/SC ratio at the VIF input is calculated asthe additionof the TV transmitter ratio and the SAW filter PC/SC

ratio. This PC/SC ratio is necessary to achieve the S/NW values as indicated.

17. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

18. Indicated is a signal for a colour bar with 75% saturation (chrominance to burst amplitude ratio = 2.2 : 1).

19. When a signal is identified which can be combed (correct combination of colour standard and reference crystal) the comb filter is switched to that mode via pins 25 and 27 and then the filter is activated by switching on the reference carrier signal and connecting the output signals of the comb filter (pins 28 and 29) to the video processing circuits.

20. The subcarrier output signal can be used as a reference signal for external comb filter ICs (e.g. SAA4961). When bit ECMB = 0 the subcarrier signal is suppressed and the DC level is LOW. When bit ECMB = 1 the output level is HIGH and the subcarrier signal is present.

21. The outputs SYS1 and SYS2 can be used to switch the comb filter to the different colour standards (e.g. PAL-M, PAL-N, PAL-B/G and NTSC-M) and are controlled by the colour decoder identification circuit.

The setting of the outputs for the various standards is given in Table 56.

input signal level). LC-VCO circuit between pins 7 and 8: Q0= 60; C

PLL

better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.

= 60 kHz (natural frequency fn= 15 kHz; damping factor d = 2; calculated with top sync

lpf

= 30 pF.

int

TDA9321H

2000 Sep 25 32

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

22. For the detection ofthe status oftheincoming SCART signala voltage divider witha ratio of2 : 3has to beconnected between pin 8 of the SCART plug and the detection input. The impedance of the voltage divider should not be too high-ohmic because of the input impedance of 100 kΩ.

23. When the decoder is forced to a fixed subcarrier frequency (via bits XA to XD or bit CM) the chrominance trap is always switched on, also when no colour signal is identified. When 2 crystals are active the chrominance trap is switched off if no colour signal is identified.

24. The typical group delay characteristic for the B/G standard is given in Fig.7.

25. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)] the dynamic range of the ACC is +6 and −20 dB.

26. The ACL function canbe activated by bit ACL.The ACL circuit reducesthe gain of thechrominance amplifier for input signals with a C/C

which exceeds a value of 3.0.

ACL

27. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measuredwith the Philipscrystalseries 9922 520 with aseries capacitance Cs= 18 pF.The oscillator circuitisrather insensitive to the spurious responses of the crystal. As long as the resonance resistance of the third overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. The typical crystal parameters for the crystal series are:

a) Load resonance frequencies fL: 4.433619, 3.579545, 3.582056 and 3.575611 MHz; Cs= 20 pF. b) Motional capacitance C

= 20.6 fF (4.43 MHz crystal) or C

mot

= 14.7 fF (3.58 MHz crystal).

mot

c) Parallel capacitance Cp= 5.0 pF. The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and therefore

the figures regarding catching range are only valid for the specified crystal series. In this figure tolerances of the crystal with respect to the nominal frequency, motional capacitance and ageing have been taken into account and have been counted for gaussic addition. Whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the tuning capabilities:

Detuning range =

mot

------------------------ -





------ C

The resulting detuning range should be corrected for temperature shift and supply voltage deviation of both the IC and the crystal. To guarantee a catching range of ±300 Hz on 4.43 MHz the minimum motional capacitance of the crystal must have a value 13.2 fF or higher. For a catching range of 250 Hz with the 3.58 MHz crystal the minimum motional capacitance must have a value of 9 fF. Note: SMD-type crystals do not fulfil these requirements. The actual series capacitance in the application should be C

= 18 pF to account for parasitic capacitances on-chip

and off-chip.

28. Thehue control isactivefor NTSC on thedemodulatedcolour difference signals andforPALplus on the demodulated helper signal.

29. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.

30. This delay is partially caused by the low-pass filter at the sync separator input.

31. The internal luminance signal (signal which is derived from the incoming CVBS or Y/C signals) has a separate gain control setting (controlledby the I2C-bus bits GAI1 and GAI0and with a gain variation between −1 and +2 dB)which can be used to get an optimal input signal amplitude for the feature box.

32. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V (peak-to-peak value).

2000 Sep 25 33

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

33. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a noisedetector and the timeconstant is switched tothe slow mode whentoo much noise ispresentin the signal.In the fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be automatic or overruled by the I2C-bus.

Thecircuit contains avideo identification circuitwhich is independent ofthe first controlloop. This identification circuit can be used to close or open the first control loop when a video signal is present or not present on the input. This enables a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first control loop can be revoked via the I2C-bus.

To prevent the horizontal synchronization being disturbed by anti copy signals such as Macrovision the phase detector is gated during the vertical retrace period from line 11 to 17 (60 Hz signal) or from line 11 to 22 (50 Hz signal) so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately 22 µs. During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 µs so that the effect of noise is reduced to a minimum.

The output current of the phase detector in the various conditions is shown in Table 57.

34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 3 modes of operation:

a) Search mode large window.

This mode is switched on when the circuit is not synchronized or when a non-standard signal [number of lines per frame outside the range between 311 and 314 (50 Hz mode) or between 261 and 264 (60 Hz mode)] is received. In the search mode the divider can be triggered between line 244 and line 361 (approximately

43.3 to 64.5 Hz).

b) Standard mode narrow window.

This mode is switched on whenmore than 15 succeedingvertical sync pulsesare detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window.

c) Standard TV-norm [divider ratio 525 (60 Hz) or 625 (50 Hz)].

When the system is switched to the narrow window a check is performed to establish whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing.

When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.

The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of bit NCIN in subaddress 06.

35. The delay between the positive edge of VA and the positive edge of CLP (≈ negative edge of HA)after VA is 32.0 µs forfield 1 and 0 µsfor field 2. Especiallyfor PALplus signals theregenerated VA pulsesmust have afixedand known phase relation to the undisturbed VA pulses of the incoming video signal. This relationship must remain correct as long as the vertical divider is in the standard mode (indirect sync mode). Therefore the coincidence window used here must be a half line window. With a well defined phase relationship of the generated VA pulses to the generated HA pulses a correct field identification and all the required timing signals referring to a certain line in each frame can be generated externally in the PALplus decoder environment.

36. Pins 19 and 22 are for general purpose outputs that can be used to switch external circuits e.g. sound traps, etc. They are controlled via the I2C-bus by bits OS0 (pin 19) and OS1 (pin 22).

TDA9321H

2000 Sep 25 34

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

Table 55 Coil data for the VIF-PLL demodulator (approximated coil values)

VIF

(MHz)

VCO

(MHz)

(nH)

TOKO SAMPLE NUMBER REMARKS

38.9 77.8 150 P369INAS-159HM ∅ 5 mm; 5 km long; TC = 30 ±100 ppm/°C

45.75 91.5 100 P369INAS-160HM

58.75 117.5 70 P369INAS-161HM

Table 56 Switching conditions of pins SYS1 and SYS2

COLOUR STANDARD SYS1 SYS2 ACTIVE CRYSTAL

PAL-M LOW LOW C PAL-B, G, H, D and I LOW HIGH A NTSC-M HIGH LOW D PAL-N HIGH HIGH B

Table 57 Output current of the phase detector in the various conditions

C-BUS COMMANDS IC CONDITIONS ϕ-1 CURRENT/MODE

VID POC FOA FOB IDENT COIN NOISE SCAN V-RETR GATING MODE

− 0 0 0 yes yes no 180 270 yes

(1)

− 0 0 0 yes yes yes 30 30 yes auto

− 000yes no − 180 270 no auto

− 001yes yes − 30 30 yes slow

− 001yes no − 180 270 no slow

− 0 1 0 yes yes no 180 270 yes fast

− 0 1 0 yes yes yes 30 30 yes slow

−−11 −−−180 270 yes

(1)

00−− no −− 6 6 no OSD

− 1 −−−−− − − − off

auto

fast

Note

1. Only during vertical retrace, pulse width 22 µs and provided that bit EMG = 1 and IVW readout bit = 1. In the other FOA FOB conditions with gating, the pulse width is 5.7 µs and the gating is continuous.

2000 Sep 25 35

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

handbook, full pagewidth

(deg)

010203040

TDA9321H

MLA739

DAC (HEX)

MBC212

Fig.4 Hue control curve.

16 %

for negative modulation

100% = 10% rest carrier

100%

92%

30%

Fig.5 Video output signal.

2000 Sep 25 36

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

handbook, full pagewidth

100

(%)

86 72 58 44 30

TDA9321H

MBC211

646056524844403632221210 26

time (µs)

500

handbook, halfpage

d(g)

(ns)

400

300

200

100

Fig.6 Test signal waveform.

1234

MGR476

f (MHz)

Fig.7 Group delay characteristic.

2000 Sep 25 37

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

handbook, full pagewidth

−13.2 dB

−30 dB

SC CC PC

SC = sound carrier, with respect to top sync level. CC = colour carrier, with respect to top sync level. PC = picture carrier, with respect to top sync level.

Value at 0.92 or 1.1 MHz 20 log

-----------------------------------------------------------V

at 3.58 or 4.4 MHz at 0.92 or 1.1 MHz

−3.2 dB

BLUE

3.6 dB+=

−13.2 dB

−30 dB

SC CC PC

YELLOW

TDA9321H

−10 dB

MBC213

Value at 2.66 or 3.3 MHz 20 log

33.4 MHz

at 3.58 or 4.4 MHz

-----------------------------------------------------------at 2.66 or 3.3 MHz

Fig.8 Input signal conditions.

38.9 MHz

34.5 MHz

ATTENUATOR

TEST

CIRCUIT

SPECTRUM

ANALYZER

gain setting adjusted for blue or yellow

MBC210

Fig.9 Test set-up intermodulation.

2000 Sep 25 38

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TEST AND APPLICATION INFORMATION

RGB1

handbook, full pagewidth

TAGC

SAW

FILTER

CVBS1

AV1

CVBS2

AV2

CVBS/Y3

CVBS/Y4

VIF1 VIF2

3662 37 38 39 40

2 3

16 15 18 17

20 21

23 24

CVBSTXT

CVBSPIP

RGB2

TDA9321H

CVBSCF

COMB FILTER

RI2 GI2 BI2

41 42 43

49 50 51

60 61

2928263234

YCF CCF

YO UO VO

FEATURE

BOX

YIN UIN VIN

H V

D D

RI1 GI1 BI1 BL1

30 31 32 33

28 27 26

TDA9330H

24 23

TDA9321H

RI2 GI2 BI2 BL2RI1 GI1 BI1

35 36 37 38

MGR477

BCL

BLKIN

VDOA

VDOB

EWO

HOUT

HFB

Fig.10 Application diagram.

2000 Sep 25 39

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Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

PACKAGE OUTLINE

QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

51 33

TDA9321H

SOT319-2

(A )

pin 1 index

w M

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

0.25

3.20

OUTLINE

VERSION

SOT319-2 MO-112

0.05

2.90

0.25

2.65

IEC JEDEC EIAJ

0.25

0.14

20.1

19.9

0.50

0.35

0 5 10 mm

(1)

(1) (1)(1)

14.1

13.9

REFERENCES

scale

24.2

23.6

w M

18.2

17.6

v M

1.0

0.6

0.2 0.10.21.95

EUROPEAN

PROJECTION

detail X

1.2

0.8

Zywv θ

1.2

0.8

ISSUE DATE

97-08-01 99-12-27

2000 Sep 25 40

Page 41

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

SOLDERING Introduction to soldering surface mount packages

Thistext gives a very briefinsightto a complex technology. A more in-depth account of soldering ICs can be found in our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011). There is no soldering method that is ideal for all surface

mount IC packages.Wave soldering isnot always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.

Reﬂow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied tothe printed-circuit boardbyscreen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating,soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended forsurfacemount devices (SMDs) orprinted-circuitboards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

TDA9321H

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• Forpackageswith leads on foursides,thefootprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

2000 Sep 25 41

Page 42

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

Suitability of surface mount IC packages for wave and reﬂow soldering methods

SOLDERING METHOD

PACKAGE

WAVE REFLOW

HLQFP, HSQFP, HSOP, SMS not suitable

(3)

PLCC

, SO suitable suitable

(2)

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

(1)

SQFP not suitable suitable SSOP, TSSOP, VSO not recommended

(5)

suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packageswith a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2000 Sep 25 42

Page 43

Philips Semiconductors Preliminary speciﬁcation

I2C-bus controlled TV input processor

DATA SHEET STATUS

Objective speciﬁcation Development This data sheet contains the design target or goal speciﬁcations for

Preliminary speciﬁcation Qualiﬁcation This data sheet contains preliminary data, and supplementary data will be

Product speciﬁcation Production This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DEFINITIONS Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device atthese or at anyotherconditions above those giveninthe Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make norepresentationor warranty that such applications willbe suitable for the specified use without further testing or modification.

PRODUCT

STATUS

DEFINITIONS

product development. Speciﬁcation may change in any manner without notice.

published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expectedto result inpersonal injury. Philips Semiconductorscustomersusingor selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for theuseof any of theseproducts,conveysno licence or title under any patent, copyright, or mask work right to these products,and makes no representationsorwarranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

(1)

TDA9321H

PURCHASE OF PHILIPS I

2000 Sep 25 43

C COMPONENTS

Purchase of Philips I components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the

Page 44

Philips Semiconductors – a w orldwide compan y

Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773

Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087

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Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

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Tel. +49 40 2353 60, Fax. +49 40 2353 6300

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254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415

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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO,

Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001

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Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087

Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. +381 11 3341 299, Fax.+381 11 3342 553

For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 753504/02/pp44 Date of release: 2000 Sep 25 Document order number: 9397 750 07032

Datasheet TDA9321H Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

Sound circuit

Video switches

Chrominance and luminance processing

Colour decoder

RGB switch and matrix

Synchronization circuit

Start-up procedure

LIMITING VALUES

QUALITY SPECIFICATION

CHARACTERISTICS

Vision IF circuit

Sound IF circuit

Colour demodulation part

RGB switch and YUV switch

Horizontal and vertical synchronization

TEST AND APPLICATION INFORMATION

PACKAGE OUTLINE

SOT319-2

DATA SHEET STATUS

DEFINITIONS