Datasheet TDA9177T-N1, TDA9177-N1 Datasheet (Philips)

Product specification
Supersedes data of 1996 Jun 28
File under Integrated Circuits, IC02

1997 Dec 01

INTEGRATED CIRCUITS

TDA9177

YUV transient improvement
processor

DATA SH EET

1997 Dec 01 2

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

FEATURES

• Can be used in 1fH and 2fH applications

• Luminance step improvement

• Line width control

• Smart peaking for detail enhancement

• Embedded feature reduction facility for smart noise

control

• Compensating chrominance delay

• YUV interface

• Two additional pins for access to 6-bit ADC and I2C-bus

• Versatile I

2

C-bus and pin control for user adjustments.

GENERAL DESCRIPTION

The TDA9177 is an I

2

C-bus controlled sharpness
improvement IC with additional inputs for 6-bit
analog-to-digital conversion to facilitate additional
parameter measurement (e.g. ambient light control).
It should preferably be used in front of an RGB video signal
processor with YUV interface.

In combination with the TDA9170, it builds a high
performance and intelligent picture improvement solution.

The sharpness processor provides 1D luminance step
improvement and detail enhancement by smart peaking,
suitable for both 1f

H

and 2fH applications. The TDA9177
can be used as a cost effective alternative to (but also in
combination with) Scan Velocity Modulation (SVM).

An on-board 6-bit Analog-to-Digital Converter (ADC) can
be used for interfacing two analog, low frequency voltage
signals to the I2C-bus.

The supply voltage is 8 V. The TDA9177 is mounted in a
24-pin SDIP envelope.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CC

supply voltage 7.2 8.0 8.8 V

V

i(Y)

luminance input voltage AMS = LOW − 0.315 0.42 V

AMS = HIGH − 1.0 1.33 V

V

i(UV)

UV input voltage −−1.9 V

V

FS(ADC)

full scale ADC input voltage − 0.5V

ref

− V

V

ref

reference voltage 3.90 4.05 4.20 V

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA9177 SDIP24 plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1

1997 Dec 01 3

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MBH229

STEP

IMPROVEMENT

PROCESSOR

SMART

SHARPNESS

CONTROLLER

CONTOUR

PROCESSOR

CLAMPS

DELAY

DELAY DELAY IPTAT

BANDGAP

BLACK

INSERTION

CLAMP

amplitude

selection

UIN

YIN

SANDCASTLE

input

UOUT

VIN VOUT R

ext

VCCGND

SANDCASTLE

DETECTOR

I

2

C-BUS

CONTROLLER

AMS CFS FHS

PIN-TO-I

2

C-BUS

INTERFACE

6-BIT

ADC

contour filter

selection

line frequency

selection

line width

steepness coring peaking

24918 167

5

1

PEAK

11

LWC

STEEP

4

22

14 8 17

SDA

13

ADR

6

SCL

12

ADEXT2

TDA9177

10

ADEXT1

3

COR

2

21 19

V

ref

SNC

YOUT

23

15

20

1997 Dec 01 4

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

PINNING

SYMBOL PIN DESCRIPTION

SANDCASTLE 1 sandcastle input
COR 2 coring level input
ADEXT1 3 ADC input 1
LWC 4 line width control input
YIN 5 luminance input
ADR 6 I

2

C-bus address input
UIN 7 colour U input
CFS 8 contour filter select input
VIN 9 colour V input
ADEXT2 10 ADC input 2
PEAK 11 peaking amplitude input
SCL 12 serial clock input (I

2

C-bus)

SDA 13 serial data input/output

(I

2

C-bus)
AMS 14 amplitude select input
SNC 15 smart noise control input
VOUT 16 colour V output
FHS 17 line frequency select input
UOUT 18 colour U output
GND 19 system ground
YOUT 20 luminance output
V

CC

21 supply voltage
STEEP 22 steepness control input
V

ref

23 reference voltage output
R

ext

24 resistor reference

Fig.2 Pin configuration.

handbook, halfpage

TDA9177

MBH228

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

SANDCASTLE

COR

ADEXT1

ADEXT2

PEAK

SCL

FHS

SDA

AMS

SNC

LWC

YIN

ADR

UIN

CFS

VIN

R

ext

V

ref

V

CC

VOUT

UOUT

GND

YOUT

STEEP

1997 Dec 01 5

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

FUNCTIONAL DESCRIPTION
Y-input selection and amplification

The dynamic range of the luminance input amplifier and
output amplifier can be switched between 0.315 V and

1.0 V typically (excluding sync), either externally
(pin AMS) or by I

2

C-bus (bit AMS of the control register).
Amplitudes outside the corresponding maximum specified
range will be clipped smoothly. The sync part is processed
transparently to the output, independently of the feature
settings. The input is clamped during the HIGH period of
the CLP, defined by the sandcastle reference, and should
be DC-decoupled with an external capacitor. During the
clamp pulse, an artificial black level is inserted in the input
signal to correctly preset the internal circuitry.

The input amplifier drives a delay line of four delay
sections, which form the core of the sharpness
improvement processor.

Sharpness improvement processor

The sharpness improvement processor increases the
slope of large luminance transients of vertical objects and
enhances transients of details in natural scenes by contour
correction. It comprises three main processing units, these
being the step improvement processor, the contour
processor and the smart sharpness controller.

STEP IMPROVEMENT PROCESSOR
The step improvement processor (see Fig.9) comprises

two main functions:

1. the MINMAX generator

2. the MINMAX fader.
The MINMAX generator utilizes 5 taps of an embedded

luminance delay line to calculate the minimum and
maximum envelope of all signals momentarily stored in the
delay line. The MINMAX fader chooses between the
minimum and maximum envelopes, depending on the
polarity of a decision signal derived from the contour
processor. Figures 4, 5 and 6 show some waveforms of
the step improvement processor and illustrate that fast
transients result with this algorithm. The MINMAX
generator also outputs a signal that represents the
momentary envelope of the luminance input signal.
This envelope information is used by the smart sharpness
controller.

Limited line width control (also called aperture control) can
be performed externally (pin 4, LWC) or by I2C-bus
(LW-DAC). Line width control can be used to compensate

for horizontal geometry because of the gamma or
blooming of the spot of the CRT.

T

HE CONTOUR PROCESSOR

The contour processor comprises two contour generators
with different frequency characteristics. The contour
generator generates a second-order derivative of the
incoming luminance signal and is used both as a decision
signal for the step improvement processor and as a
luminance correction signal for the smart sharpness
controller. In the smart sharpness controller, this
correction signal is added to the proper delayed original
luminance input signal, making up the peaking signal for
detail enhancement. The peaking path is allowed to select
either the narrow- or wide-peaked contour generators
either externally (pin 8, CFS) or by I

2

C-bus (bit CFS in the
control register). The step improvement circuitry always
selects the wide-peaked contour filter.

The contour generators utilize 3 taps (narrow band) or
5 taps (broad band) of the embedded luminance delay
lines. Figures 11 and 12 illustrate the normalized
frequency transfer of both the narrow and wide contour
filters.

S

MART SHARPNESS CONTROLLER

The smart sharpness controller (see Fig.10) is a fader
circuit that fades between peaked luminance and
step-improved luminance, defined by the output of a step
discriminating device known as the step detector. It also
contains a variable coring level stage.

The step detector behaves like a band-pass filter, so both
amplitude of the step and its slope add to the detection
criterion. The smart sharpness controller has four user
controls:

1. Steepness control

2. Peaking control

3. Coring level control

4. Smart Noise control.
Control settings can be performed either by the I2C-bus or

externally by pin, depending on the status of the I2C-bus
bit STB.

The steepness setting controls the amount of steepness in
the edge-correction processing path. The peaking setting
controls the amount of contour correction for proper detail
enhancement.

1997 Dec 01 6

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

The envelope signal generated by the step improvement
processor modulates the peaking setting in order to
reduce the amount of peaking for large sine excursions
see Figs 7 and 8.

The coring setting controls the coring level in the peaking
path for rejection of high-frequency noise. All three
settings facilitate reduction of the impact of the sharpness
features, e.g. for noisy luminance signals.

An external noise detector and a user-preferred noise
algorithm are needed to make a fully automatic I2C-bus
controlled smart sharpness control.

An on-board, hard-wired smart sharpness algorithm can
be executed by driving pin SNC with the output of an
external noise detector. This pin, however, is active both in
I2C-bus and pin mode. Figures 13 and 14 illustrate the
impact of the noise control voltage at pin SNC on the user
settings.

Figure 15 shows the relationship between the feature
settings STEEP, COR, PEAK, LWC and their
corresponding pin voltages.

Chrominance compensation

The chrominance delay lines compensate for the delay of
the luminance signal in the step improvement processor,
to ensure a correct colour fit. No delay compensation will
be performed in the chrominance path for line-width
corrections in the luminance path.

Successive approximation ADC

Pins ADEXT1 and ADEXT2 are connected to a 6-bit
successive approximation ADC, via a multiplexer.
The multiplexer toggles between the inputs with each field.

For each field flyback, a conversion is started for either of
the two inputs and the result is stored in the corresponding
bus register, ADEXT1 or ADEXT2.

In this way, any analog, slowly varying signal can be given
access to the I

2

C-bus. If a register access conflict occurs,
the data of that register is made invalid by setting the flag
bit DV (Data Valid) to zero.

I

2

C-bus

At power up, the bit STB (standby) in the control register is
reset, to leave control to the pins. However, the I2C-bus is
at standby and responds if properly addressed. By setting
STB to logic 1, the control of all features is instead left to
the I2C-bus registers. The PDD bit (Power Down Detected)
in the status register is set each time an interruption of the
supply power occurs and is reset only by reading the
status register. A 3-bit identification code can also be read
from the status register, which can be used to
automatically configure the application by software.

The input control registers can be written sequentially by
the I2C-bus by the embedded automatic subaddress
increment feature or by addressing it directly. The output
control functions cannot be addressed separately.
Reading out the output control functions always starts at
subaddress 00 and all subsequent words are read out by
the automatic subaddress increment procedure. The I2C
address is 40H if pin 6 (ADR) is connected to ground and
E0H if pin 6 (ADR) is connected to pin 23 (V

ref

).

I

2

C-bus specification

Slave address

Auto-increment mode available for subaddresses.

A6 A5 A4 A3 A2 A1 A0 R/W

ADR 1 ADR 0 0 0 0 X

1997 Dec 01 7

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Control functions

FUNCTIONS TYPE SUBADDRESS

DATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

Inputs

Control REG 00 X X X X CFS FHS AMS STB
Peaking DAC 01 X X PK5 PK4 PK3 PK2 PK1 PK0
Steepness DAC 02 X X SP5 SP4 SP3 SP2 SP1 SP0
Coring DAC 03 X X CR5 CR4 CR3 CR2 CR1 CR0
Line width DAC 04 X X LW5 LW4 LW3 LW2 LW1 LW0

Outputs

Status REG 00 0 0 0 0 ID2 ID1 ID0 PDD
ADEXT1 (output) REG 01 0 DV AD5 AD4 AD3 AD2 AD1 AD0
ADEXT2 (output) REG 02 0 DV AD5 AD4 AD3 AD2 AD1 AD0

INPUT SIGNALS

Table 1 Address selection

Table 2 Standby

Table 3 Amplitude selection

Table 4 Line frequency selection

Table 5 Contour filter selection

ADR FUNCTION

0I

2

C address is 40H

1I

2

C address is E0H

STB FUNCTION

0 pin mode
1I

2

C-bus mode

AMS FUNCTION

0 0.315 V luminance
1 1.0 V luminance

FHS FUNCTION

01f

H

12f

H

CFS FUNCTION

0 narrow contour filter
1 wide contour filter

Table 6 Peaking amplitude

Table 7 Steepness correction

Table 8 Coring level

Table 9 Line width correction

PK5 to PK0 FUNCTION

000000 0%

111111 100%

SP5 to SP0 FUNCTION

000000 0%

111111 100%

CR5 to CR0 FUNCTION

000000 0%

111111 100%

LW5 to LW0 FUNCTION

000000 0%

111111 100%

1997 Dec 01 8

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

OUTPUT SIGNALS

Table 10 Power Down Detection (PDD)

Table 11 Identification

(version number or derivative type)

PDD FUNCTION

0 no power down detected since last read

action

1 power down detected

ID2 to ID0 FUNCTION

000 TDA9177/N1

Table 12 Data valid of ADC registers

Table 13 Bits AD5 to AD0

DV FUNCTION

0 data not valid because of possible

register access collision

1 data valid

AD5 to AD0 FUNCTION

000000B 0 V

111111B 0.5V

ref

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

QUALITY SPECIFICATION

Quality level in accordance with

“SNW-FQ-611 part E”

.

All pins are protected against ESD by means of internal clamping diodes. The protection circuit meets the specification:

Human body model (100 pF, 1500 Ω): All pins >3000 V.

Machine model (200 pF, 0 Ω): All pins >300 V.
Latch-up:
At an ambient temperature of 70 °C, all pins meet the specification:

I

trigger

> 100 mA or V

pin

> 1.5V

CC(max)

I

trigger

< −100 mA or V

pin

< −0.5V

CC(max)

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

supply voltage −0.5 +8.8 V

V

i

input voltage on any input −0.5 VCC+ 0.5 V

V

o

output voltage of any output −0.5 VCC+ 0.5 V

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −10 +70 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air <59 K/W

1997 Dec 01 9

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

CHARACTERISTICS

V

CC

=8V; R

ref

=10kΩ±2%; T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies

M

AIN SUPPLY V

CC

(PIN 21)

V

CC

supply voltage 7.2 8.0 8.8 V

I

CC

supply current 1fH mode − 40 − mA

2f

H

mode − 45 − mA

REFERENCE SUPPLY V

ref

(PIN 23)

V

ref

reference supply voltage 3.90 4.05 4.20 V

I

L(max)

maximum load current 1.0 −−mA

RESISTOR REFERENCE R

ext

(PIN 24)

V

Rref

resistor supply voltage − 2 − V

R

ref

resistor value − 10 − kΩ

Luminance input/output selection

L

UMINANCE INPUT YIN (PIN 5)

V

i(Y)

luminance input voltage AMS = LOW − 0.315 0.42 V

AMS = HIGH − 1.0 1.33 V

V

i(Yclamp)

luminance input voltage level during
clamping

− 4.0 − V

I

ib(Y)

luminance input bias current no clamp −−0.1 µA
LUMINANCE INPUT VOLTAGE RANGE SELECTION AMS (PIN 14); note 1
V

AMSL

input voltage for low luminance range −−0.5 V
V

AMSH

input voltage for high luminance range 3.5 − 5.5 V

1997 Dec 01 10

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

LUMINANCE OUTPUT YOUT (PIN 20)
V

o(Y) (p-p)

luminance output voltage, peak-to-peak AMS = LOW − 0.315 − V

AMS = HIGH − 1.0 − V

V

o(Yclamp)

luminance output voltage during

clamping

AMS = LOW − 2.35 − V

AMS = HIGH − 2 − V
S/N(Y) luminance output signal-to-noise ratio 52 −−dB
B

Y

luminance bandwidth 1fH mode (−1 dB);

transparent; note 2

5 −−MHz

2f

H

mode (−1 dB);

transparent; note 2

10 −−MHz

E

bl

black level error transparent; note 3 − 0 1.0 %

E

G(n)

nominal gain error transparent − 05%

R

out

output resistance −−150 Ω

I

ob

output bias current 1.3 −−mA

Step improvement

G

ENERAL

t

r(min)

minimum rise time 10% to 90% 1fH mode; note 4 − 20 − ns

2f

H

mode; note 4 − 20 − ns

LINE WIDTH CONTROL

δ

(min)

minimum duty factor 2 MHz − 33 − %

δ

(max)

maximum duty factor 2 MHz − 67 − %

t

sd(max)

maximum step displacement 1fH mode − 140 − ns

2f

H

mode − 70 − ns
LINE-WIDTH CONTROL LWC (PIN 4); note 1
V

i(min)

input voltage for minimum line width −−37.5 %V

ref

V

i(max)

input voltage for maximum line width 87.5 − 137.5 %V

ref

I

bias

input bias current − 0.5 −µA

Contour processing

C

ONTOUR FILTER NARROW-PEAKED

f

pc

peaking centre frequency 1f

H

− 3.57 − MHz

2f

H

− 7.14 − MHz
CONTOUR FILTER WIDE-PEAKED
f

pc1

peaking centre frequency 1f

H

− 4.14 − MHz

2f

H

− 8.28 − MHz
Q

max

maximum contour amplitude at centre
frequency

note 5 − 12 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Dec 01 11

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

CONTOUR FILTER SELECTION CFS (PIN 8); note 1
V

i(ncf)

input voltage for narrow contour filter −−0.5 V

V

i(wcf)

input voltage for wide contour filter 3.5 − 5.5 V

Smart sharpness controller

S

TEP DETECTOR

f

dc

detection centre frequency 1f

H

− 2.13 − MHz

2f

H

− 4.26 − MHz
CORING
Q

smcL

minimum coring level note 6 − 0 − %

Q

smcH

maximum coring level note 6 − 22 − %
CORING LEVEL CONTROL COR (PIN 2); note 1
V

i(min)

input voltage for minimum coring −−37.5 %V

ref

V

i(max)

input voltage for maximum coring 87.5 − 137.5 %V

ref

I

bias

input bias current −−0.5 µA
PEAKING LEVEL CONTROL PEAK (PIN 11); note 1
V

i(min)

input voltage for minimum peaking −−37.5 %V

ref

V

i(max)

input voltage for maximum peaking 87.5 − 137.5 %V

ref

I

bias

input bias current −−0.5 µA
STEEPNESS LEVEL CONTROL STEEP (PIN 22); note 1
V

i(min)

input voltage for minimum steepness −−37.5 %V

ref

V

i(max)

input voltage for maximum steepness 87.5 − 137.5 %V

ref

I

bias

input bias current −−0.5 µA
SMART NOISE CONTROL SNC (PIN 15)
V

nfr

level for no feature reduction − 0.0 − V
V

cfr

level for complete feature reduction − V

ref

− V

I

bias

input bias current −−1.0 µA

Overall group delay performance for luminance

t

d

delay time from input to output 1fH mode − 175 − ns

2f

H

mode − 108 − ns

t

de

delay error contour correction 1fH mode; note 7 − 010ns

2f

H

mode; note 7 − 05ns

t

de1

delay error step correction 1fH mode; note 7 − 010ns
t

de2

delay error step correction 2fH mode − 05ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Dec 01 12

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

DELAY TIME SELECTION FHS (PIN 17); note 1
V

i1fH

input voltage for 1f

H

−−0.5 V

V

i2fH

input voltage for 2f

H

3.5 − 5.5 V

Colour difference processing

C

OLOUR DIFFERENCE INPUTS UIN AND VIN (PINS 7 AND 9)

V

iUIN(p-p)

input voltage range UIN, peak-to-peak 1.9 −−V
V

iVIN(p-p)

input voltage range VIN, peak-to-peak 1.9 −−V
I

bias

input bias current UIN, VIN no clamp −−0.1 µA
V

cl

voltage level during clamping − 4.0 − V
COLOUR DIFFERENCE OUTPUTS UOUT AND, VOUT (PINS 18 AND 16)
V

o(cl)

output voltage level during clamping − 3.2 − V
G gain − 1.0 −
E

off

offset error transparent − 01%
E

G

gain error transparent − 05%
E

G(UV)

UV gain tracking error transparent − 01%
B bandwidth 1f

H

7 −−MHz

2f

H

7 −−MHz

t

d

delay time 1f

H

− 175 − ns

2f

H

− 108 − ns

R

out

output resistance −−150 Ω
I

ob

output bias current 0.5 −−mA

Successive Approximation ADC

ADEXT1

AND ADEXT2 (PINS 3 AND 10)

V

FS

full scale input voltage range with respect to GND − 2.0 − V
I

ib

input bias current −−1µA

data path − 6 − bit
DLE differential linearity error −−1 LSB
ILE integral linearity error −−1 LSB
f

con

conversion frequency each channel − 0.5f

V

− Hz

Q

adt

conversion time (video lines) each channel − 8 − lines

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Dec 01 13

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Notes

1. This selection is only valid when the standby bit STB is not set.

2. In transparent mode i.e. no step improvement and no peaking, the bandwidth of the luminance path for which the
group delay is constant is 7 MHz in 1fH mode and 14 MHz in 2fH mode. However, as the circuit uses all-pass filters,
ringing on the output signal may occur if the bandwidth of the input signal is larger than 7 MHz in 1fH mode or 14 MHz
in 2fH mode. As the step improvement circuit adds harmonics to the luminance signal, the bandwidth of the output
signal is much larger than 14 MHz.

3. The black level error that may occur will mainly be caused by inaccuracies in the internal clamping circuit. This
internal clamping circuit is activated during 70% of the duration of the burst key pulse on the sandcastle signal.
Integration of the ‘ramp shaped’ black level error during the full duration of the burst key pulse will reduce the black
level error to less than 1%.

4. Peaking set to minimum. Input signal is a sine wave with the nominal peak-to-peak amplitude corresponding to the
selected input range.

5. The contour signal cannot be measured separately from the luminance input signal. The contour signal is also
processed by the smart noise controller. The frequency transfer in the peaking mode of the luminance signal can be
derived from the frequency transfer of the selected contour signal, taking into account the summation of the contour
signal and the luminance input signal. The frequency transfer is most easily measured by sine excitation with a
relatively small signal amplitude of 10% of the selected dynamic range of the luminance input, to avoid interaction
with the step detector.

6. The coring level refers to the internally selected contour signal. It is dependent on the contour filter selected and is
specified for the corresponding peaking centre frequency. The coring level can not be measured explicitly at the
luminance output from a big step or sine excitation, because of its interaction with the step detector.

7. Contour correction and step improvement delays are internal delays and cannot be measured in a straightforward
way. Contour correction delay mismatch results in asymmetrical ‘ears’ with respect to the centre of the transient.
Step improvement correction delay mismatch affects the symmetry of the line width control.

Timing

S

ANDCASTLE INPUT SANDCASTLE (PIN 1)

V

scbn

detection level for blank no clamping 1.25 1.5 1.75 V

V

scbc

detection level for blank with clamping and w.r.t. top

level sandcastle pulse

−−0.6 − V

t

scnV

input blanking width for no V-sync −−15 µs

t

scV

input blanking width for V-sync 35 −−µs

V

bkvar

ripple on sandcastle burst key level −−0.4 V

Overall output group delay performance

t

dm(YUV)

delay of matching YUV 1f

H

− 010ns

2f

H

− 05ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1997 Dec 01 14

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Figures 3 to 8 show the excitation and response of the
TDA9177 sharpness improvement processor.
The excitation shown in Fig.3 is a 2T-pulse, followed by a
step function. Because the TDA9177 can handle both 1f

H

and 2fH signals, figures illustrating both situations could
have been provided. However, as the difference between
these two modes (with respect to the TDA9177) is that the
time scale of a 2fH response diagram is half that of a 1f

H

response diagram under equal conditions, only the 1f

H

figures are shown.
Figure 4 shows that the step improvement processor does

not affect small amplitudes. Large transients, however,
acquire steeper edges.

Figures 5 and 6 show that the width of the signal
processed by the step improvement processor can be
modified by the Line Width Control pin LWC (or DACLW).
Figure 7 shows that the contour processor does not affect
large transients, but works exclusively on small signals,
e.g. details in a video signal.

Figure 8 shows the combination of smart peaking and the
step improvement processor; small signals will be affected
by the contour processor, while large transients will be
modified by the step improvement processor.

1997 Dec 01 15

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.3 Excitation signals: 90% and 30% of nominal

amplitude 2T-pulse and step function.

(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.

handbook, halfpage

0 0.5

1000

800

200

0

400

600

MBH230

1.0

(1)

(2)

1.5 2.0

t (µs)

input

signal

(mV)

Fig.4 Response signals for maximum step

improvement, no peaking and nominal line
width.

handbook, halfpage

0 0.5

1000

800

200

0

400

600

MBH231

1.0 1.5 2.0

t (µs)

(1)

(2)

V

o

(mV)

(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.

Fig.5 Response signals for maximum step

improvement, no peaking and minimum line
width.

handbook, halfpage

0 0.5

1000

800

200

0

400

600

1.0 1.5 2.0

t (µs)

V

o

(mV)

(1)

(2)

MBH232

(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.

Fig.6 Response signals for maximum step

improvement, no peaking and maximum
line width.

handbook, halfpage

0 0.5

1000

800

200

0

400

600

1.0 1.5 2.0

t (µs)

V

o

(mV)

(1)

(2)

MBH233

(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.

1997 Dec 01 16

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.7 Response signals for no step improvement,

maximum peaking and 0% coring.

handbook, halfpage

0 0.5

1400

1000

200

−200

600

1.0 1.5 2.0

t (µs)

V

o

(mV)

(1)

(2)

MBH234

(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.

Fig.8 Response signals for maximum step

improvement, nominal line width, maximum
peaking and 0% coring.

handbook, halfpage

0 0.5

1400

1000

200

−200

600

1.0 1.5 2.0

t (µs)

V

o

(mV)

(1)

(2)

MBH235

(1) 90% of nominal amplitude.
(2) 30% of nominal amplitude.

Fig.9 Block diagram of the step improvement processor.

handbook, full pagewidth

MBH236

MINMAX

SELECTOR

MINMAX

Y

envelope

Y

STEP

CLAMPS

FADER

line width

control

DELAY

YIN

1997 Dec 01 17

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.10 Block diagram of the smart sharpness controller.

handbook, full pagewidth

MBH237

STEP

DETECTOR

FADERCORING

Y

envelope

Y

STEP

Y

contour

Y

STEP

Y

c

delay cells

coring control

peaking

control

smart
noise

steepness

control

Fig.11 Frequency transfers narrow contour filter.

handbook, full pagewidth

0

100

MBH238

10

4

10

5

10

6

10

7

f (Hz)

contour

(%)

10

8

20

40

60

80

(1) (2)

(1) 1fH mode.
(2) 2fH mode.

1997 Dec 01 18

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.12 Frequency transfers wide contour filter.

handbook, full pagewidth

0

100

MBH239

10

4

10

5

10

6

10

7

f (Hz)

contour

(%)

10

8

20

40

60

80

(1) (2)

(1) 1fH mode.
(2) 2fH mode.

Fig.13 Relative decrease of steepness level as a function of voltage at pin SNC starting from four different

steepness level presets.

handbook, halfpage

0

(%)

25 50 100

V

ref

(%)

100

50

0

MBH240

75

75

25

1997 Dec 01 19

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.14 Relative increase of coring level as a function of voltage at pin SNC starting from four different coring level

presets.

handbook, halfpage

0

(%)

25 50 100

V

ref

(%)

100

80

60

40

20

0

MBH241

75

Fig.15 Feature setting control as a function of the pin voltage for peaking, coring, steepness and line width.

handbook, halfpage

37.5

transfer

(%)

50.0 62.5 87.5
V

ref

(%)

100

50

0

MBH242

75

1997 Dec 01 20

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

INTERNAL CIRCUITRY

Fig.16 Simplified circuit diagram pin 1.

handbook, halfpage

MBH244

275 Ω

SANDCASTLE

1

Fig.17 Simplified circuit diagram pin 2.

2

handbook, halfpage

MBH245

275 Ω

COR

Fig.18 Simplified circuit diagram pin 3.

handbook, halfpage

275 Ω

ADEXT1

MBH246

100 kΩ

3

Fig.19 Simplified circuit diagram pin 4.

handbook, halfpage

MBH247

275 Ω

LWC

4

Fig.20 Simplified circuit diagram pin 5.

handbook, halfpage

MBH248

275 Ω

YIN

5

Fig.21 Simplified circuit diagram pin 6.

6

handbook, halfpage

MBH249

275 Ω

ADR

1997 Dec 01 21

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.22 Simplified circuit diagram pin 7.

handbook, halfpage

MBH250

275 Ω
275 Ω

UIN

7

Fig.23 Simplified circuit diagram pin 8.

8

handbook, halfpage

MBH251

275 Ω 900 Ω

1 MΩ

CFS

Fig.24 Simplified circuit diagram pin 9.

9

handbook, halfpage

MBH252

275 Ω
275 Ω

VIN

Fig.25 Simplified circuit diagram pin 10.

handbook, halfpage

275 Ω

ADEXT2

MBH253

100 kΩ900 Ω

10

Fig.26 Simplified circuit diagram pin 11.

dbook, halfpage

MBH254

275 Ω

PEAK

11

Fig.27 Simplified circuit diagram pin 12.

12

handbook, halfpage

MBH255

275 Ω

SCL

1997 Dec 01 22

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.28 Simplified circuit diagram pin 13.

13

handbook, halfpage

MBH256

275 Ω

SDA

Fig.29 Simplified circuit diagram pin 14.

14

handbook, halfpage

MBH257

275 Ω 900 Ω

1 MΩ

AMS

Fig.30 Simplified circuit diagram pin 15.

15

handbook, halfpage

275 Ω

SNC

MBH258

Fig.31 Simplified circuit diagram pin 16.

16

handbook, halfpage

100 Ω

0.5 mA

VOUT

MBH259

Fig.32 Simplified circuit diagram pin 17.

17

handbook, halfpage

MBH260

275 Ω 900 Ω

1 MΩ

FHS

Fig.33 Simplified circuit diagram pin 18.

handbook, halfpage

100 Ω

0.5 mA

UOUT

MBH261

18

1997 Dec 01 23

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

Fig.34 Simplified circuit diagram pin 19.

handbook, halfpage

MBH262

GND

19

Fig.35 Simplified circuit diagram pin 20.

20

handbook, halfpage

100 Ω

0.5 mA

YOUT

MBH263

Fig.36 Simplified circuit diagram pin 21.

21

handbook, halfpage

MBH264

V

CC

Fig.37 Simplified circuit diagram pin 22.

22

handbook, halfpage

MBH265

275 Ω

STEEP

Fig.38 Simplified circuit diagram pin 23.

23

handbook, halfpage

100 Ω

21 kΩ

V

ref

MBH266

Fig.39 Simplified circuit diagram pin 24.

handbook, halfpage

24

100 Ω

100 Ω

R

ext

MBH267

1997 Dec 01 24

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

APPLICATION INFORMATION

To benefit optimally from its picture-sharpening
capabilities, the TDA9177 should be positioned as the last
part of the YUV-chain.

Feature reduction as a function of the noise contents of the
picture can easily be realized in hardware by using a Noise
Detector. Smart Noise Control (SNC) can be tailor-made
for each application, by means of controlling the peaking
and the steepness values by software (I2C-bus control).

Whenever I

2

C-bus control is not feasible, the embedded
smart sharpness algorithm can be executed by driving pin
SNC with the output of a noise detector. In this concept,
additional post-processing of the noise detector output can
easily be realized with external components.

Figure 40 shows an application example in which the
TDA9177 is bus controlled, with the I2C-bus address at
40H. Furthermore, the Smart Noise Control pin (SNC;
pin 15) is not used in the example shown.

Fig.40 Application diagram.

handbook, full pagewidth

MBH243

24

8 V

0 V

23 22 21 20 19

TDA9177

YOUT UOUT VOUT

18 17 16 15 14 13

1 2 3 4 5 6 7 8 9 10 11 12

100

nF

YIN

100

nF

UIN

10
nF

VIN SCL SDA

10
nF

sandcastle

100

µF

10

kΩ

100

Ω

100

Ω

1997 Dec 01 25

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

PACKAGE OUTLINE

UNIT b

1

cEe M

H

L

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

DIMENSIONS (mm are the original dimensions)

SOT234-1

92-11-17
95-02-04

b

max.

w

M

E

e

1

1.3

0.8

0.53

0.40

0.32

0.23

22.3

21.4

9.1

8.7

3.2

2.8

0.181.778 10.16

10.7

10.2

12.2

10.5

1.6

4.7 0.51 3.8

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

e

D

A

2

Z

24

1

13

12

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1) (1)

D

(1)

Z

A

max.

12

A

min.

A

max.

SDIP24: plastic shrink dual in-line package; 24 leads (400 mil)

SOT234-1

1997 Dec 01 26

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

1997 Dec 01 27

Philips Semiconductors Product specification

YUV transient improvement processor TDA9177

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1997 SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Printed in The Netherlands 547047/1200/02/pp28 Date of release: 1997 Dec 01 Document order number: 9397 750 03053