Datasheet tda8763a DATASHEETS (Philips)

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

TDA8763A

10-bit high-speed low-power ADC

Preliminary speciﬁcation File under Integrated Circuits, IC02

1996 Feb 13

Page 2

Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

FEATURES

• 10-bit resolution

• Sampling rate up to 50 MHz

• DC sampling allowed

• One clock cycle conversion only

• High signal-to-noise ratio over a large analog input

frequency range (9.3 effective bits at 4.43 MHz full-scale input at f

• No missing codes guaranteed

• In range (IR) CMOS output

• CMOS compatible digital inputs

• 3 to 5 V CMOS digital outputs

• Low-level AC clock input signal allowed

• External reference voltage regulator

• Power dissipation only 175 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

= 40 MHz)

clk

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Radar pulse analysis

• Transient signal analysis

• High energy physics research

•Σ∆ modulators

• Medical imaging.

GENERAL DESCRIPTION

The TDA8763A is a 10-bit high-speed low-power analog-to-digital converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 50 MHz. All digital inputs and outputs are CMOS compatible, although a low-level sine wave clock input signal is allowed.

The device requires an external source to drive its reference ladder. If the application requires that the reference is driven via internal sources the recommendation is to use the TDA8763.

ORDERING INFORMATION

TYPE

NUMBER

TDA8763AM/3 SSOP28 TDA8763AM/4 SSOP28 SOT341-1 40 TDA8763AM/5 SSOP28 SOT341-1 50

NAME DESCRIPTION VERSION

plastic shrink small outline package; 28 leads; body width 5.3 mm

PACKAGE

SAMPLING

FREQUENCY (MHz)

SOT341-1 30

1996 Feb 13 2

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CCA

CCD

CCO

CCA

CCD

CCO

INL integral non-linearity f DNL differential non-linearity f AINL AC integral non-linearity note 1 −±1.0 ±2.0 LSB f

clk(max)

tot

analog supply voltage 4.75 5.0 5.25 V digital supply voltage 4.75 5.0 5.25 V output stages supply voltage 3.0 3.3 5.25 V analog supply current − 18 tbf mA digital supply current − 14 tbf mA output stages supply current f

= 40 MHz; ramp input − 4 tbf mA

clk

= 40 MHz; ramp input −±0.8 tbf LSB

clk

= 40 MHz; ramp input −±0.5 ±0.9 LSB

clk

maximum clock frequency

TDA8763AM/3 30 −−MHz TDA8763AM/4 40 −−MHz TDA8763AM/5 50 −−MHz

total power dissipation f

= 40 MHz; ramp input − 175 tbf mW

clk

Note

1. Full-scale sine wave (f

= 4.43 MHz; f

= 40 MHz).

clk

1996 Feb 13 3

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

BLOCK DIAGRAM

ook, full pagewidth

analog

voltage input

CCA

LAD

ANALOG -TO - DIGITAL

CONVERTER

4 AGND

12 DGND2

CLK

CLOCK DRIVER

LATCHES

IN RANGE LATCH

CCD2

TDA8763A

CMOS OUTPUT

OGND

OE 10

CMOS

OUTPUTS

27 DGND1

25 24 23 22 21

20 D4 19 18 17 D1

16 D0

MBG913

MSB

D8 D7 D6 D5

data outputs D3 D2

LSB

CCO



IR output



CCD1

analog ground digital ground digital ground

Fig.1 Block diagram.

1996 Feb 13 4

output ground

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input TC 2 two’s complement input (active LOW) V

CCA

AGND 4 analog ground n.c. 5 not connected V

OE 10 output enable input (CMOS level

CCD2

DGND2 12 digital ground 2 V

CCO

OGND 14 output ground n.c. 15 not connected D0 16 data output; bit 0 (LSB) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 D4 20 data output; bit 4 D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (MSB) IR 26 in range data output DGND1 27 digital ground 1 V

CCD1

3 analog supply voltage (+5 V)

6 reference voltage BOTTOM input 7 reference voltage MIDDLE 8 analog input voltage 9 reference voltage TOP input

input, active LOW)

11 digital supply voltage 2 (+5 V)

13 supply voltage for output stages

(+3 to 5 V)

28 digital supply voltage 1 (+5 V)

handbook, halfpage

CLK

CCA

AGND

n.c.

CCD2

DGND2

CCO

OGND

10 11 12 13

TDA8763A

8 9

MBG914

Fig.2 Pin configuration.

1514

CCD1 DGND1 IR

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 n.c.

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

CCA

CCD

CCO

∆V

clk(p-p)

stg

amb

analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage difference

V V V

CCA CCA CCD

− V

CCD CCO DDO

−1.0 +1.0 V

−1.0 +4.0 V

input voltage referenced to AGND −0.3 +7.0 V AC input voltage for switching (peak-to-peak value) referenced to DGND − V

CCD

V output current − 10 mA storage temperature −55 +150 °C operating ambient temperature −40 +85 °C junction temperature − +150 °C

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

CCO

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

th j-a

thermal resistance from junction to ambient in free air 110 K/W

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

CHARACTERISTICS

CCA=V3

AGND and DGND shorted together; T V

CCO

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply

CCA

CCD1

CCD2

CCO

∆V

CCA

CCD

CCO

Inputs

to V4= 4.75 to 5.25 V; V

= 3.3 V; V

i(p-p)

analog supply voltage 4.75 5.0 5.25 V digital supply voltage 1 4.75 5.0 5.25 V digital supply voltage 2 4.75 5.0 5.25 V output stages supply voltage 3.0 3.3 5.25 V

supply voltage difference

CCA

CCD

analog supply current − 18 tbf mA digital supply current − 14 tbf mA output stages supply current f

CCD=V11

=0to+70°C; typical values measured at V

amb

= 2.0 V; CL= 15 pF and T

− V

CCD

− V

CCO

− V

CCO

to V12and V28to V27= 4.75 to 5.25 V; V

=25°C; unless otherwise speciﬁed.

amb

CCO=V13 CCA=VCCD

to V14= 3.0 to 5.25 V;

= 5 V and

−0.20 − +0.20 V

−0.20 − +2.25 V

= 40 MHz; ramp input − 4 tbf mA

clk

LOCK INPUT CLK (REFERENCED TO DGND); note 1

C V

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V LOW level input current V HIGH level input current V input impedance f input capacitance f

= 0.3V

clk

= 0.7V

clk

=40MHz − 2 − kΩ

clk

=40MHz − 2 − pF

clk

INPUTS OE AND TC (REFERENCED TO DGND); see Table 2 V

(ANALOG INPUT VOLTAGE REFERENCED TO AGND)

LOW level input voltage 0 − 0.3V HIGH level input voltage 0.7V LOW level input current VIL= 0.3V HIGH level input current VIH= 0.7V

LOW level input current VI=VRB= 1.3 V − 0 −µA HIGH level input current VI=VRT= 3.67 V − 35 −µA input impedance fi= 4.43 MHz − 8 − kΩ input capacitance fi= 4.43 MHz − 5 − pF

CCD CCD

CCD

V V

CCD

− V

CCD

−10+1 µA

− 210 µA

V V

CCD

− V

CCD

−1 −− µA

−−1 µA

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder using the internal voltage regulator; see Table 1

V V V

ref

R TC

V V V

RB RT diff

LAD

RLAD

osB osT i(p-p)

reference voltage BOTTOM 1.2 1.3 2.45 V reference voltage TOP 3.0 3.67 VCA− 0.8 V differential reference voltage

VRT− V

1.8 2.37 3.0 V

reference current VRT− VRB= 2.37 V − 9.7 − mA resistor ladder − 245 −Ω temperature coefﬁcient of the

resistor ladder

− 1860 − ppm

− 456 − mΩ/K

offset voltage BOTTOM note2 − 175 − mV offset voltage TOP note 2 − 175 − mV analog input voltage

note 3 1.5 2.02 2.5 V

(peak-to-peak value)

Outputs

IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)

D V

LOW level output voltage IOL= 1 mA 0 − 0.5 V HIGH level output voltage IOH= −1mA V output current in 3-state mode 0.5 V < VO<V

CCO

−0.5 − V

CCO

−20 − +20 µA

Switching characteristics

LOCK INPUT CLK; see Fig.4; note 1

C f

clk(max)

maximum clock frequency

TDA8763AM/3 30 −− MHz TDA8763AM/4 40 −− MHz TDA8763AM/5 50 −− MHz

CPH

CPL

clock pulse width HIGH 8 −− ns clock pulse width LOW 8 −− ns

Analog signal processing

INEARITY

L INL integral non-linearity f

DNL differential non-linearity f

= 40 MHz; ramp input −±0.8 tbf LSB

clk

= 40 MHz; ramp input −±0.5 ±0.9 LSB

clk

AINL AC integral non-linearity note 4 −±1.0 ±2.0 LSB OFER offset error middle code;

= 1.3 V; VRT= 3.67 V

GER gain error (from device to device)

using external reference voltage

= 1.3 V;

VRT= 3.67 V; note 5

−±1− LSB

−±0.1 − %

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BANDWIDTH (f

= 40 MHz)

clk

B analog bandwidth full-scale sine wave;

note 6 75% full-scale sine wave;

note 6 small signal at mid-scale;

= ±10 LSB at

code 512; note 6

STLH

analog input settling time LOW-to-HIGH

STHL

analog input settling time

HIGH-to-LOW HARMONICS (f h

fundamental harmonics

=40MHZ); see Figs 7 and 8

clk

full-scale square wave; see Fig.6; note 7

fi= 4.43 MHz −−0dB

(full scale) h

all

harmonics (full scale);

fi= 4.43 MHz

all components

second harmonics −−73 tbf dB third harmonics −−70 tbf dB

THD total harmonic distortion f

= 4.43 MHz −−68 − dB

SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 8 S/N signal-to-noise ratio (full scale) without harmonics;

= 40 MHz;

clk

fi= 4.43 MHz EFFECTIVE BITS; see Figs 7 and 8; note 8 EB effective bits

TDA8763AM/3 f

=30MHz

clk

= 4.43 MHz − 9.4 − bits

= 7.5 MHz − 9.1 − bits

EB effective bits

TDA8763AM/4 f

=40MHz

clk

= 4.43 MHz − 9.3 − bits

= 7.5 MHz − 9.0 − bits

EB effective bits

TDA8763AM/5 f

=50MHz

clk

= 4.43 MHz − 9.2 − bits

= 7.5 MHz − 8.9 − bits

TWO-TONE; note 9 TTIR two-tone intermodulation

=40MHz −−68 − dB

clk

rejection

− 10 − MHz

− 14 − MHz

− 350 − MHz

− 2.0 tbf ns

− 2.5 tbf ns

56 58 − dB

1996 Feb 13 9

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

IT ERROR RATE

B BER bit error rate f

DIFFERENTIAL GAIN; note 10 G

diff

differential gain f

DIFFERENTIAL PHASE; note 10

diff

differential phase f

= 50 MHz;

clk

fi= 4.43 MHz;

VI= ±16 LSB at code 512

= 40 MHz;

clk

PAL modulated ramp

= 40 MHz;

clk

PAL modulated ramp

− 10

− 0.5 − %

− 0.3 − deg

−13

− times/

sample

Timing (f

= 40 MHz; CL= 15 pF); see Fig.4; note 11

clk

sampling delay time −−2ns output hold time 5 −− ns output delay time V

= 4.75 V − 13 16 ns

CCO

= 3.15 V − 16 19 ns

CCO

digital output load capacitance − 15 40 pF 3-state output delay times; see Fig.5 t

dZH

dZL

dHZ

dLZ

enable HIGH − 14 18 ns

enable LOW − 16 20 ns

disable HIGH − 16 20 ns

disable LOW − 14 18 ns

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns.

2. Analog input voltages producing code 0 up to and including code 1023: a) V

b) V

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

osB

the reference voltage BOTTOM (VRB) at T

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

osT

produces data outputs equal to code 1023 at T

amb

=25°C.

amb

1996 Feb 13 10

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins V

a) The current flowing into the resistor ladder is and the full-scale input range at the converter,

b) Since R

4. Full-scale sine wave (f

GER

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data.

8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

9. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.

10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter.

11. Output data acquisition: the output data is available after the maximum delay time of t recommended to have the lowest possible output load and/or to use V

and VRT via offset resistors ROB and ROT as shown in Fig.3.

VRTVRB–

----------------------------------------- -

OBRLROT

== V(

to cover code 0 to code 1023, is

, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio

----------------------------------------- R

OBRLROT

will be kept reasonably constant from device to device. Consequently variation of the output

RLIL×

----------------------------------------- R

codes at a given input voltage depends mainly on the difference V

OBRLROT

× VRB– )+ 0.˙852 V(

− VRB and its variation with temperature and

RTVRB

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized.

= 4.43 MHz; f

–()2V–

1023V0

-----------------------------------------------2V

100×=

= 40 MHz).

clk

CCO

at 5 V.

. For 50 MSPS version it is

)–×=

handbook, halfpage

Fig.3 Explanation of note 3.

1996 Feb 13 11

code 1023

LAD

MGD281

code 0

Page 12

Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

Table 1 Output coding and input voltage (typical values; referenced to AGND, VRB= 1.3 V, VRT= 3.67 V)

STEP V

i(p-p)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

U/F <1.475 0 0 0 0 0 0000001000000000

0 1.475 1 0 0 0 0 0000001000000000 1 . 100000000011000000001

. . .....................

1022 . 111111111100111111110 1023 3.495 1 1 1 1 1 1111110111111111

O/F >3.495 0 1 1 1 1 1111110111111111

Table 2 Mode selection

TC OE D9 to D0 IR

X 1 high impedance high impedance

0 0 active; two’s complement active 1 0 active; binary active

BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS

handbook, full pagewidth

CLK

DATA D0 to D9

sample N

DATA

N - 2

CPH

CPL

sample N + 1

DATA

N - 1

Fig.4 Timing diagram.

sample N + 2

DATA

N + 1

MBG916

CCO

50% 0 V

CCO

50% 0 V

1996 Feb 13 12

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

handbook, full pagewidth

fOE= 100kHz.

output data

CCD

LOW

dLZ

10%

TDA8763A

HIGH

50%

LOW

CCD

dZH

50%

TEST

dLZ

dZL

dHZ

dZH

CCD

DGND DGND

MGD262

dHZ

HIGH

dZL

50%

3.3 kΩ

15 pF

90%

Fig.5 Timing diagram and test conditions of 3-state output delay time.

2 ns

STHL

50%

0.5 ns

code 1023

code 0

CLK

MBE566

STLH

50%

2 ns

50%

0.5 ns

Fig.6 Analog input settling-time diagram.

1996 Feb 13 13

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

handbook, full pagewidth

amplitude

(dB)

100

120

0 2.50 5.00

Effective bits: 9.38; THD= −68.52 dB.

Harmonic levels (dB): 2nd = −75.42; 3rd = −76.62; 4th = −79.05; 5th = −72.33; 6th = −77.17.

Fig.7 Typical Fast Fourier Transform (f

12.57.50 10.0 15 17.5 20.0

= 40 MHz; fi= 4.43 MHz).

clk

MBG919

f (MHz)

handbook, full pagewidth

amplitude

(dB)

100

120

0 2.50 5.00

Effective bits: 8.67; THD = −57.38 dB.

Harmonic levels (dB): 2nd = −64.65; 3rd = −58.83; 4th = −76.15; 5th = −68.49; 6th = −78.57.

Fig.8 Typical Fast Fourier Transform (f

12.57.50 10.0 15.0 17.5 20.0

= 40 MHz; fi= 10 MHz).

clk

MBG920

f (MHz)

1996 Feb 13 14

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

INTERNAL PIN CONFIGURATIONS

handbook, halfpage

Fig.9 CMOS data and in range outputs.

MBG915

CCO

D9 to D0

OGND

handbook, halfpage

CCA

AGND

MGC040 - 1

Fig.10 Analog inputs.

handbook, halfpage



(TC)

OGND

CCO

OE

MBE557

Fig.11 OE (TC) input.

1996 Feb 13 15

handbook, halfpage

AGND

CCA

Fig.12 VRB, VRM and VRT.

LAD

MGD232

Page 16

Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

handbook, halfpage

CCD

CLK

DGND

Fig.13 CLK input.

1/2V

CCD

MBE559 - 1

1996 Feb 13 16

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

APPLICATION INFORMATION

handbook, halfpage

100 nF

AGND

100 nF

AGND

CLK

CCA

AGND1

n.c.

CCD2

DGND2

(1)

TDA8763A

(1)

CCD1

DGND1

CCO

OGND

The analog and digital supplies should be separated and decoupled.

The external voltage regulator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the

reference ladder voltages can be derived from a well regulated V

(1) VRB, VRM and VRT are decoupled to AGND.

(2) Pin 15 should be connected to DGND in order to prevent noise influence.

supply through a resistor bridge and a decoupled capacitor.

CCA

MBG918

n.c.

(2)

Fig.14 Application diagram.

1996 Feb 13 17

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Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

28 15

pin 1 index

SOT341-1

(A )

v M

114

w M

DIMENSIONS (mm are the original dimensions)

UNIT A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

max.

2.0

OUTLINE VERSION

SOT341-1 MO-150AH

0.21

0.05

A2A

1.80

1.65

IEC JEDEC EIAJ

0.25

0.38

0.25

0.20

0.09

0 2.5 5 mm

scale

(1)E(1) (1)

10.4

5.4

10.0

REFERENCES

0.65 1.25

5.2

1996 Feb 13 18

detail X

eHELLpQZywv θ

7.9

7.6

1.03

0.63

0.9

0.7

EUROPEAN

PROJECTION

0.13 0.10.2

1.1

0.7

ISSUE DATE

93-09-08 95-02-04

Page 19

Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

Reﬂow soldering

Reflow soldering techniques are suitable for all SSOP packages.

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

Wave soldering

Wave soldering isnot recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.

(order code 9398 652 90011).

If wave soldering cannot be avoided, the following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave) soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate solder thieves at the downstream end.

Even with these conditions, only consider wave soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1).

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

1996 Feb 13 19

Page 20

Philips Semiconductors Preliminary speciﬁcation

10-bit high-speed low-power ADC TDA8763A

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1996 Feb 13 20