Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA8760
10-bit high-speed analog-to-digital
converter
Product specification
Supersedes data of April 1994
File under Integrated Circuits, IC02
1996 Sep 12
Page 2
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
FEATURES
• 10-bit resolution
• Sampling rate up to 40 MHz
• Total Harmonic Distortion (THD): −65 dB at 4.43 MHz
full-scale and a 40 MHz clock frequency
• High signal-to-noise ratio over a large analog input
frequency range (8.8 effective bits at 10 MHz full-scale
input at a 40 MHz clock frequency)
• +5 V power supplies
• Binary or two’s complement 3-state TTL outputs
• In-range 3-state TTL output
• TTL compatible digital inputs
• LOW-level AC clock input signal allowed
• Power dissipation 850 mW (typical)
• Low analog input capacitance (typ. 4.5 pF), no buffer
amplifier required
• No external sample-and-hold circuit required
• Analog Input; single or differential
• External amplitude range control
• Voltage controlled regulator included.
TDA8760
APPLICATIONS
• High-speed analog-to-digital conversion for
– Video signal digitizing
– High Definition TV (HDTV)
– Digital video broadcasting (satellite and cable)
– Transient signal analysis
– High energy physics research
– Sigma-delta (SD) modulators
– Medical imaging
– Radar pulse digitizing.
GENERAL DESCRIPTION
The TDA8760 is a monolithic bipolar 10-bit
Analog-to-Digital Converter (ADC) for video or other
applications. It converts the analog input signal into 10-bit
binary coded digital words at a maximum sampling rate of
40 MHz. All digital inputs and outputs are TTL compatible.
However, a sine wave clock input signal is allowed.
1996 Sep 12 2
Page 3
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ILE DC integral linearity error f
DLE DC differential linearity error f
AILE AC integral linearity error f
f
clk(max)
P
tot
T
amb
analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 4.75 5.0 5.25 V
analog supply current − 95 100 mA
digital supply current − 40 45 mA
output supply current − 35 40 mA
= 4 MHz −±1.0 ±2.0 LSB
clk
= 4 MHz −±0.6 ±1.0 LSB
clk
= 40 MHz;
clk
−±1.2 ±2.0 LSB
fi= 4.43 MHz
maximum clock frequency
TDA8760K/2 20 −−MHz
TDA8760K/4 40 −−MHz
total power dissipation − 850 970 mW
operating ambient temperature 0 − +70 °C
ORDERING INFORMATION
TYPE
NUMBER
TDA8760K/2
TDA8760K/4 40
NAME DESCRIPTION VERSION
PLCC44 plastic leaded chip carrier; 44 leads SOT187-2
PACKAGE SAMPLING
FREQUENCY
(MHz)
20
1996 Sep 12 3
Page 4
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
BLOCK DIAGRAM
OGND1
output ground
OGND2
output ground
OGND3
output ground
OGND4
output ground
30
37
AMP
44
ADC
FINE
DAC
FINE
CLK
CLK
CCD2
V
CCD1
V
CCA3
V
CCA2
V
CCA1
V
24
1
2
21
3
17
13
7
TDA8760
42
CCO3
V
V
43
CCO4
D9 (MSB)29D831D732D633D534D435D336D240D141D0 (LSB)26IR
data outputs
27
TTL
ERROR
OUTPUTS
CORECTION
MBD222 - 2
25
28
2322
20
4
TDA8760
CCO1
V
CCO2
V
OTC
CS
DGND2
digital groundanalog ground
DGND1
handbook, full pagewidth
Fig.1 Block diagram for SO187 package.
refL
V
15 14
refH
V
1996 Sep 12 4
AMP
10
VIV
16
ADC
COARSE
AND
HOLD
SAMPLE
11
I
AGND4
12
AGND3
9
AGND2
8
AGND1
Page 5
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
PINNING
SYMBOL PIN DESCRIPTION
CLK 1 clock input
CLK 2 complementary clock input
V
CCD1
DGND1 4 digital ground
n.c. 5 not connected
n.c. 6 not connected
V
CCA1
AGND1 8 analog ground
AGND2 9 analog ground
V
I
V
I
AGND3 12 analog ground
V
CCA2
V
refL
V
refH
AGND4 16 analog ground
V
CCA3
n.c. 18 not connected
n.c. 19 not connected
DGND2 20 digital ground
V
CCD2
CS 22 chip select input (TTL level input; active HIGH)
OTC 23 output two’s complement
OGND1 24 output ground
V
CCO1
IR 26 in-range output
D9 27 data output, bit 9 (MSB)
V
CCO2
D8 29 data output, bit 8
OGND2 30 output ground
D7 31 data output, bit 7
D6 32 data output, bit 6
D5 33 data output, bit 5
D4 34 data output, bit 4
D3 35 data output, bit 3
D2 36 data output, bit 2
OGND3 37 output ground
n.c. 38 not connected
n.c. 39 not connected
D1 40 data output, bit 1
3 digital supply voltage (+5 V)
7 analog supply voltage (+5 V)
10 analog input voltage
11 complementary analog input voltage
13 analog supply voltage (+5 V)
14 reference voltage LOW
15 reference voltage HIGH
17 analog supply voltage (+5 V)
21 digital supply voltage (+5 V)
25 output supply voltage (+5 V)
28 output supply voltage (+5 V)
TDA8760
1996 Sep 12 5
Page 6
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
SYMBOL PIN DESCRIPTION
D0 41 data output, bit 0 (LSB)
V
CCO3
V
CCO4
OGND4 44 output ground
handbook, full pagewidth
42 output supply voltage (+5 V)
43 output supply voltage (+5 V)
CCD1
n.c.
5
V
DGND1
4
3
CLK
CLK
2
1
TDA8760
V
CCA1
AGND1
AGND2
V
AGND3
V
CCA2
V
refL
V
refH
AGND4
V
CCA3
n.c.
6
7
8
9
V
10
I
11
I
12
13
14
15
16
17
CCO4
V
OGND4
44
43
CCO3
V
42
D0 (LSB)
41
D1
40
39
38
37
36
35
34
33
32
31
30
29
TDA8760
n.c.
n.c.
OGND3
D2
D3
D4
D5
D6
D7
OGND2
D8
21
20
CCD2
V
DGND2
22
CS
18
n.c.
19
n.c.
Fig.2 Pin configuration for SOT187-2.
1996 Sep 12 6
23
OTC
24
25
CCO1
V
OGND1
26
IR
27
28
CCO2
V
D9 (MSB)
MGA928-1
Page 7
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
V
V
∆V
∆V
∆V
V
V
I
O
T
T
T
CCA
CCD
CCO
CC1
CC2
CC3
I
I(p-p)
stg
amb
j
analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
output supply voltage −0.3 +7.0 V
supply voltage difference between
V
and V
CCA
CCD
supply voltage difference between
V
and V
CCO
CCD
supply voltage difference between
V
and V
CCA
CCO
input voltage referenced to AGND 0.3 V
input voltage for differential clock
−0.5 +0.5 V
−0.5 +0.5 V
−0.5 0.5 V
CCA
− V
CCD
V
V
drive (peak-to-peak value)
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 +70 °C
junction temperature − +150 °C
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER THERMAL RESISTANCE
R
th j-a
Thermal resistance from junction to ambient in free air
TDA8760K/4 35 K/W
TDA8760K/2 46 K/W
1996 Sep 12 7
Page 8
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
CHARACTERISTICS
V
CCA=VCCD=VCCO
V
− V
CCA
CCD=VCCO
Typical values measured at V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
V
V
I
CCA
I
CCD
I
CCO
CCA
CCD
CCO
analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output supply voltage 4.75 5.0 5.25 V
analog supply current − 95 100 mA
digital supply current − 40 45 mA
output supply current all outputs LOW − 35 40 mA
Inputs
CLK
AND CLK (REFERENCED TO DGND); note 1
V
V
I
IL
I
IH
Z
C
∆V
IL
IH
I
I
clk
LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current V
HIGH level input current V
input impedance f
input capacitance f
AC input voltage for
switching (V
OTC AND CS (REFERENCED TO DGND); see Table 3
V
IL
V
IH
I
IL
I
IH
LOW level input voltage 0 − 0.8 V
HIGH level input voltage 2.0 − V
LOW level input current VIL= 0.8 V −400 −−µA
HIGH level input current VIH= 2.0 V −−20 µA
= 4.75 to 5.25 V; AGND and DGND shorted together;
− V
CCD=VCCA
− V
CCA=VCCD=VCCO
= −0.25 to +0.25 V; T
CCO
clk
clk
V
clk
= 40 MHz − 2 − kΩ
clk
= 40 MHz − 4.5 − pF
clk
=5V; T
or V
or V
or V
= 0 to +70 °C; unless otherwise specified.
amb
=25°C.
amb
= 0.4 V −400 −−mA
clk
= 2.0 V −−100 mA
clk
clk=VCCD
DC level = 1.5 V 0.5 − 2.0 V
− V
clk
)
DC level = 2.5 V 1.5 − 5.0 V
clk
CCD
V
−−300 mA
CCD
V
1996 Sep 12 8
Page 9
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
AND V
I
I
IL
I
IH
Z
I
C
I
V
Ioffset(d)
V
Ioffset(s)
Voltage controlled regulator inputs V
V
refH
V
refL
V
I(p-p)
I
refH
I
refL
Voltage controlled regulator inputs V
V
refH
V
refL
V
I(p-p)
I
refH
I
refL
Outputs (referenced to DGND)
(REFERENCED TO AGND); see also Tables 1 and 2
I
LOW level input current V
HIGH level input current V
refH
refH
− V
= 1.5 V − 7 −µA
refL
− V
= 1.5 V − 22 −µA
refL
input impedance fi= 4.43 MHz − 2 − kΩ
input capacitance fi= 4.43 MHz − 4.5 − pF
input offset voltage differential mode; VI= VI;
output code 511; Table 1
= 5 V 3.3 3.4 3.6 V
V
CCA
= 4.75 V 3.2 − 3.45 V
V
CCA
= 5.25 V 3.3 − 3.8 V
V
CCA
input offset voltage single mode; VI=V
Ioffset(s)
;
output code 511; Table 2
= 5 V 3.6 3.7 3.8 V
V
CCA
= 4.75 V 3.5 − 3.65 V
V
CCA
= 5.25 V 3.6 − 4.0 V
V
CCA
and V
refH
reference voltage HIGH 4.0 4.5 V
(referenced to AGND); differential input
refL
CCA
reference voltage LOW 2.5 3.0 3.5 V
input voltage amplitude
1.4 1.5 1.6 V
(peak-to-peak value)
input current at V
input current at V
refH
refL
refH
and V
(referenced to AGND); single input
refL
reference voltage HIGH 4.0 4.4 V
− 10 −µA
− 10 −µA
CCA
reference voltage LOW 2.5 3.0 3.5 V
input voltage amplitude
1.3 1.4 1.5 V
(peak-to-peak value)
input current at V
input current at V
refH
refL
− 10 −µA
− 10 −µA
V
V
IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO DGND)
D
V
OL
V
OH
I
O
LOW level output voltage IO= 2 mA 0 − 0.4 V
HIGH level output voltage IO= −0.4 mA 2.4 − V
output current in 3-state
mode
1996 Sep 12 9
0.4V<VO<V
CCO
CCD
V
−20 − +20 µA
Page 10
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Switching characteristics
CLOCK FREQUENCY f
f
clk(min)
f
clk(max)
minimum clock frequency −−1 MHz
maximum clock frequency
TDA8760K/4 40 −−MHz
TDA8760K/2 20 −−MHz
t
CPH
t
CPL
clock pulse width HIGH note 7 10 −−ns
clock pulse width LOW 8 −−ns
Analog signal processing in differential input mode; see Table 1; 50% clock duty factor;
V
I(p-p)=VrefH
L
INEARITY
− V
ILE DC integral linearity error f
DLE DC differential linearity error f
AILE AC integral linearity error note 3 −±1.2 ±2.0 LSB
OFE offset error V
GE gain error; amplitude spread
between devices
BANDWIDTH (f
clk
B Analog bandwidth −1dB − 140 − MHz
ARMONICS (f
H
f
1
clk
fundamental harmonics
(full scale)
f
all
harmonics (full scale);
all components
second harmonics −−70 −63 dB
third harmonics −−70 −63 dB
THD total harmonic distortion f
SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Figs 6, 8 and 9
SNR signal-to-noise ratio without harmonics;
(note 1; see Fig.3)
clk
= 1.5 V
refL
clk
clk
CCA=VCCD=VCCO
VI=VI; T
output code = 511
V
CCA=VCCD=VCCO
T
amb
V
refH
=40MHZ); note 9
−3dB − 220 − MHz
=40MHZ); see Figs 6, 8 and 9
fi= 4.43 MHz −−0dB
fi= 4.43 MHz
= 4.43 MHz; note 2 −−65 −60 dB
i
f
clk
fi= 4.43 MHz; T
= 4 MHz −±1.0 ±2.0 LSB
= 4 MHz −±0.6 ±1.0 LSB
amb
=5V;
=25°C;
=5V;
−3 − +3 LSB
−10 − +10 LSB
=25°C;
− V
= 1.5 V
refL
54 56 − dB
= 40 MHz;
=25°C
amb
1996 Sep 12 10
Page 11
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
EFFECTIVE BITS; notes 4 and 5; see Figs 6, 8 and 9
EB effective bits
TDA8760K/2 (f
= 20 MHz)
clk
effective bits
TDA8760K/4 (f
= 40 MHz)
clk
TWO-TONE
Two-tone two-tone intermodulation
rejection
BIT ERROR RATE
BER bit error rate f
DIFFERENTIAL GAIN; SEE Fig.5
G
diff
differential gain f
DIFFERENTIAL PHASE
Φ
diff
differential phase f
Analog signal processing in single input mode; see Table 2; 50% clock duty factor; V
fi= 4.43 MHz − 8.90 − bits
= 7.5 MHz − 8.70 − bits
f
i
fi= 4.43 MHz − 8.80 − bits
=10MHz − 8.80 − bits
f
i
=15MHz − 8.70 − bits
f
i
f
= 40 MHz; note 8 −−65 − dB
clk
= 40 MHz;
clk
fi= 4.43 MHz; VI= ±16 LSB
− 2 × 10
−12
− times/
samples
at code 512
= 20 MHz; fi= 4.43 MHz − 0.5 − %
clk
= 40 MHz; fi= 4.43 MHz − 1.0 − %
f
clk
= 40 MHz; fi= 4.43 MHz − 0.1 0.2 deg
clk
I(p-p)=VrefH
− V
refL
= 1.4 V
L
INEARITY
ILE DC integral linearity error f
DLE DC differential linearity error f
= 4 MHz −±1.0 ±2.0 LSB
clk
= 4 MHz −±0.6 ±1.0 LSB
clk
AILE AC integral linearity error note 3 −±1.2 ±2.0 LSB
ANDWIDTH (f
B
=40MHZ); note 9
clk
B Analog bandwidth −1dB − 140 − MHz
−3dB − 220 − MHz
ARMONICS (f
H
f
1
=40MHZ); see Fig.7
clk
fundamental harmonics
fi= 4.43 MHz −−0dB
(full scale)
f
all
harmonics (full scale);
fi= 4.43 MHz
all components
second harmonics −−61 − dB
third harmonics −−62 − dB
THD total harmonic distortion f
= 4.43 MHz; note 2 −−59 − dB
i
SIGNAL-TO-NOISE RATIO; notes 4 and 5; see Fig.7
1996 Sep 12 11
Page 12
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
SNR signal-to-noise ratio without harmonics;
f
= 40 MHz;
clk
fi= 4.43 MHz; T
amb
EFFECTIVE BITS; notes 4 and 5; see Fig.7
EB effective bits
TDA8760K/2 (f
effective bits
TDA8760K/4 (f
= 20 MHz)
clk
= 40 MHz)
clk
fi= 4.43 MHz − 8.70 − bits
= 7.5 MHz − 8.50 − bits
f
i
fi= 4.43 MHz − 8.50 − bits
=10MHz − 8.20 − bits
f
i
TWO-TONE
Two-tone two-tone intermodulation
f
= 40 MHz; note 8 −−60 − dB
clk
rejection
BIT ERROR RATE
BER bit error rate f
= 40 MHz;
clk
fi= 4.43 MHz; VI= ±16 LSB
at code 512
DIFFERENTIAL GAIN; see Fig.5
G
diff
differential gain f
= 20 MHz; fi= 4.43 MHz − 0.5 − %
clk
= 40 MHz; fi= 4.43 MHz − 1.0 − %
f
clk
DIFFERENTIAL PHASE
Φ
diff
differential phase f
= 40 MHz; fi= 4.43 MHz − 0.1 0.2 deg
clk
Timing (note 6; see Fig.3; CL = 15 pF)
t
ds
t
h
t
d
sampling delay time −−2ns
output hold time 8 −−ns
output delay time − 12 16 ns
3-state output delay times (see Fig.4)
t
dZH
t
dZL
t
dHZ
t
dLZ
enable HIGH − 12 16 ns
enable LOW − 12 16 ns
disable HIGH − 812ns
disable LOW − 16 20 ns
=25°C
54 56 − dB
− 2 × 10
−12
− times/
samples
1996 Sep 12 12
Page 13
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
Notes
1. The circuit has two clock inputs: CLK and CLK. There are three modes of operation:
a) TTL mode 1:
CLK input is at TTL level with a threshold voltage of 1.5 V and sampling is taken on the falling edge of the clock
input signal. CLK decoupled to DGND via a 100 nF capacitor.
b) TTL mode 2:
CLK input is at TTL level with threshold voltage of 1.5 V and sampling is taken on the rising edge of the clock
input signal. CLK decoupled to DGND via a 100 nF capacitor.
c) TTL mode 3:
CLK and CLK inputs are at differential TTL levels.
d) AC driving modes:
When driving the CLK input directly and with any AC signal of minimum 0.5 V (p-p) and with a DC level of 1.5 V,
the sampling takes place at the falling edge of the clock signal.
When driving the CLK input with the same signal, sampling takes place at the rising edge of the clock signal.It is
recommended to decouple the CLK or CLK input to DGND via a 100 nF capacitor.
2. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:
a)
THD 20 log
b) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.
3. AC linearity: full-scale differential sine wave (f
4. Effective bits with differential input and single input are respectively executed with full scale differential input and
full-scale single sine wave.
5. Effective bits are obtained via a Fast Fourier Transformer (FFT) treatment taking 8K acquisition points per period.
The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to SNR: SNR = EB × 6.02 + 1.76 dB.
6. Output data acquisition: the output data is available after the maximum delay of td.
7. t
8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
9. The −3 dB (or −1 dB) analog bandwidth is determined by the 3 dB (or 1 dB) reduction in the reconstructed output,
of 9 ns (minimum) can be applied at the penalty of 0.5 effective bit drop compared to typical values.
CPH
input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.
the input being a full-scale sine wave.
---------------------------------------------------------------------------------------------------------------=
(2nd)2(3rd)2(4th)2(5th)2(6th)
++++
F
2
= 4.43 MHz; f
i
= 40 MHz).
clk
1996 Sep 12 13
Page 14
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
Table 1 Output coding with differential inputs (typical values to AGND); V
I(p-p)=VrefH
BINARY OUTPUTS
CODE V
I(p-p)
V
I(p-p)
IR
D9 TO D0 D9 TO D0
underflow <3.025 >3.775 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 3.025 3.775 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 −−1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
• − − • •••••••••• ••••••••••
511 3.40 3.40 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
• − − • •••••••••• ••••••••••
1022 −−1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0
1023 3.775 3.025 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
overflow >3.775 <3.025 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
Table 2 Output coding with single inputs (typical values to AGND); V
I(p-p)=VrefH
BINARY OUTPUTS
CODE V
I(p-p)
IR
D9 TO D0 D9 TO D0
underflow <3.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 3.0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 − 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
• − • •••••••••• ••••••••••
511 3.7 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
• − • •••••••••• ••••••••••
1022 − 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0
1023 4.4 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
overflow >4.4 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
− V
= 1.5 V
refL
TWO’S COMPLEMENT
OUTPUTS
− V
= 1.4 V; V
refL
TWO’S COMPLEMENT
OUTPUTS
I(p-p)
= 3.7 V
Table 3 Mode selection.
OTC CS D0 TO D9 AND IR
1 1 binary; active
0 1 two’s complement; active
(1)
X
Note
1. Where: X = don’t care.
1996 Sep 12 14
0 high impedance
Page 15
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
t
CPL
t
CPH
CLK
V
l
DATA
D0 to D7
sample N
t
dS
DATA
N - 2
sample N + 1
DATA
N - 1
sample N + 2
t
d
DATA
N
TDA8760
1.4 V
t
HD
DATA
N + 1
2.4 V
1.4 V
0.4 V
MBD721
full pagewidth
CS =100 kHz.
V
CS
output
data
output
data
CCD
LOW
t
dLZ
10 %
TDA8760
CS
Fig.3 Timing diagram.
t
dZL
HIGH
50 %
15 pF
HIGH
3.3 kΩ
t
90 %
dHZ
LOW
S1
V
CCD
50 %
t
dZH
50 %
MBD723
TEST S1
t
t
t
t
dLZ
dZL
dHZ
dZH
V
V
GND
GND
CCD
CCD
1996 Sep 12 15
Fig.4 Timing diagram and test conditions of 3-state output delay time.
Page 16
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
handbook, full pagewidth
V
i
(1)
fi= 4.43 MHz
(1)
fi= 4.43 MHz
(1)
(1) Full-scale divided-by-5.
V
G
diff
maximum of
n
------------------------------------------
1to4()V0–
V0
DC offset voltage
100%×=
fi= 4.43 MHz
(1)
fi= 4.43 MHz
(1)
fi= 4.43 MHz
TDA8760
digital output
CODE 1023
V4
V3
V2
V1
V0
CODE 0
MBD722
9.0
f =
20 MHz
effective
clk
bits
8.8
8.6
8.4
8.2
8.0
04 12
40 MHz
Fig.5 Differential gain measurement conditions.
MGA931 - 2
8
16
f (MHz)
i
20
9.0
effective
bits
8.8
8.6
8.4
8.2
8.0
02 6
f =
clk
20 MHz
40 MHz
4
MBD223 - 1
8
f (MHz)
i
10
Fig.6 Typical effective bits under differential input
mode as a function of input signal
frequency.
1996 Sep 12 16
Fig.7 Typical effective bits under single input
mode as a function of input signal
frequency.
Page 17
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
0
amplitude
(dB)
–20.2
–40.4
–60.6
–80.8
–101
–121
Effective bits: 9.1; THD =−65.81 dB;
Harmonic levels (dB): 2nd =−75.54; 3rd = −76.29; 4th = −74.90; 5th = −67.50; 6th = −90.87.
TDA8760
MRC299
10.00 1.25 2.50 3.75 5.00 6.25 7.50 8.75
f (MHz)
Fig.8 Fast Fourier Transformer (f
0
amplitude
(dB)
–20
–40
–60
–80
–100
–120
0 2.5 5 7.5 10 12.5 15 17.5 20
Effective bits: 8.92; THD = −65.86 dB;
Harmonic levels (dB): 2nd = −70.92; 3rd = −68.48; 4th = −75.32; 5th = − 81.40; 6th = −72.69.
= 20 MHz; fi= 4.43 MHz); for differential input mode.
clk
MBD220
f (MHz)
Fig.9 Fast Fourier Transformer (f
1996 Sep 12 17
= 40 MHz; fi= 4.43 MHz); for differential input mode.
clk
Page 18
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
INTERNAL PIN CONFIGURATION
V
handbook, full pagewidth
V
CCA1
71317 321
V
I
10 and 11
and
V
I
refL
refH
14
15
V
V
V
CCA2
CCA3VCCD1VCCD2
AGND
V
CCA
V
CCA
CLK CLK
12
V
CCD
30
Ωk
DGND
30
1.5 V
25 and 43
Ωk
V
CCO1
V
CCO4
TDA8760
/
AGND
20
Ωk
CS
22 and 23
and
OTC
DGND
AGND18AGND29AGND312AGND416DGND14DGND2
Fig.10 Description of input and output circuitry.
V
CCO3
1.5 V
TDA8760
digital groundanalog ground
31 to 36,
40 and 41
30 and 37
20
MGA978
data output
bit 7 to 0
OGND2 /
OGND3
1996 Sep 12 18
Page 19
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
APPLICATION INFORMATION
handbook, full pagewidth
differential
analog inputs
(2)
R1
3 V
IN
4.5 V
4.7 F
µ
(2)
R2
R3
IN
4.7 F
µ
100
nF
(2)
R4
(3)
(2)
100 nF
IN
IN
100 nF
100 nF
(3)
100
nF
5 V
100 nF
5 V5 V
100 nF
6543214443424140
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
100 nF
TDA8760
5 V
100 nF
100 nF
output format select
chip select input
CLK
100 nF
5 V
TDA8760
(1)
D0 (LSB)
D1
39
38
37
36
35
34
33
32
31
30
29
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
MGA979
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain a middle voltage of 3.4 V; see Table 1.
(3) V
refH
and V
must be decoupled to AGND.
refL
Fig.11 Application diagram for differential input mode.
1996 Sep 12 19
Page 20
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
handbook, full pagewidth
100
nF
single
analog
input
IN
3 V
R1
(2)
4.5 V
100
nF
100 nF
IN
IN
(3)
100
nF
100 nF
100 nF
5 V
(2)
R2
(3)
100 nF
5 V5 V
100 nF
6543214443424140
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
100 nF
TDA8760
5 V
100 nF
100 nF
output format select
chip select input
CLK
5 V
(1)
39
38
37
36
35
34
33
32
31
30
29
100 nF
TDA8760
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
MGA980
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 and R2 must be determined in order to obtain 3.4 V at the transformer; see Table 1.
Adaptation with the single input signal impedance must be taken care of.
(3) V
refH
and V
must be decoupled to AGND.
refL
Fig.12 Application diagram for differential input mode using an input transformer.
1996 Sep 12 20
Page 21
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
handbook, full pagewidth
(2)
R1
3 V
single
analog
input
IN
4.5 V
4.7 F
(2)
R2
100 nF
IN
IN
100 nF
100 nF
(3)
100
nF
R3
4.7 F
µ
100
nF
(2)
R4
(3)
(2)
µ
5 V
100 nF
5 V5 V
100 nF
6543214443424140
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
100 nF
TDA8760
5 V
100 nF
100 nF
output format select
chip select input
CLK
5 V
(1)
39
38
37
36
35
34
33
32
31
30
29
100 nF
TDA8760
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9 (MSB)
MGA981
The analog, digital and output supplies should be separated and decoupled.
(1) Differential clock signals can be applied if required.
(2) R1 = R3; R2 = R4. R1, R2, R3 and R4 must be determined in order to obtain a middle voltage of 3.7 V; see Table 2.
(3) V
refH
and V
must be decoupled to AGND.
refL
Fig.13 Application diagram for single input mode.
1996 Sep 12 21
Page 22
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
PACKAGE OUTLINE
PLCC44: plastic leaded chip carrier; 44 leads
e
D
y
40
44
1
pin 1 index
6
β
k
717
e
D
H
D
X
2939
TDA8760
SOT187-2
e
E
A
Z
E
28
H
E
E
A
A
1
A
e
18
k
1
v M
Z
D
A
4
B
v M
B
w M
detail X
b
p
b
1
(A )
3
L
p
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
A
UNIT A
mm
inches
1
A
3
min. max. max. max. max.
4.57
0.51
0.020
0.25
0.01
4.19
0.180
0.165
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
OUTLINE
VERSION
SOT187-2
1996 Sep 12 22
0 5 10 mm
A
3.05
0.12
4
b
0.53
0.33
0.021
0.013
b
p
1
0.81
0.66
0.032
0.026
D
16.66
16.51
0.656
0.650
(1)
(1)
E
eH
e
D
1.27
0.05
16.00
14.99
0.630
0.590
16.66
16.51
0.656
0.650
REFERENCES
IEC JEDEC EIAJ
112E10 MO-047AC
scale
e
16.00
14.99
0.630
0.590
k
H
E
D
E
17.65
17.65
17.40
17.40
0.695
0.695
0.685
0.685
k
1.22
1.07
0.048
0.042
0.51
0.020
1
L
p
1.44
1.02
0.057
0.040
0.18 0.100.18
0.007 0.0040.007
EUROPEAN
PROJECTION
(1) (1)
Z
Z
E
D
ywv β
2.16
2.16
o
45
0.085
0.085
ISSUE DATE
92-11-17
95-02-25
Page 23
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
converter
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our
Reference Handbook”
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
(order code 9398 652 90011).
“Quality
(order code 9397 750 00192).
TDA8760
Wave soldering
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1996 Sep 12 23
Page 24
Philips Semiconductors Product specification
10-bit high-speed analog-to-digital
TDA8760
converter
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATION
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1996 Sep 12 24
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