Datasheet TDA8758G-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1995 Mar 22
File under Integrated Circuits, IC02

1996 Feb 01

INTEGRATED CIRCUITS

TDA8758

YC 8-bit low-power
analog-to-digital video interface

1996 Feb 01 2

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital
video interface

TDA8758

FEATURES

• Two 8-bit ADCs:
– one Luminance or CVBS channel
– one Chrominance channel

• Sampling rate up to 32 MHz

• Binary or two's complement 3-state TTL outputs for

each channel

• Internal reference voltage regulator

• TTL-compatible digital inputs and outputs

• Power dissipation of 530 mW (typical)

• Input selector circuit (five selectable video inputs for

CVBS or YC processing)

• Peak white enable input

• Clamp and Automatic Gain Control (AGC) functions for

Y/CVBS channel (clamping on code 64 and Peak White
level control at code 255)

• Clamp function for C channel (code 128)

• No sample-and-hold circuit required.

APPLICATIONS

• Video signal decoding

• Digital picture processing

• Frame grabbing

• Multimedia with the Philips Desktop Video chip set (and

especially SAA7196 multistandard decoder and scaler).

GENERAL DESCRIPTION

The TDA8758 is an 8-bit video high-speed low-power
analog-to-digital conversion (ADC) interface for YC and
CVBS signal processing. It converts 1-of-3 CVBS input
signals or 1-of-2 YC input signals into binary or two’s
complement words at a sampling rate of 32 MHz.
All analog signal inputs are digitally clamped and an ADC
interface is provided on the Y/CVBS channel. A fast
precharge on clamp and AGC is provided for start-up.
All digital inputs and outputs are TTL compatible.

QUICK REFERENCE DATA

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 59 70 mA

I

CCD

digital supply current − 28 40 mA

I

CCO

output supply current CL=15pF − 19 28 mA
ILE DC integral linearity error −±0.75 ±1.5 LSB
DLE DC differential linearity error −±0.4 ±1.0 LSB
EB effective bits

(from video input to digital outputs)

f

clk

= 32 MHz;

fi= 4.43 MHz

− 7.1 − bits

f

clk(max)

maximum clock frequency 30 32 − MHz
B maximum −3 dB bandwidth

(input preamplifier)

full-scale; 0 dB gain − 15 − MHz

α

ct

crosstalk between Y and C channels

and each video input

−−63 −55 dB

P

tot

total power dissipation − 530 724 mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8758G LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

1996 Feb 01 3

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGB469 - 1

TDA8758

CLAMP

LEVEL 128

ADC

INPUT

SELECTOR

COMPARATOR

TTL

TIMING

GENERATOR

COMPARATORS

48 45 8 44 17 1 46 15

ADC TTL

713

AGC &
CLAMP 64

1614 19 20

2

4

6

9

11

5

10 21 41 32

33

to

40

47

42

22

23

to

30

12 31 43 18 3

8

8

C7 to C0

Y7 to Y0

OGND2

OFC

DEC2

ANOUTC

REG1

CCA

V

OGND1

CLK

DEC1

CHROM2

AGND

CHROM1

SEL2

CVBS3

SDN

Y2/CVBS2

Y1/CVBS1

SEL1

PWE

DEC3

ANOUTY

REG2

DGND

GATE A

GATE B

OFY

V

CCO2

C

CLPC

V

CCO1

C

CLPY

V

CCA

C

AGC

V

CCD

1996 Feb 01 4

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

PINNING

SYMBOL PIN DESCRIPTION

DEC1 1 decoupling input 1
CHROM2 2 chrominance analog voltage input 2
AGND 3 analog ground
CHROM1 4 chrominance analog voltage input 1
SEL2 5 selection control input 2
CVBS3 6 luminance analog voltage input 3
C

CLPY

7 Y channel clamping capacitor
SDN 8 stabilizer decoupling node
Y2/CVBS2 9 luminance analog voltage input 2
V

CCA

10 analog supply voltage (+5 V)
Y1/CVBS1 11 luminance analog voltage input 1
SEL1 12 selection control input 1
C

AGC

13 AGC capacitor
PWE 14 peak white enable input (active LOW)
DEC3 15 decoupling input 3
ANOUTY 16 analog output for Y channel
REG2 17 decoupling input 2 (internal stabilization loop decoupling)
DGND 18 digital ground
GATE A 19 AGC control input
GATE B 20 clamp control input
V

CCD

21 digital supply voltage (+5 V)
OFY 22 Y channel output format/chip enable (3-state input)
Y7 23 Y channel data output; bit 7 (MSB)
Y6 24 Y channel data output; bit 6
Y5 25 Y channel data output; bit 5
Y4 26 Y channel data output; bit 4
Y3 27 Y channel data output; bit 3
Y2 28 Y channel data output; bit 2
Y1 29 Y channel data output; bit 1
Y0 30 Y channel data output; bit 0 (LSB)
OGND2 31 output ground 2
V

CCO2

32 output supply voltage 2 (+5 V)
C7 33 C channel data output; bit 7 (MSB)
C6 34 C channel data output; bit 6
C5 35 C channel data output; bit 5
C4 36 C channel data output; bit 4
C3 37 C channel data output; bit 3
C2 38 C channel data output; bit 2
C1 39 C channel data output; bit 1
C0 40 C channel data output; bit 0 (LSB)

1996 Feb 01 5

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

V

CCO1

41 output supply voltage 1 (+5 V)
CLK 42 clock input
OGND1 43 output ground 1
REG1 44 decoupling input 1 (internal stabilization loop decoupling)
ANOUTC 45 analog output for C channel
DEC2 46 decoupling input 2
OFC 47 C channel output format/chip enable (3-state input)
C

CLPC

48 C channel clamping capacitor

SYMBOL PIN DESCRIPTION

Fig.2 Pin configuration.

handbook, full pagewidth

1
2
3
4
5
6
7
8

9
10
11

36
35
34
33
32

31
30
29
28
27
26

13

14

15

16

17

18

19

20

21

22

23

48

47

46

45

44

43

42

41

40

39

38

12

24 37

25

pin 1
index
corner

TDA8758

MGB470

C4
C5

C6
C7

OGND2
Y0
Y1
Y2
Y3
Y4
Y5

DEC1

CHROM2

AGND

CHROM1

SEL2

CVBS3

SDN

Y2/CVBS2

Y1/CVBS1

SEL1

V

CCO2

OFC

DEC2

ANOUTC

REG1

OGND1

CLK

C0C1C2

C3

C

CLPC

V

CCO1

C

CLPY

V

CCA

PWE

DEC3

ANOUTY

REG2

DGND

GATE A

GATE B

OFY

Y7

Y6

C

AGC

V

CCD

1996 Feb 01 6

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

FUNCTIONAL DESCRIPTION

The TDA8758 provides a simple interface between CVBS
or Y/C analog signals and a digital colour decoder.

Video inputs selection

The input selector allows a choice from different video
sources, and has one of the following configurations:

A: Two Y/C and one CVBS signals
B: One Y/C and two CVBS signals
C: Three CVBS signals (only the Y channel is used).

The wiring of the five video inputs (pins 2, 4, 6, 9 and 11)
and the control of the two selection inputs (pins 5 and 12)
will depend on the available video sources.

• In configuration A, connect as follows:
– Y1 to pin 11
– C1 to pin 4
– Y2 to pin 9
– C2 to pin 2
– CVBS3 to pin 6.
Keep SEL2 (pin 5) LOW and select Y1/C1 or Y2/C2 by

switching SEL1 (pin 12).
CVBS3 is selected with SEL1 and SEL2 HIGH.

• In configuration B, replace Y1 (or Y2) by a CVBS input
(no more C1 or C2). The selection mode is the same.

• In configuration C, connect as follows:
– CVBS1 to pin 11
– CVBS2 to pin 9
– CVBS3 to pin 6.
Use both SEL1 and SEL2 to select inputs.

Remark: the video inputs selection is a static selection.

Synchronization pulses

GATE A and GATE B pulses are synchronization pulses
occurring during the sync period and rear porch
respectively. They should be distinct.

On the Y channel, the digital output of the ADC is
compared to internal digital reference levels. The resultant
outputs control the charge or discharge current of a
capacitor connected to the C

AGC

pin. The voltage across
this capacitor controls the gain of the video amplifier.
This is the control loop.

The sync level comparator is active during a positive-going
pulse at the GATE A input. This means that sync pulse of
the composite video signal is used as an amplitude
reference. The bottom of the sync pulse is adjusted to
obtain a digital output of logic 1 at the converter Y output.
As the black level is digital level 64, the sync pulse will
have a digital amplitude of 64 LSBs.

The Peak White control loop is active when the selection
pin

PWE is LOW. Then, if the Y video signal exceeds the
digital code of 255, it will be limited to avoid any over-range
of the converter.

The clamp level control is accomplished by using the same
techniques as used for the gain control. On both Y and C
channels, the black level digital comparators are active
during a positive-going pulse at the GATE B input. On the
Y channel, the clamping capacitor connected to the C

CLPY

pin will be charged or discharged to adjust the digital
output to code 64. On the C channel, the clamping
capacitor connected to the C

CLPC

pin will be charged or

discharged to adjust the digital output to code 128.

1996 Feb 01 7

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

THERMAL CHARACTERISTICS

CHARACTERISTICS

V

CCA=V10

to V3= 4.75 to 5.25 V; V

CCD=V21

to V18= 4.75 to 5.25 V; V

CCO1=V41

to V43= 4.75 to 5.25 V;

V

CC02=V32

to V31= 4.75 to 5.25 V; AGND and DGND shorted together; V

CCA

to V

CCD

= −0.25 to +0.25 V;

V

CCO

to V

CCD

= −0.25 to +0.25 V; V

CCA

to V

CCO

= −0.25 to +0.25 V; T

amb

= 0 to +70 °C; typical values measured

at V

CCA=VCCD=VCCO

= 5 V and T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

CCO

output supply voltage −0.3 +7.0 V

∆V

CC

supply voltage difference between V

CCA

and V

CCD

−1.0 +1.0 V

supply voltage difference between V

CCO

and V

CCD

−1.0 +1.0 V

supply voltage difference between V

CCA

and V

CCO

−1.0 +1.0 V

V

I

input voltage referenced to AGND − 5.0 V

V

clk(p-p)

AC input voltage for switching (peak-to-peak value) referenced to DGND − V

CCO

V

I

O

output current − +6 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 +70 °C

T

j

junction temperature − +150 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 72 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 59 70 mA

I

CCD

digital supply current − 28 40 mA

I

CCOtot

total output supply current CL=15pF − 19 28 mA

Video amplifier inputs

Y1/CVBS1, Y2/CVBS2, CVBS3, CHROM1

AND CHROM2 INPUTS

V

I(p-p)

input voltage (peak-to-peak value) AGC load with external

capacitor; note 1
Y channel 0.7 − 1.4 V
C channel − 1.0 − V

|Z

i

| input impedance fi= 6 MHz − 25 − kΩ

C

I

input capacitance fi= 6 MHz − 2 − pF

1996 Feb 01 8

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

SEL1 AND SEL2 TTL INPUTS; see Table 1
V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current VI= 0.4 V −400 −−µA

I

IH

HIGH level input current VI= 2.7 V −−20 µA
GATE A AND GATE B TTL INPUTS; see Figs 5 and 6
V

IL

LOW level input voltage 0 − 0.8 V
V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current VI = 0.4 V −400 −−µA
I

IH

HIGH level input current VI = 2.7 V −−20 µA
AGC INPUT (PIN 13); see Fig.8
V

13(min)

AGC voltage for minimum gain at −3dB − 3.3 − V
V

13(max)

AGC voltage for maximum gain at +3 dB − 3.75 − V
I

12

AGC output current see Table 2
C-CHANNEL CLAMP INPUT (PIN 48)
V

48

CLAMP voltage for code 128 output − 3.45 − V
I

48

CLAMP output current see Table 3
Y-CHANNEL CLAMP INPUT (PIN 7)
V

7

CLAMP voltage for code 64 output − 3.70 − V
I

7

CLAMP output current see Table 3

Video amplifier dynamic characteristics

α

ct

crosstalk between video inputs

(pins 2, 4, 6, 9 and 11)

V

CCA

= 4.75 to 5.25 V −−63 −55 dB

B −3 dB bandwidth − 15 − MHz
∆G gain range −3 − +3 dB
G

stab

gain stability as a function of:

supply voltage f

i

= 4.43 MHz −−0.5 %

supply voltage and temperature −−6%

Analog-to-digital converter inputs

CLK

INPUT (PIN 42)

V

IL

LOW level input voltage 0 − 0.8 V
V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current V

clk

= 0.4 V −400 −−µA

I

IH

HIGH level input current V

clk

= 2.7 V −−20 µA

C

I

input capacitance f

clk

= 32 MHz − 2 − pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Feb 01 9

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

OFY AND OFC INPUTS;3-STATE; see Table 4
V

IL

LOW level input voltage 0 − 0.2 V
V

IH

HIGH level input voltage 2.6 − V

CCD

V

V

I

input voltage in high impedance state − 1.15 − V
I

IL

LOW level input current −370 −300 −µA
I

IH

HIGH level input current − 500 700 µA

Analog-to-digital converter outputs

ANOUTY

AND ANOUTC OUTPUTS (PINS 16 AND 45); see Table 5

V

ANOUT

output voltage digital output = 00 − 2.6 − V
V

ANOUT

output voltage digital output = 255 − 3.6 − V
V

ANOUT(p-p)

output voltage amplitude

(peak-to-peak value)

− 1.0 − V

DIGITAL OUTPUTS Y0 TO Y7, C0 TO C7
V

OL

LOW level output voltage IOL=2mA 0 − 0.6 V
V

OH

HIGH level output voltage IOL= −0.4 mA 2.4 − V

CCD

V
Switching characteristics; see Fig.9
f

clk(max)

CLK input maximum frequency note 2 30 32 − MHz

t

CPH

clock pulse width HIGH 12 −−ns

t

CPL

clock pulse with LOW 12 −−ns

Analog signal processing from video input to digital output on both channels; 0 dB gain (f

clk

= 32 MHz)

INL DC integral non-linearity −±0.75 ±1.5 LSB
DNL DC differential non-linearity −±0.4 ±1.0 LSB
AINL AC integral non linearity f

i

= 4.43 MHz −±1.5 − LSB

ADNL AC differential non-linearity f

i

= 4.43 MHz −±0.5 − LSB
THD total harmonic distortion note 3 −−52 − dB
EB effective bits f

i

= 4.43 MHz; note 4 − 7.1 − bits
G

diff

differential gain V

16,45

= 1.0 V (p-p);
see Fig.4; PAL
modulated ramp; note 5

− 1.5 3.0 %

ϕ

diff

differential phase see Fig.5; PAL

modulated ramp; note 5

− 0.6 1.5 deg

SVRR2 supply voltage ripple rejection note 6 −−5 %/V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Feb 01 10

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Notes

1. 0 dB is obtained at the AGC amplifier when applying V

I(p-p)

= 1.0 V on Y channel.

2. It is recommended that the rise and fall times of the clock are ≥1 ns. In addition, a ‘good layout’ for the digital and
analog grounds is recommended.

3. THD (total harmonic distortion) is obtained with the addition of the first five harmonics:

a) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input.

4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

5. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a
digital-to-analog converter.

6. The supply voltage ripple rejection is the relative variation of the analog signal (full-scale signal at input) for 0.5 V of
supply variation:

Timing (f

clk

= 32 MHz); see Fig.9

D

IGITAL OUTPUTS (C

L

= 15 pF)

t

ds

sampling delay time − 2 − ns

t

h

output hold time 10 −−ns

t

d

output delay time − 15 18 ns

t

W

clamp pulse width see Figs 6 and 7 2 3 −µs
3-state output delay times; see Fig.10
t

dZH

enable HIGH − 12 14 ns
t

dZL

enable LOW − 10 12 ns
t

dHZ

disable HIGH − 58 62 ns
t

dLZ

disable LOW − 70 74 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

THD 20 log

F

(2nd)2(3rd)2(4th)2(5th)2(6th)

2

++++

---------------------------------------------------------------------------------------------------------------=

SVRR2

∆ V

I00()VIFF()

–()V

I00()VIFF()

–()×

∆V

CCA

-----------------------------------------------------------------------------------------------------

=

1996 Feb 01 11

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Table 1 Video input selection

Note

1. X = don't care.

SEL1 SEL2 Y-CHANNEL C-CHANNEL FIGURE 3

0X

(1)

Y1/CVBS1 CHROM1 (a)
1 0 Y2/CVBS2 CHROM2 (b)
1 1 CVBS3 CHROM2 (c)

Fig.3 Video inputs selector.

handbook, full pagewidth

2

CHROM2
CHROM1

SEL2

CVBS3

Y2/CVBS2
Y1/CVBS1

SEL1

4

9
11

6

5

12

C CHANNEL

Y CHANNEL

(a)

2

CHROM2
CHROM1

SEL2

CVBS3

Y2/CVBS2
Y1/CVBS1

SEL1

4

9

11

6

5

12

C CHANNEL

Y CHANNEL

(b)

2

CHROM2
CHROM1

SEL2

CVBS3

Y2/CVBS2
Y1/CVBS1

SEL1

4

9

11

6

5

12

C CHANNEL

Y CHANNEL

(c)

MGB471

1996 Feb 01 12

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Table 2 AGC output current

Note

1. X = don't care.

Table 3 CLAMP output current

Note

1. X = don't care.

PWE GATE A

DIGITAL

OUTPUT

I

AGC

0 0 output < 255 0 µA

output > 255 +540 µA

0 1 output < 0+8µA

0 < output < 255 −8 µA
output > 255 +540µA

10X

(1)

0 µA

1 1 output < 0+8µA

0 < output < 255 −8 µA

CLAMP GATE B

DIGITAL

OUTPUT

I

CLAMP

C 1 output < 128 +54 µA

output > 128 −54 µA

X

(1)

0X

(1)

0 µA

Y 1 output < 64 +54 µA

64 < output −54 µA

Table 4 OFY and OFC input coding

Note

1. Use C ≥ 10 pF to DGND.

OFY (or OFC) Y0 to Y7 (or C0 TO C7)

0 active, twos complement
1 high impedance

open circuit

(1)

active, binary

Table 5 Output coding and ANOUTY (or ANOUTC) voltage (typical values)

STEP V

I

BINARY OUTPUTS TWOS COMPLIMENT

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Underflow − 0000000010000000

0 2.6 0000000010000000
1 − 0000000110000001

. − ................

. − ................

254 − 1111111001111110
255 3.6 1111111101111111

Overflow − 1111111101111111

1996 Feb 01 13

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Fig.4 Typical differential gain result on VM700A.

handbook, full pagewidth

1st 2nd 3rd 4th 5th 6th

1.0

0.0

2.0

3.0

1.0

MBE455

DIFFERENTIAL

GAIN

(%)

(6)

(5)(4)

(3)

(2)

(1)

step number

(1) =0.00; (2) = 0.09; (3) = −0.63; (4) = −0.45; (5) = −0.45; (6) = −1.23.
Differential gain = max. (2) − min. (6) = 1.32%.

Fig.5 Typical differential phase result on VM700A.

handbook, full pagewidth

1st 2nd 3rd 4th 5th 6th

2.0

1.0

1.0

2.0

0

MBE456

DIFFERENTIAL

PHASE

(deg)

(6)

(5)

(4)

(3)

(2)

(1)

step number

(1) = 0.00; (2) = 0.03; (3) = −0.53; (4) = −0.32; (5) = 0.01; (6) = −0.08.
Differential phase = max. (2) − min. (3) = 0.56 deg.

1996 Feb 01 14

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Fig.6 Control mode Y channel.

handbook, full pagewidth

MGB472

digital
output

level

64

255

0

time

black-level

clamping

213

safety

margin

standard picture

level

GATE A

GATE B

sync-level control

peak-level gain control

W

t

W

t

Fig.7 Control mode C-channel.

ndbook, full pagewidth

MGB473

digital
output

level

255

0

time

black-level

clamping

GATE B

128

W

t

1996 Feb 01 15

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Fig.8 AGC behaviour as a function temperature and supply voltage for ANOUTY output; fi= 4.43 MHz, Vi= 0 dB.

handbook, full pagewidth

4.03.93.73.53.33.1

8

6

2

4

4

8

3.0 3.2 3.4 3.6 3.8

MBE463

0

2

6

AGC

GAIN

(dB)

C voltage (V)

AGC

Dotted line: Typical curve (T

amb

=25°C; VCC= 5 V).

Full line: Maximum envelope (T

amb

= 0 to 70 °C; VCC= 4.75 to 5.25 V).

Fig.9 Timing diagram.

handbook, full pagewidth

ds

t

sample N + 1

sample N

CLK

MBE454

sample N + 2

1.4 V

V

l

DATA
C0 to C7
Y0 to Y7

t

d

t

h

CPH

t

CPL

t

2.4 V

0.4 V

1.4 V

DATA
N + 1

DATA

N

DATA

N - 1

DATA

N - 2

1996 Feb 01 16

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Fig.10 Timing diagram and test conditions of 3-state output delay time.

f

OFC=fOFY

= 100 kHz.

handbook, full pagewidth

MBE453

50 %

1.15 V

50 %

HIGH

dZH

t

dHZ

t

50 %

HIGH Z

HIGH Z

LOW

dZL

t

dLZ

t

10 %

90 %

output
data

V

CCD

output
data

3.3 kΩ

15 pF

S1

V

CCD

TDA8758

OFC
OFY

OFC
OFY

TEST

dLZ

t

dZL

t

dHZ

t

dZH

S1

CCD

V

CCD

V

GND
GND

t

1996 Feb 01 17

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

APPLICATION INFORMATION

Fig.11 Application diagram.

handbook, full pagewidth

MGB476

OFC

DEC2

ANOUTC

AGND

REG1

OGND1

CLK

DEC1

AGND

AGND

CHROM2

AGND

CHROM1

SEL2

CVBS3

SDN

Y2/CVBS2

Y1/CVBS1

SEL1

ANOUTY

REG2

DGND

GATE A

GATE B OFY

C

CLPC

C

CLPY

V

CCA

C

AGC

V

CCD

48 47 46

45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

36

35

34

33

32

31

30

29

28

27

26

25

C4

C5

C6

C7

OGND2

Y0

Y1

Y2

Y3

Y4

Y5

C0 C1 C2 C3

Y6Y7

PWE

V

CCO2

( 5 V)

V

CCO1

V

CCA

AGND

V

CCA

( 5 V)

1 µF

75 Ω

75 Ω

75 Ω

75 Ω

75 Ω

4.7 µF

4.7 µF

4.7 µF

4.7 µF

18 nF

22 nF

DEC3

( 5 V)

TDA8758

18
nF

22 nF

1 nF

3.3
nF

470
nF

1 nF

3.3
nF

(1)

(1)

(1) It is recommended that pin 16 and pin 45 are not loaded in order to avoid any distortion.

1996 Feb 01 18

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

Fig.12 Example of system application (DPC71 evaluation board).

ndbook, full pagewidth

MBH012


4

CHROMA1

33 CHR7

CHR7

34 CHR6

CHR6

CHROMA2
Y1/CVBS1
Y2/CVBS2

2

11

9

CVBS3

6

C274.7 µF

C264.7 µF

C254.7 µF

C114.7 µF

SEL1IN0

12

SEL2IN1

5

PWEGPSWO

14

GATE AHSY

19

GATE BHCL

20

IN_ADC_Y

DEC_LLC

INADCY

16

IN_ADC_CINADCC

45

OE_Y

22

OE_C

INADCY
INADCC

47

CHROMA IN

LUMA IN
CVBS1 IN
CVBS2 IN

CLMP_Y
CLMP_C

7

48

SDN

8

C120.1 µF

C140.022 µF

C130.1 µF

DEC1

1

DEC2

46

C160.022 µF

C150.022 µF

AGC_CAP

13

C180.47 µF

REG1

HEADER 3

3SIP100

44

REG2

17

C200.047 µF

C190.047 µF

DEC3

15

C170.022 µF

V

CCA

V

CC

1
2
3

JP14

HEADER 3

3SIP100

V

CC

V

CCA

V

CC

V

CCA

1
2
3

JP15

HEADER 3

3SIP100

V

CC

321

JP5

TDA8758

TDA8758

U2

SAA7151B

SAA7151B

68LLC50U4

35 CHR5

CHR5

36 CHR4

CHR4

37 CHR3

CHR3

38 CHR2

CHR2

39 CHR1

CHR1

40 CHR0

13

CHR7

12

CHR6

11

CHR5

10

CHR4

9

CHR3

8

CHR2

7

CHR1

6

CHR0

55

UV7

56

UV6

57

UV5

58

UV4

59

UV3

60

UV2

61

UV1

62

DEC_UV7

DEC_UV0

to 7

DEC_Y0

to 7

DEC_UV6
DEC_UV5
DEC_UV4
DEC_UV3
DEC_UV2
DEC_UV1
DEC_UV0

UV0

45

D7

46

D6

47

D5

48

D4

49

D3

50

D2

53

D1

54

DEC_Y7
DEC_Y6
DEC_Y5
DEC_Y4
DEC_Y3
DEC_Y2
DEC_Y1
DEC_Y0

DEC_HREF
DEC_HS
DEC_VS

D0

42

HREF

31

HS

30

VS

CHR7
CHR6
CHR5
CHR4
CHR3
CHR2
CHR1
CHR0

CHR0

23 CVBS7

Y7

24 CVBS6

Y6

25 CVBS5

Y5

26 CVBS4

Y4

27 CVBS3

Y3

28 CVBS2

Y2

29 CVBS1

Y1

DEC_FI
DEC_RTC

GPSWO

65

MUXC

39

ODD

32

RTCO

1

SP

2

AP

35

37

V

SSA

19

V

SS1

38

V

SS2

51

V

SS3

67

V

SS4

V

DDA

V

DD1

V

DD2

V

DD3

V

DD4

5
18
28
52

SDA
SCL

40

SDA

41

SCL

64

FEIN

63

GPSWO

39

RSVRD

43

IICSA

66

GTBS

68

FSI

30 CVBS0

23

CVBS7

22

CVBS6

21

CVBS5

20

CVBS4

17

CVBS3

16

CVBS2

15

CVBS1

14

44
33

CVBS0

SDAT
XTAL

CVBS7
CVBS6
CVBS5
CVBS4
CVBS3
CVBS2
CVBS1
CVBS0

XTAL2

XTAL1

34

24

XTAL1

GPSW1

IN0

25

GPSW2

IN1

29

HSY

HSY

26

HCL

HCL

27

LL27

DEC_LLC

4

CREF

DEC_REF

36

LFCO

LFCO

3

RES

RES

CVBS0 to 7

R13

220 Ω

CHR0 to 7

Y0

42

CLK

31

CX12

0.1 µF

CCX4

0.1 µF

CX3

22 µF

OGND1

43

OGND2

18

DGND

3

36

25

1

12

13 24

48 37

AGND

41

V

CCO1

32

V

CCO2

21

V

CCD

10

V

CCA

R64

4.7 kΩ

V

CC

CX6
22 µF

CX5

0.1 µF

CX14

0.1 µF

60

44

10

26

27 43

91 61

PAD100

TEST PT

J10

V

CC

V

CC

V

CC

V

CCA

GND

PAD100

J24

GROUND

PAD100

J25

GROUND

PAD100
TEST PT

J9

V

CC

V

CCA

HEADER

4X2

8HH100

2
4
6
8

1 DEC_LLC

DEC_LLC2
DEC_CREF

3
5
7

JP16

SAA7197

20SOP300

U3

12

1

RES

MS

RES

R12

4.7 kΩ

CX13

0.1 µF

CX7

0.1 µF

C24

0.1 µF

15

16

CLKREF

LFCOSEL

LL3B

LL1 to 5B

3

PORD

4

V

SSA

6

V

SSD

9

V

SSD

10
20

13

V

SSD

18

V

SSD

V

DDA

V

DDD

V

DDD

5

11

LFCO
LFCO2

19

8

17

2

CE

R15

33 Ω

R16

33 Ω

R1433 Ω

R11

22 kΩ

7

LL1 to 5A
LL3A

14

RES

RES

C21

10 pF

C22

10 pF

C23

XTAL1

Y2

24.576 MHz
2SIP100

XTAL2

0.001 µF
L2
10 µH

1996 Feb 01 19

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

PACKAGE OUTLINE

UNIT

A

max.

A1A2A3b

p

cE

(1)

eH

E

LLpQZywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

1.60

0.20

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

7.1

6.9

0.5

9.15

8.85

0.69

0.59

0.95

0.55

7
0

o
o

0.12 0.10.21.0

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT313-2

93-06-15
94-12-19

D

(1) (1)(1)

7.1

6.9

H

D

9.15

8.85

E

Z

0.95

0.55

D

b

p

e

E

B

12

D

H

b

p

E

H

v

M

B

D

Z

D

A

Z

E

e

v

M

A

1

48

37

36

25

24

13

θ

A

1

A

L

p

Q

detail X

L

(A )

3

A

2

X

y

c

w

M

w

M

0 2.5 5 mm

scale

pin 1 index

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

1996 Feb 01 20

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all LQFP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering LQFP packages LQFP48 (SOT313-2),
LQFP64 (SOT314-2) or LQFP80 (SOT315-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Feb 01 21

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1996 Feb 01 22

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

NOTES

1996 Feb 01 23

Philips Semiconductors Product specification

YC 8-bit low-power analog-to-digital video
interface

TDA8758

NOTES

Philips Semiconductors – a worldwide company

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BUENOS AIRES, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Brazil: Rua do Rocio 220 - 5

th

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77621 BOGOTA, Tel. [phone],
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COPENHAGEN S, Tel. [phone], Fax. [phone]

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P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Piazza IV Novembre 3, 20124 MILANO,
Tel. [phone], Fax. [phone]

Japan: Philips Bldg13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,

Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,
KARACHI 75600, Tel. [phone],
Fax. [phone]

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
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Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,
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252148 KIEV, Tel.[phone], Fax. [phone]

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276 Bath Road, Hayes, MIDDLESEX UB3 5BX,
Tel. [phone], Fax. [phone]

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Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

Internet: http://www.semiconductors.philips.com/ps/
For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,
P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCDS47 © Philips Electronics N.V. 1996

All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.

Printed in The Netherlands

537021/1100/03/pp24 Date of release: 1996 Feb 01
Document order number: 9397 750 00606