Datasheet TDA8752H-8-C4, TDA8752H-8-C3, TDA8752H-8-C2, TDA8752H-8-C1, TDA8752H-6-C3 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of 1998 Aug 11
File under Integrated Circuits, IC02

1999 Mar 09

INTEGRATED CIRCUITS

TDA8752

Triple high speed Analog-to-Digital
Converter (ADC)

1999 Mar 09 2

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

FEATURES

• Triple 8-bit ADC

• Sampling rate up to 100 MHz

• IC controllable via a serial interface, which can be either

I2C-bus or 3-wire, selected via a TTL input pin

• IC analog voltage input from 0.4 to 1.2 V (p-p) to
produce full-scale ADC input of 1 V (p-p)

• 3 clamps for programming a clamping code between

−63.5 and +64 in steps of1⁄2LSB

• 3 controllable amplifiers: gain controlled via the serial

interface to produce a full scale resolution of

1

⁄2LSB

peak-to-peak

• Amplifier bandwidth of 250 MHz

• Low gain variation with temperature

• PLL, controllable via the serial interface to generate the

ADC clock, which can be locked to a line frequency from
15 to 280 kHz

• Integrated PLL divider

• Programmable phase clock adjustment cells

• Internal voltage regulators

• TTL compatible digital inputs and outputs

• Chip enable high-impedance ADC output

• Power-down mode

• Possibility to use up to four ICs in the same system,

using the I2C-bus interface, or more, using the 3-wire
serial interface

• 1 W power dissipation.

APPLICATIONS

• R, G and B high speed digitizing

• LCD panels drive

• LCD projection systems

• VGA and higher resolutions

• Using two ICs in parallel, higher display resolution can

be obtained; 200 MHz pixel frequency.

GENERAL DESCRIPTION

The TDA8752 is a triple 8-bit ADC with controllable
amplifiers and clamps for the digitizing of large bandwidth
RGB signals.

The clamp level, the gain and all of the other settings are
controlled via a serial interface (either I

2

C-bus or 3-wire

serial bus, selected via a logic input).
The IC also includes a PLL that can be locked on the

horizontal line frequency and generates the ADC clock.
The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the
ADC.

It is possible to set the TDA8752 serial bus address
between four fixed values, in the event that several
TDA8752 ICs are used in a system, using the I

2

C-bus
interface (for example, two ICs used in an odd/even
configuration).

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE SAMPLING

FREQUENCY

(MHz)

NAME DESCRIPTION VERSION

TDA8752H/6

QFP100

plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm

SOT317-2

60

TDA8752H/8 100

1999 Mar 09 3

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage for R, G and B channels 4.75 5.0 5.25 V

V

DDD

logic supply voltage for I2C-bus and 3-wire 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V

V

CCA(PLL)

analog PLL supply voltage 4.75 5.0 5.25 V

V

CCO(PLL)

output PLL supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 120 − mA

I

DDD

logic supply current for I2C-bus and 3-wire − 1.0 − mA

I

CCD

digital supply current − 40 − mA

I

CCO

output stages supply current f

CLK

= 100 MHz;

ramp input

− 6 − mA

I

CCA(PLL)

analog PLL supply current − 28 − mA

I

CCO(PLL)

output PLL supply current − 5 − mA

f

CLK

maximum clock frequency TDA8752/6 60 −−MHz

TDA8752/8 100 −−MHz

f

ref(PLL)

PLL reference clock frequency 15 − 280 kHz

f

VCO

VCO output clock frequency 12 − 100 MHz

INL DC integral non linearity from analog input to

digital output; full-scale;
ramp input;
f

CLK

= 100 MHz

−±0.5 ±1.5 LSB

DNL DC differential non linearity from analog input to

digital output; full-scale;
ramp input;
f

CLK

= 100 MHz

−±0.5 ±1.0 LSB

∆G

amp

/T amplifier gain stability as a function of

temperature

V

ref

= 2.5 V with

100 ppm/°C maximum

−−200 ppm/°C

B amplifier bandwidth −3 dB; T

amb

=25°C 250 −−MHz

t

set

settling time of the ADC block plus AGC input signal settling

time < 1 ns; T

amb

=25°C

−−6ns

DR

PLL

PLL divider ratio 100 − 4095

P

tot

total power consumption f

CLK

= 100 MHz;

ramp input

− 1.0 − W

j

PLL(rms)

maximum PLL phase jitter (RMS value) f

ref

= 66.67 kHz;

f

CLK

= 100 MHz

− 0.3 − ns

1999 Mar 09 4

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

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BLOCK DIAGRAM

bo

ok, full pagewidth

MGG363

SERIAL

INTERFACE

I

2

C-BUS

OR

3-WIRE

I

2

C/3W

I

2

C-bus; 1-bit

(H level)

REGULATOR

PLL

PWDWN

CP

CZ

CKREF

COAST

INV

CKEXT

CKREFO

CKAO

CKBO

CKADCO

B0 to B7
BOR

R0 to R7

OE

G0 to G7

BBOT

BCLP

RBOT

RCLP

GBOT

GCLP

DEC2DEC1HSYNCn.c.

HSYNCI

ADD2

BIN

BGAINC

BAGC

GAGC

V

ref

RDEC

RIN

RGAINC

RAGC

GDEC

GIN

GGAINC

BDEC

ADD1

SEN
SCL
SDA

DIS

BLUE CHANNEL

GREEN CHANNEL

TDA8752

RED CHANNEL

ADC

GOR

ROR

MUX

CLAMP

OUTPUTS

6

V

CCAR

11

V

CCAG

19

V

CCAB

27

V

DDD

40

AGNDG

21

V

CCOG

69

V

CCOB

59

V

CCOR

79

V

CCD

95

V

CCA(PLL)

99

V

CCO(PLL)

85

CLP

89

AGNDR

13

V

SSD

41

AGNDB

29

OGNDG

60

OGNDR

70

AGNDPLL

96

OGNDB

48

DGND

86

OGNDPLL

82

12
10

3

22
24

28
26

20
18

14
16

33

34

38

TDO
TCK

35

36

42
39
37

90

1, 5, 30, 31, 43 , 44
50, 51, 100

4 2 88 97 98

32

8

9
7

71 to 78

45

17
15

61 to 68

87

46

25
23

49, 52 to 58

47

93
94

92

80

91

84
83

81

Fig.1 Block diagram.

1999 Mar 09 5

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Fig.2 Red channel diagram.

handbook, full pagewidth

CLP RAGC CLKADC

R0 to R7

ROR

RBOT

ADC

AGC

MUX

1

CLAMP

CONTROL

REGISTER

OUTPUTS

ADC

D ≥ R

R

D

V

CCAR

DAC

DAC

RCLP

RIN

V

ref

V

P

8

8

8

8

7

REGISTER

FINE GAIN ADJUST

5

I2C-bus; 5 bits

(Fr)

I

2

C-bus; 8 bits

(Or)

REGISTER

COARSE GAIN ADJUST

HSYNCI

I

2

C-bus; 7 bits

(Cr)

I

2

C-BUS

SERIAL

RGAINC

1

OE

150

kΩ

3
kΩ

45
kΩ

MGG364

1999 Mar 09 6

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Fig.3 PLL diagram.

handbook, full pagewidth

MGG370

PHASE

FREQUENCY

DETECTOR

I

2

C-bus; 5 bits

(Ip, Up, Do)

I

2

C-bus; 1 bit

(V level)

I

2

C-bus; 12 bits (Di)

I

2

C-bus;

1 bit (Ckb)

phase selector A
I

2

C-bus;

5 bits (Pa)

I

2

C-bus;

1 bit (Cka)

edge selector
I

2

C-bus;
1 bit
(edge)

CLK
ADC

I

2

C-bus;

2 bits (VCO)

C

z

loop filter
I

2

C-bus;

3 bits (Z)

12 to

100 MHz

DIV N (100 to 4095)

0°/180°

MUX

SYNCHRO

C

p

CZ CP

COAST

CKEXT INV

VCO

CKADCO

CKAO

CKREFO

CKREF

phase selector B

I

2

C-bus; 5 bits (Pb)

CKBO

1999 Mar 09 7

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
DEC2 2 main regulator decoupling input
V

ref

3 gain stabilizer voltage reference input
DEC1 4 main regulator decoupling input
n.c. 5 not connected
RAGC 6 red channel AGC output
RBOT 7 red channel ladder decoupling input (BOT)
RGAINC 8 red channel gain capacitor input
RCLP 9 red channel gain clamp capacitor input
RDEC 10 red channel gain regulator decoupling input
V

CCAR

11 red channel gain analog power supply
RIN 12 red channel gain analog input
AGNDR 13 red channel gain analog ground
GAGC 14 green channel AGC output
GBOT 15 green channel ladder decoupling input (BOT)
GGAINC 16 green channel gain capacitor input
GCLP 17 green channel gain clamp capacitor input
GDEC 18 green channel gain regulator decoupling input
V

CCAG

19 green channel gain analog power supply
GIN 20 green channel gain analog input
AGNDG 21 green channel gain analog ground
BAGC 22 blue channel AGC output
BBOT 23 blue channel ladder decoupling input (BOT)
BGAINC 24 blue channel gain capacitor input
BCLP 25 blue channel gain clamp capacitor input
BDEC 26 blue channel gain regulator decoupling input
V

CCAB

27 blue channel gain analog power supply
BIN 28 blue channel gain analog input
AGNDB 29 blue channel gain analog ground
n.c. 30 not connected
n.c. 31 not connected
I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire serial bus (active LOW)
ADD1 33 I2C-bus address control input 1
ADD2 34 I2C-bus address control input 2
TCK 35 scan test mode (active HIGH)

1999 Mar 09 8

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

TDO 36 scan test output
DIS 37 I2C and 3W disable control input (disable at HIGH level)
SEN 38 select enable for 3-wire serial bus input (see Fig.10)
SDA 39 I2C/3W serial data input
V

DDD

40 logic I2C/3W digital power supply
V

SSD

41 logic I2C/3W digital ground
SCL 42 I

2

C/3W serial clock input
n.c. 43 not connected
n.c. 44 not connected
ROR 45 red channel ADC output bit out of range
GOR 46 green channel ADC output bit out of range
BOR 47 blue channel ADC output bit out of range
OGNDB 48 blue channel ADC output ground
B0 49 blue channel ADC output bit 0 (LSB)
n.c. 50 not connected
n.c. 51 not connected
B1 52 blue channel ADC output bit 1
B2 53 blue channel ADC output bit 2
B3 54 blue channel ADC output bit 3
B4 55 blue channel ADC output bit 4
B5 56 blue channel ADC output bit 5
B6 57 blue channel ADC output bit 6
B7 58 blue channel ADC output bit 7 (MSB)
V

CCOB

59 blue channel ADC output power supply
OGNDG 60 green channel ADC output ground
G0 61 green channel ADC output bit 0 (LSB)
G1 62 green channel ADC output bit 1
G2 63 green channel ADC output bit 2
G3 64 green channel ADC output bit 3
G4 65 green channel ADC output bit 4
G5 66 green channel ADC output bit 5
G6 67 green channel ADC output bit 6
G7 68 green channel ADC output bit 7 (MSB)
V

CCOG

69 green channel ADC output power supply
OGNDR 70 red channel ADC output ground
R0 71 red channel ADC output bit 0 (LSB)

SYMBOL PIN DESCRIPTION

1999 Mar 09 9

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

R1 72 red channel ADC output bit 1
R2 73 red channel ADC output bit 2
R3 74 red channel ADC output bit 3
R4 75 red channel ADC output bit 4
R5 76 red channel ADC output bit 5
R6 77 red channel ADC output bit 6
R7 78 red channel ADC output bit 7 (MSB)
V

CCOR

79 red channel ADC output power supply
CKREFO 80 reference output clock resynchronized horizontal pulse
CKAO 81 PLL clock output 3 (in phase with reference output clock)
OGNDPLL 82 PLL digital ground
CKBO 83 PLL clock output 2
CKADCO 84 PLL clock output 1 (in phase with internal ADC clock)
V

CCO(PLL)

85 PLL output power supply
DGND 86 digital ground
OE 87 output enable not (when OE is HIGH, the outputs are in high-impedance)
PWDWN 88 power-down control input (IC is in power-down mode when this pin is HIGH)
CLP 89 clamp pulse input (clamp active HIGH)
HSYNC 90 horizontal synchronization input pulse
INV 91 PLL clock output inverter command input (invert when HIGH)
CKEXT 92 external clock input
COAST 93 PLL coast command input
CKREF 94 PLL reference clock input
V

CCD

95 digital power supply
AGNDPLL 96 PLL analog ground
CP 97 PLL filter input
CZ 98 PLL filter input
V

CCAPLL

99 PLL analog power supply
n.c. 100 not connected

SYMBOL PIN DESCRIPTION

1999 Mar 09 10

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Fig.4 Pin configuration.

handbook, full pagewidth

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

CKREFO
V

CCOR

R7
R6
R5
R4
R3
R2
R1
R0
OGNDR

V

CCOG

G7
G6
G5
G4
G3
G2
G1
G0
OGNDG

V

CCOB

B7
B6
B5
B4
B3
B2
B1
n.c.

n.c.

DEC2

V

ref

DEC1

n.c.
RAGC
RBOT

RGAINC

RCLP

RDEC

V

CCAR

RIN

AGNDR

GAGC

GBOT

GGAINC

GCLP
GDEC

V

CCAG

GIN

AGNDG

BAGC
BBOT

BGAINC

BCLP

BDEC

V

CCAB

BIN

AGNDB

n.c.

n.c.

I

2

C/3W

ADD1

ADD2

TCK

TDO

DIS

SEN

SDA

V

DDD

V

SSD

SCL

n.c.

n.c.

ROR

GOR

BOR

OGNDB

B0

n.c.

n.c.

V

CCA(PLL)

CZCPAGNDPLL

V

CCD

CKREF

COAST

CKEXT

INV

HSYNC

CLP

PWDWNOEDGND

V

CCO(PLL)

CKADCO

CKBO

OGNDPLL

CKAO

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

100

99989796959493929190898887868584838281

31323334353637383940414243444546474849

50

MGG362

TDA8752

1999 Mar 09 11

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

FUNCTIONAL DESCRIPTION

This triple high-speed 8-bit ADC is designed to convert
RGB signals, from a PC or work station, into data used by
a LCD driver (pixel clock up to 200 MHz, using 2 ICs).

IC analog video inputs

The video inputs are internally DC polarized. These inputs
are AC coupled externally.

Clamps

Three independent parallel clamping circuits are used to
clamp the video input signals on the black level and to
control the brightness level. The clamping code is
programmable between code −63.5 and +64 in steps of

1

⁄2LSB. The programming of the clamp value is achieved

via an 8-bit DAC. Each clamp must be able to correct an
offset from±0.1 V to±10 mV within 300 ns, and correct the
total offset in 10 lines.

The clamps are controlled by an external TTL positive
going pulse (pin CLP). The drop of the video signal is
<1 LSB.

Normally, the circuit operates with a 0 code clamp,
corresponding to the 0 ADC code. This clamp code can be
changed from −63.5 to +64 as represented in Fig.7,
in steps of1⁄2LSB. The digitized video signal is always
between code 0 and code 255 of the ADC.

Variable gain amplifier

Three independent variable gain amplifiers are used to
provide, to each channel, a full-scale input range signal to
the 8-bit ADC. The gain adjustment range is designed so
that, for an input range varying from 0.4 to 1.2 V (p-p), the
output signal corresponds to the ADC full-scale input of
1 V (p-p).

To ensure that the gain does not vary over the whole
operating temperature range, an external reference of
+2.5 V DC, (V

ref

with a 100 ppm/°C maximum variation)
supplied externally, is used to calibrate the gain at the
beginning of each video line before the clamp pulse using
the following principle.

A differential of 0.156 V (p-p) (1⁄16V

ref

) reference signal is

generated internally from the reference voltage (V

ref

).
During the synchronization part of the video line, the
multiplexer, controlled by the TTL synchronization signal
(HSYNCI, coming from HSYNC; see Fig.1) with a width
equal to one of the video synchronization signals
(e.g. signal coming from a synchronization separator), is
switched between the two amplifiers.

The output of the multiplexer is either the normal video
signal or the 0.156 V reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a
pre-set value loaded in a register. Depending on the result
of the comparison, the gain of the variable gain amplifiers
is adjusted (coarse gain control; see Figs 2 and 8).
The three 7-bit registers receive data via a serial interface
to enable the gain to be programmed.

The pre-set value loaded in the 7-bit register is chosen
between approximately 67 codes to ensure the full-scale
input range (see Fig.8). A contrast control can be achieved
using these registers. In this case care should be taken to
stay within the allowed code range (32 to 99).

A fine correction using three 5-bit DACs, also controlled via
the serial interface, is used to finely tune the gain of the
three channels (fine gain control; see Figs 2 and 9) and to
compensate the channel-to-channel gain mismatch.

With a full scale ADC input, the resolution of the fine
register corresponds to

1

⁄2LSB peak-to-peak variation.

To use these gain controls correctly, it is recommended to
fix the coarse gain (to have a full-scale ADC input signal)
to within 4LSB and then adjust it with the fine gain.
The gain is adjusted during HSYNC. During this time the
output signal is not related to the amplified input signal.
The outputs, when the coarse gain system is stable, is
related to the programmed coarse code (see Fig.8).

ADCs

The ADCs are 8-bit with a maximum clock frequency of
100 Msps. The ADCs input range is 1 V (p-p) full-scale.
One out of range bit exists per channel (ROR, GOR and
BOR). It will be at logic 1 when the signal is out of range of
the full scale of the ADCs.

Pipeline delay in the ADCs is 1 clock cycle from sampling
to data output.

The ADCs reference ladders regulators are integrated.

ADC outputs

ADC outputs are straight binary. An output enable pin
(

OE; active LOW) enables the output status between
active and high-impedance (OE = HIGH) to be switched;
it is recommended to load the outputs with a 10 pF
capacitive load. The timing must be checked very carefully
if the capacitive load is more than 10 pF.

1999 Mar 09 12

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Phase-locked loop

The ADCs are clocked either by an internal PLL locked to
the CKREF clock, (all of the PLL is on-chip except the loop
filter capacitance) or an external clock, CKEXT. Selection
is performed via the serial interface bus.

The reference clock (CKREF) range is between
15 and 280 kHz. Consequently, the VCO minimum
frequency is 12 MHz and the maximum frequency
100 MHz for the TDA8752/8 and 60 MHz for the
TDA8752/6. The gain of the VCO part can be controlled via
the serial interface, depending on the frequency range to
which the PLL is locked.

To increase the bandwidth of the PLL, the charge pump
current, controlled by the serial interface, must also be
increased. The relationship between the frequency and
the current is given by the following equation:

Where:

f

n

= the natural PLL frequency
KO= the VCO gain
N = the division number
Cz and CP= capacitors of the PLL filter.

The other PLL equation is as follows:

f

n

1

2π

------ -

K

OIP

Cz( CP) N+

---------------------------------- -=

Where:

fz= loop filter zero frequency
R = the chosen resistance for the filter
ξ = the damping factor.

Different resistances for the filter can be programmed via
the serial interface. To have better performances, the PLL
parameters should be chosen so that:

fn/f

ref

≅ 0.05

ξ≅1.5.

It is possible to control (independently) the phase of the
ADC clock and the phase of an additional clock output
(which could be used to drive a second TDA8752).
For this, two serial interface-controlled digital phase-shift
controllers are included (controlled by 5-bit registers,
phase shift controller steps are 11.25° each on the whole
PLL frequency range).

CKREF is resynchronized, by the synchro block, on the
CKAO clock. The output is CKREFO (LOW during 8 clock
periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO
and CKADCO. The timing is given in Fig.5.

f

z

1

2π R× Cz×

------------------------------

and ξ

1
2

-- -

f

n

f

z

--- -

×=







=

t

CKAO=tCLK(buffer)+tphase selector

(t

CLK(buffer)

= 10 ns and t

phase selector

= × T

CLK(pixel)

).

t

CKREFO

= either t

CKAO

if phase A ≥01000 or t

CKAO+TCLK(pixel)

if phase A <01000.

t

phase selector

2π

------------------------------ -

Fig.5 Timing.

ndbook, full pagewidth

t

CKAO

t

CKREFO

MBK773

CKREF

CKAO

CKREFO

1999 Mar 09 13

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

The COAST pin is used to disconnect the PLL phase
frequency detector during the frame flyback or the
unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.

The clock output is able to drive an external 10 pF load
(for the on-chip ADCs).

The PLL can be used in three different methods:

1. The IC can be used as stand-alone with a sampling
frequency of up to 100 MHz for the TDA8752/8 and up
to 60 MHz for the TDA8752/6.

2. When an RGB signal is at a pixel frequency exceeding
100 to 200 MHz, it is possible to follow one of the two
possibilities given below;

a) Using one TDA8752; the sampling rate can be

reduced by a factor of two, by sampling the even
pixels in the even frame and the odd pixels in the
odd frame. The INV pin is used to toggle between
frames.

b) Using two TDA8752s the PLL of the master

TDA8752 is used to drive both ADC clocks.
The PLL of the slave TDA8752 is disconnected and
the CKBO of the master TDA8752 is connected to
pin CKEXT of both TDA8752.

The master TDA8752 is used to sample the even
pixels and the slave TDA8752 for odd pixels, using
a 180° phase shift between the clocks (CKADCO
pins). The master chip has its INV pin LOW while
the slave chip has its INV pin HIGH, which
guarantees the 180° shift ADC clock drive. It is then
necessary to adjust phase B of the master chip.
Special care should be taken with the quality of the
input signal (input setting time).

If CKREFO output signal at the master chip is
needed, it is possible to use one of the two phase A
values in order to avoid set-up and hold problems
in the SYNCHRO function; e.g.
PHASEA = 100000 and PHASEA = 111111.

1999 Mar 09 14

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Fig.6 Dual TDA8752 solution for pixel clock rate with a single phase adjustment (100 to 200 MHz).

Slave at 180° phase shift with respect to pin CKADCO of the master TDA8752.

handbook, full pagewidth

MBK772

I2C-bus;

1 bit (Ckb)

(Ckb = 1)

phase selector A

I

2

C-bus;

5 bits (Pa)

I

2

C-bus;

1 bit (Cka)

(Cka = 1)

CLK
ADC

12 to

100 MHz

PLL

Master TDA8752

(even pixels)

0°/180°

MUX

SYNCHRO

COAST CKEXT

INV

CKADCO

CKAO

CKREFO

CKREF

phase selector B

I

2

C-bus; 5 bits (Pb)

CKBO

I2C-bus;

1 bit (Ckb)

(Ckb = 0)

phase selector A

I

2

C-bus;

5 bits (Pa)

I

2

C-bus;

1 bit (Cka)

(Cka = 1)

CLK
ADC

12 to

100 MHz

PLL

Slave TDA8752

(odd pixels)

0°/180°

MUX

SYNCHRO

COAST CKEXT INV

5 V

CKADCO

CKAO

CKREFO

CKREF

phase selector B

I

2

C-bus; 5 bits (Pb)

CKBO

1999 Mar 09 15

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

I2C-bus and 3-wire serial bus interface

The I2C-bus and 3-wire serial buses control the status of the different control DACs and registers. Control pin DIS
enables or disables the full serial interface function (disable at HIGH level). Four ICs can be used in the same system
and programmed by the same bus. Therefore, two pins (ADD1 and ADD2) are available to set each address respectively,
for use with the I2C-bus interface. All programming is described in Chapter “I2C-bus and 3-wire interfaces”.

Fig.7 Clamp definition.

handbook, full pagewidth

digitized

video

signal

video signal

CLP

clamp

programming

code 64
code 0

255

code −63.5

MGG368

Fig.8 Coarse gain control.

handbook, full pagewidth

MGG366

128

160

227

255

0

32

99

127

G

(max)

G

(min)

ADC output

code

N

coarse
code

coarse

register

value

(67 codes)

0.2

0.6

V

i (p-p)

2

0.156 =

V

ref

16

1999 Mar 09 16

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Fig.9 Fine gain correction for a coarse gain G

NCOARSE

.

handbook, full pagewidth

MGG367

128

160

227

255

G

(max)

G

NCOARSE

N

COARSE

G

(min)

ADC

output code

coarse
register

value

(67 codes)

N

FINE

= 31

N

FINE

= 0

V

ref

1999 Mar 09 17

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

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I

2

C-BUS AND 3-WIRE INTERFACES

Register definitions

The configuration of the different registers is as follows:

Table 1 I

2

C-bus and 3-wire registers

All the registers are defined by a sub-address of 8 bits; bit A4 refers to the mode which is used with the I

2

C-bus interface; bits Sa3 to Sa0 are the

subaddresses of each register.
The bit mode, used only with the I2C-bus, enables two modes to be programmed:

• If Mode= 0, each register is programmed independently by giving its sub-address and its content

• If Mode= 1, all the registers are programmed one after the other by giving this initial condition (xxx1 1111) as the sub-address state; thus, the

registers are charged following the predefined sequence of 16 bytes (from sub-address 0000 to 1101).

FUNCTION

NAME

SUB-ADDRESS BIT DEFINITION

DEFAULT

VALUE

A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB

SUBADDR −−−−−−−− X X X Mode Sa3 Sa2 Sa1 Sa0 xxx10000
OFFSETR XXXX0000Or7Or6Or5Or4Or3Or2Or1Or001111111
COARSER XXXX0001 X Cr6Cr5Cr4Cr3Cr2Cr1Cr0x010 0000
FINER XXXX0010 X X XFr4Fr3Fr2Fr1Fr0xxx0 0000
OFFSETG XXXX0011Og7Og6Og5Og4Og3Og2Og1Og001111111
COARSEG XXXX0100 X Cg6Cg5Cg4Cg3Cg2Cg1Cg0x010 0000
FINEG XXXX0101 X X XFg4Fg3Fg2Fg1Fg0xxx0 0000
OFFSETB XXXX0110Ob7Ob6Ob5Ob4Ob3Ob2Ob1Ob001111111
COARSEB XXXX0111 X Cb6Cb5Cb4Cb3Cb2Cb1Cb0x010 0000
FINEB XXXX1000 X X XFb4Fb3Fb2Fb1Fb0xxx0 0000
CONTROL XXXX1001V level H level edge Up Do Ip2 Ip1 Ip0 0000 0100
VCO XXXX1010 Z2 Z1Z0Vco1 Vco0 Di11 Di10 Di9 0110 0001
DIVIDER

(LSB)

XXXX1011Di8Di7Di6Di5Di4Di3Di2Di11001 0000

PHASEA XXXX1100 X Di0CkaPa4Pa3Pa2Pa1Pa0x000 0000
PHASEB XXXX1101 X XCkbPb4Pb3Pb2Pb1Pb0xx00 0000

1999 Mar 09 18

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

OFFSET REGISTER
This register controls the clamp level for the RGB

channels. The relationship between the programming
code and the level of the clamp code is given in Table 2.

Table 2 Coding

The default programmed value is:

• Programmed code = 127

• Clamp code = 0

• ADC output = 0.

C

OARSE AND FINE REGISTERS

These two registers enable the gain control, the AGC gain
with the coarse register and the reference voltage with the
fine register. The coarse register programming equation is
as follows:

=

Where: V

ref

= 2.5 V.

The gain correspondence is given in Table 3. The gain is
linear with reference to the programming code (N

FINE

= 0).

PROGRAMMED

CODE

CLAMP CODE ADC OUTPUT

0 −63.5 underflow
1 −63
2 −62.5

↓↓

127 0 0

↓↓↓

254 63.5 63 or 64
255 64 64

GAIN

N

COARSE

1+

V

ref

1

N

FINE

32 16×

-------------------

–





----------------------------------------------

1

16

------

×=

N

COARSE

1+

V

ref

512 N

FINE

–()

-------------------------------------------------

32×

Table 3 Gain correspondence (COARSE)

The default programmed value is as follows:

• N

COARSE

=32

• Gain = 0.825

• Vi to be full-scale = 1.212.

To modulate this gain, the fine register is programmed
using the above equation. With a full-scale ADC input, the
fine register resolution is a

1

⁄2LSB peak-to-peak

(see Table 4 for N

COARSE

= 32).

Table 4 Gain correspondence (FINE)

The default programmed value is: N

FINE

=0.

C

ONTROL REGISTER

COAST and HSYNC signals can be inverted by setting the
I2C-bus control bits V level and H level respectively. When
V level and H level are set to zero respectively, COAST
and HSYNC are active HIGH.

The bit ‘edge’ defines the rising or falling edge of CKREF
to synchronise the PLL. It will be on the rising edge if the
bit is at logic 0 and on the falling edge if the bit is at logic 1.

The bits Up and Do are used for the test, to force the
charge pump current. These bits have to be logic 0 during
normal use.

The bits Ip0, Ip1 and Ip2 control the charge pump current,
to increase the bandwidth of the PLL, as shown in Table 5.

N

COARSE

GAIN

Vi TO BE

FULL-SCALE

32 0.825 1.212
99 2.5 0.4

N

FINE

GAIN

Vi TO BE

FULL-SCALE

0 0.825 1.212

31 0.878 1.139

1999 Mar 09 19

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Table 5 Charge-pump current control

The default programmed value is as follows:

• Charge pump current = 100 µA

• Test bits: no test mode; bits Up and Do at logic 0

• Rising edge of CKREF: bit edge at logic 0

• COAST and HSYNC inputs are active HIGH: V level and

H level at logic 0.

VCO

REGISTER

The bits Z2, Z1 and Z0 enable the internal resistance for
the VCO filter to be selected.

Table 6 VCO register bits

Ip2 Ip1 Ip0

CURRENT

(µA)

0 0 0 6.25
0 0 1 12.5
010 25
011 50
100 100
101 200
110 400
111 700

Z2 Z1 Z0

RESISTANCE

(kΩ)

0 0 0 high impedance
001 128
010 32
011 16
100 8
101 4
110 2
111 1

Table 7 VCO gain control

The bits V

CO1

and V

CO0

control the VCO gain.

The default programmed value is as follows:

• Internal resistance = 16 kΩ

• VCO gain = 15 MHz/V.

D

IVIDER REGISTER

This register controls the PLL frequency. The bits are the
LSB bits.

The default programmed value is 0011 0010 0000 = 800.
The MSB bits (Di11, Di10, Di9) and the LSB bit (Di0) have

to be programmed before the bits Di8 to Di1 to have the
required divider ratio. The bit Di0 is used for the parity
divider number = Di0 = 0 = even number Di0 = 1 = odd
number. It should be noted that if the I2C-bus programming
is done in mode = 1 and the bit Di0 has to be toggled, then
the registers have to be loaded twice to have the update
divider ratio.

P

OWER-DOWN MODE

• When the supply is completely switched off, the
registers are set to their default values; in that event they
have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)

• When the device is in power-down mode, the previously
programmed register values remain unaffected.

PHASEA

AND PHASEB REGISTERS

The bit Cka is logic 0 when the used clock is the PLL clock,
and logic 1 when the used clock is the external clock.

The bit Ckb is logic 0 when the second clock is not used.
The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program

the phase shift for the clock, CKADCO, CKAO and CKBO
(see Table 8).

V

CO1

V

CO0

VCO gain

(MHz/V)

PIXEL CLOCK

FREQUENCY

RANGE (MHz)

1 0 60 10 to 17
0 1 30 17 to 35
1 0 60 35 to 60
1 1 100 60 to 100

1999 Mar 09 20

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Table 8 Phase registers bits

The default programmed value is as follows:

• No external clock: CKA at logic 0

• No use of the second clock: CKB at logic 0

• Phase shift for CKAO and CKADCO = 0°

• Phase shift for CKBO = 0°.

I

2

C-bus protocol

Table 9 I

2

C-bus address

The I

2

C-bus address of the circuit is 10011 xx0.

Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752s can be used on the same
system, using the addresses for ADD1 and ADD2 with the I2C-bus. The A0 bit must always be equal to logic 0 because
it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences
are available, see Tables 10 and 11.

Table 10 Address sequence for mode 0

Where: S = START condition, ACK = acknowledge and P = STOP condition.

Table 11 Address sequence for mode 1

Where: S = START condition, ACK = acknowledge and P = STOP condition.

Pa4, Pb4 Pa3, Pb3 Pa2, Pb2 Pa1, Pb1 Pa0, Pb0 PHASE SHIFT (°)

000000

0000111.25

↓↓↓↓↓↓
↓↓↓↓↓↓

11110337.5

11111348.75

A7 A6 A5 A4 A3 A2 A1 A0

10011ADD2 ADD1 0

S IC ADDRESS ACK SUBADDRESS

REGISTER1

ACK DATA

REGISTER1

(see Table 1)

ACK SUBADDRESS

REGISTER2

ACK .... P

S IC ADDRESS ACK SUBADDRESS

xxx1 1111

ACK DATA

REGISTER1

(see Table 1)

ACK DATA

REGISTER2

ACK .... P

1999 Mar 09 21

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

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3-wire protocol

For the 3-wire serial bus the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen
register (see Table 1). The acquisition is achieved via SEN.

Using the 3-wire interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to validate the circuits.

MGG365

t

s3W

= 100 ns

t

h3W

= 100 ns

t

r3W

= 600 ns

100 ns

1199

XXXXA3A2A1A0XD7D6D5D4D3D2D1D0X

SEN

SCL

SDA

Fig.10 3-wire serial bus protocol.

1999 Mar 09 22

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

DDD

logic input voltage −0.3 +7.0 V

V

CCO

output stages supply voltage −0.3 +7.0 V

∆V

CC

supply voltage differences

V

CCA

− V

CCD

−1.0 +1.0 V

V

CCO

− V

CCD

, V

CCO

− V

DDD

−1.0 +1.0 V

V

CCA

− V

DDD

, V

CCD

− V

DDD

−1.0 +1.0 V

V

CCA

− V

CCO

−1.0 +1.0 V

V

i(RGB)

RGB input voltage range referenced to AGND −0.3 +7.0 V

I

o

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 70 °C

T

j

junction temperature − 150 °C

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 52 K/W

1999 Mar 09 23

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

CHARACTERISTICS

V

CCA

= V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96 = 4.75 to 5.25 V; V

CCD

= V95

referenced to DGND (V86) = 4.75 to 5.25 V; V

DDD

= V40 referenced to V

SSD

(V41) = 4.75 to 5.25 V; V

CCO

= V59

(or V69, V79 or V85) referenced to OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and V

SSD

short circuited together. T

amb

= 0 to 70 °C; typical values measured at V

CCA=VDDD=VCCD=VCCO

= 5 V and

T

amb

=25°C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

DDD

logic supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current − 120 − mA

I

DDD

logic supply current for
I2C-bus and 3-wire

− 1.0 − mA

I

CCD

digital supply current − 40 − mA

I

CCO

output stages supply current ramp input; f

CLK

= 100 MHz − 6 − mA

I

CCO(PLL)

output PLL supply current − 5 − mA

I

CCA(PLL)

analog PLL supply current − 28 − mA

∆V

CC

supply voltage differences

V

CCA

− V

CCD

−0.25 − +0.25 V

V

CCO

− V

CCD

, V

CCO

− V

DDD

−0.25 − +0.25 V

V

CCA

− V

DDD

, V

CCD

− V

DDD

−0.25 − +0.25 V

V

CCA

− V

CCO

−0.25 − +0.25 V

P

tot

total power consumption ramp input; f

CLK

= 100 MHz − 1.0 − W

P

pd

power consumption in
power-down mode

− 87 − mW

R, G and B amplifiers

B bandwidth −3 dB; T

amb

=25°C 250 −−MHz

t

set

settling time of the block ADC
plus AGC

full-scale (black-to-white)
transition; input signal
settling time<1ns;
1 to 99%; T

amb

=25°C

− 4.5 6 ns

G

NCOARSE

coarse gain range V

ref

= 2.5 V; minimum
coarse gain register;
code = 32; (see Fig.8)

−−1.67 − dB

maximum coarse gain
register; code = 99;
(see Fig.8)

− 8 − dB

1999 Mar 09 24

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

G

FINE

fine gain correction range fine register input code = 0;

(see Fig.9)

− 0 − dB

fine register input
code = 31; (see Fig.9)

−−0.5 − dB

∆G

amp

/T amplifier gain stability as a

function of temperature

V

ref

= 2.5 V with
100 ppm/°C maximum
variation

−− 200 ppm/°C

I

GC

gain current −±20 −µA

t

stab

amplifier gain adjustment
speed

HSYNC active; capacitors
on pins 8, 16 and 24 = 22 nF

− 25 − mdB/µs

V

i(p-p)

input voltage range
(peak-to-peak value)

corresponding to full-scale
output

0.4 − 1.2 V

t

r(Vi)

input voltage rise time fi= 100 MHz; square wave −− 2.5 ns

t

f(Vi)

input voltage fall time fi= 100 MHz; square wave −− 2.5 ns

G

E(rms)

channel-to-channel gain
matching (RMS value)

maximum coarse gain;
T

amb

=25°C

− 1 − %

minimum coarse gain;
T

amb

=25°C

− 2 − %

Clamps

P

CLP

precision black level noise on RGB

channels = 10 mV (max.)
(RMS value); T

amb

=25°C

−1 − +1 LSB

t

COR1

clamp correction time to within

±10 mV

±100 mV black level input

variation;
clamp capacitor = 4.7 nF

−− 300 ns

t

COR2

clamp correction time to less
than 1 LSB

±100 mV black level input
variation;
clamp capacitor = 4.7 nF

−− 10 lines

t

W(CLP)

clamp pulse width 500 − 2000 ns

CLP

E

channel-to-channel clamp
matching

−1 − +1 LSB

A

off

code clamp reference clamp register input

code = 0

−−63.5 − LSB

clamp register input
code = 255

− 64 − LSB

Phase-locked loop

j

PLL(rms)

long term PLL jitter
(RMS value)

f

CLK

= 60 MHz; see Table 13 − 450 − ps

f

CLK

= 100 MHz;

see Table 13

− 360 − ps

DR divider ratio 100 − 4095
f

ref

reference clock frequency
range

15 − 280 kHz

f

PLL

output clock frequency range 12 − 100 MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Mar 09 25

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

t

COASTmax

maximum coast mode time −− 40 lines

t

recap

PLL recapture time when coast mode is aborted − 3 − lines

t

cap

PLL capture time in start-up conditions −− 5ms

Φ

step

phase shift step T

amb

=25°C − 11.25 − deg

ADCs

f

s

maximum sampling frequency TDA8752/6 60 −−MHz

TDA8752/8 100 −−MHz

INL DC integral non linearity from IC analog input to

digital output; ramp input;
f

CLK

= 100 MHz

−±0.5 ±1.5 LSB

DNL DC differential non linearity from IC analog input to

digital output; ramp input;
f

CLK

= 100 MHz

−±0.5 ±1.0 LSB

ENOB effective number of bits from IC analog input to

digital output; 10 kHz sine
wave input; ramp input;
f

CLK

= 100 MHz; note 1

− 7.4 − bits

Signal-to-noise ratio

S/N signal-to-noise ratio maximum gain;

f

CLK

= 100 MHz

− 45 − dB

minimum gain;
f

CLK

= 100 MHz

− 44 − dB

Spurious free dynamic range

SFDR spurious free dynamic range maximum gain;

f

CLK

= 100 MHz

− 60 − dB

minimum gain;
f

CLK

= 100 MHz

− 60 − dB

Clock timing output (CKADCO, CKBO and CKAO)

η

ext

ADC clock duty cycle 100 MHz output 45 50 55 %

f

CLK(max)

maximum clock frequency 100 −−MHz

Clock timing input (CKEXT)

f

CLK(max)

maximum clock frequency 100 −−MHz

t

CPH

clock pulse width HIGH 3.6 −−ns

t

CPL

clock pulse width LOW 4.5 −−ns

t

d(CLKO)

delay from CKEXT to
CKADCO

INV set to LOW 13.6 14.7 15.2 ns
INV set to HIGH −−ns

∆t

sample

time difference between
samples

operating in the same supply
and temperature condition

− 0.1 0.3 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

CLK

2

----------

1999 Mar 09 26

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Data timing (see Fig.11); f

CLK

= 100 MHz; CL= 10 pF; note 2

t

d(s)

sampling delay time referenced to CKADCO −− − ns

t

d(o)

output delay time −−3.3 −2.6 ns

t

h(o)

output hold time 4.6 5.5 − ns

3-state output delay time; (see Fig.12)
t

dZH

output enable HIGH − 12 − ns

t

dZL

output enable LOW − 10 − ns

t

dHZ

output disable HIGH − 50 − ns

t

dLZ

output disable LOW − 65 − ns

PLL clock output

V

OL

LOW-level output voltage Io=1mA − 0.3 0.8 V

V

OH

HIGH-level output voltage Io= − 1 mA 2.4 3.5 − V

I

OL

LOW-level output current VOL= 0.4 V − 2 − mA

I

OH

HIGH-level output current VOH= 2.7 V −−0.4 − mA

ADC data outputs

V

OL

LOW-level output voltage Io=1mA − 0 0.8 V

V

OH

HIGH-level output voltage Io= − 1 mA 2.4 V

CCD

− V

I

OL

LOW-level output current VOL= 0.4 V − 2 − mA

I

OH

HIGH-level output current VOH= 2.7 V −−0.5 − mA

TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)

V

IL

LOW level input voltage −− 0.8 V

V

IH

HIGH level input voltage 2.0 −−V
IILLOW level input current VIL= 0.4 V 400 −−µA
IIHHIGH level input current VIH= 2.7 V −− 100 µA
Z

i

input impedance − 4 − kΩ
C

i

input capacitance − 4.5 − pF

3-wire serial bus

t

reset

reset time of the chip before

3-wire communication

− 600 − ns

t

su

data set-up time − 100 − ns
t

h

data hold time − 100 − ns

I

2

C-bus; see note 3

f

SCL

clock frequency 0 − 100 kHz
t

BUF

time the bus must be free

before new transmission can

start

4.7 −−µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1999 Mar 09 27

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Notes to the characteristics

1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST
frequency). Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

2. Output data acquisition is available after the maximum delay time t

d(o)

, which is the time during which the data is
available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then
be rechecked.

3. The I2C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of
400 kbit/s (400 kHz).

t

HD;STA

start condition hold time 4.0 −−µs

t

SU;STA

start condition set-up time repeated start 4.7 −−µs

t

CKL

LOW level clock period 4.7 −−µs

t

CKH

HIGH level clock period 4.0 −−µs

t

SU;DAT

data set-up time 250 −−ns

t

HD;DAT

data hold time 0 −−ns

t

r

SDA and SCL rise time for f

SCL

= 100 kHz −− 1.0 µs

t

f

SDA and SCL fall time for f

SCL

= 100 kHz −− 300 ns

t

SU;STOP

stop condition set-up time 4.0 −−µs

C

L(bus)

capacitive load for each bus
line

−− 400 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fig.11 Timing diagram.

handbook, full pagewidth

t

d(s)

sample N + 1

sample N

CKADCO

n

MGL103

sample N + 2

50 % = 1.4 V

1.4 V

2.4 V

0.4 V

V

lN

DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR

t

d(o)

t

h(o)

t

CPH

t

CPL

I

n + 2

I

n + 1

I

n

I

n − 1

1999 Mar 09 28

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Fig.12 Timing diagram and test conditions of 3-state output delay time.

tOE= 100 kHz.

handbook, full pagewidth

output

data

output

data

OE

50%

50%

50%

10%

90%

LOW

TDA8752

LOW

HIGH

HIGH

t

dZH

t

dZL

t

dHZ

V

CCD

t

dLZ

3.3 kΩ

MGD695

S1

OE

V

CCD

10 pF

Table 12 Test conditions for Fig.12

TEST SWITCH S1

t

dLZ

V

CCD

t

dZl

V

CCD

t

dHZ

GND

t

dZH

GND

1999 Mar 09 29

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital

Converter (ADC)

TDA8752

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APPLICATION INFORMATION

Table 13 Examples of PLL settings and performances; note 1

Notes

1. Values measured at V

CCA=VDDD=VCCD=VCCO

= 5 V and T

amb

=25°C.

2. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.

3. Measured between 0 and 70 °C.

VIDEO

STANDARDS

f

ref

(kHz)

f

CLK

(MHz)

N

KO

(MHz/V)CZ(nF)CP(nF)

IP (µA)

Z

(kΩ)

LONG TIME JITTER

(2)

PLL PHASE

DRIFT

(3)

(ns)

ps (RMS) ns (p-p)

CGA: 640 × 200 15.75 14.3 912 15 150 1 200 4 −− 1.2
VGA: 640 × 480 31.5 25.2 800 30 150 1 400 2 610 3.6 0.7
VESA: 800 × 600 48.08 50 1040 60 150 1 700 1 480 2.9 0.55
VESA: 1024 × 768 60.02 78.8 1312 100 150 1 700 1 380 2.3 0.3
SUN: 1152× 900 66.67 100 1500 100 150 1 700 1 360 2.2 0.3

1999 Mar 09 30

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Fig.13 Application diagram.

All supply pins have to be decoupled, with two capacitors:
one for high frequencies (approximately 1 nF) and one for the low frequencies (approximately 100 nF or higher).

handbook, full pagewidth

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

CKREFO
V

CCOR
R7
R6
R5
R4
R3
R2
R1
R0
OGNDR

V

CCOG
G7
G6
G5
G4
G3
G2
G1
G0
OGNDG

V

CCOB
B7
B6
B5
B4
B3
B2
B1
n.c.

DEC2

V

ref

DEC1

n.c.

RAGC

RBOT

RGAINC

RCLP

RDEC

V

CCAR

RIN

AGNDR

GAGC

GBOT

GGAINC

GCLP

GDEC

V

CCAG

GIN

AGNDG

BAGC
BBOT

BGAINC

BCLP

BCDEC

V

CCAB

BIN

RIN

2.5 V

GIN

BIN

AGNDB

n.c.

n.c.

V

CCA(PLL)

CZ

CP

AGNDPLL

V

CCD

CKREF

COAST

CKEXT

INV

HSYNC

CLP

PWDWN

OE

DGND

V

CCO(PLL)

CKADCO

CKBO

OGNDPLL

CKAO

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 40 4132 4233 4334 4435 4536 4637 4738 4839 49 50

MGG371

TDA8752

n.c.

4.7
kΩ

4.7
kΩ

150 pF

10 nF

1.5 nF

10 nF

22 nF

4.7 nF
10 nF

10 nF

22 nF

4.7 nF
10 nF

10 nF

22 nF

4.7 nF
10 nF

100 nF

33 nF

100 nF

75 Ω or 50 Ω

100 nF

75 Ω or 50 Ω

n.c.

I

2

C/3W

ADD1

ADD2

TCK

TDO

DIS

SEN

SCL

V

DDD

V

DDD

V

DDD

V

SSD

SDA

n.c.GORn.c.

BORRORn.c.

OGNDB

B0

75 Ω or 50 Ω

1999 Mar 09 31

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

PACKAGE OUTLINE

UNIT A1A2A3bpcE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

0.25

0.05

2.90

2.65

0.25

0.40

0.25

0.25

0.14

14.1

13.9

0.65

18.2

17.6

1.0

0.6

7
0

o
o

0.15 0.10.21.95

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

1.0

0.6

SOT317-2

95-02-04
97-08-01

D

(1) (1)(1)

20.1

19.9

H

D

24.2

23.6

E

Z

0.8

0.4

D

e

θ

E

A

1

A

L

p

detail X

L

(A )

3

B

30

c

b

p

E

H

A

2

D

Z

D

A

Z

E

e

v M

A

1

100

81

80 51

50

31

pin 1 index

X

y

b

p

D

H

v M

B

w M

w M

0 5 10 mm

scale

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

SOT317-2

A

max.

3.20

1999 Mar 09 32

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Mar 09 33

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE

SOLDERING METHOD

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(2)

suitable

PLCC

(3)

, SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended

(3)(4)

suitable

SSOP, TSSOP, VSO not recommended

(5)

suitable

1999 Mar 09 34

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

1999 Mar 09 35

Philips Semiconductors Product specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1999 SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

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Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

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Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

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For all other countries apply to: Philips Semiconductors,
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Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
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Hungary: see Austria
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
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Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
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Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
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Printed in The Netherlands 545004/750/05/pp36 Date of release: 1999 Mar 09 Document order number: 9397 750 05306