Datasheet TDA8752 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8752

Triple high speed Analog-to-Digital
Converter (ADC)

Preliminary specification
Supersedes data of 1997 Apr 22
File under Integrated Circuits, IC02

1997 Jun 04

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

FEATURES

• Triple 8-bit ADC

• Sampling rate up to 80 MHz

• IC controllable via a serial interface, which can be either

I2C-bus or 3-wire, selected via a TTL input pin

• IC analog voltage input from 0.4 to 1.2 V (p-p) to
produce full-scale ADC input of 1 V (p-p)

• 3 clamps for programming a clamping code between

−63.5 and +64 in steps of1⁄2LSB

• 3 controllable amplifiers: gain controlled via the serial

interface to produce a full scale resolution of
peak-to-peak

• Amplifier bandwidth of 250 MHz

• Low gain variation with temperature

• PLL, controllable via the serial interface to generate the

ADC clock, which can be locked to a line frequency from
15 to 280 kHz

• Integrated PLL divider

• Programmable phase clock adjustment cells

• Internal voltage regulators

• TTL compatible digital inputs and outputs

• Chip enable high-impedance ADC output

• Power-off mode

• Possibility to use up to four ICs in the same system,

using the I2C-bus interface, or more, using the 3-wire
serial interface

• 1 W power dissipation.

1

⁄2LSB

TDA8752

GENERAL DESCRIPTION

The TDA8752 is a triple 8-bit ADC with controllable
amplifiers and clamps for the digitizing of large bandwidth
RGB signals.

The clamp level, the gain and all of the other settings are
controlled via a serial interface (either I
serial bus, selected via a logic input).

The IC also includes a PLL that can be locked on the
horizontal line frequency and generates the ADC clock.
The PLL jitter is minimized for high resolution PC graphics
applications. An external clock can also be input to the
ADC.

It is possible to set the TDA8752 serial bus address
between four fixed values, in the event that several
TDA8752 ICs are used in a system, using the I
interface (for example, two ICs used in an odd/even
configuration).

2

C-bus or 3-wire

2

C-bus

APPLICATIONS

• R, G and B high speed digitizing

• LCD panels drive

• LCD projection systems

• VGA and higher resolutions

• Using two ICs in parallel, higher display resolution can

be obtained; 160 MHz pixel frequency.

ORDERING INFORMATION

TYPE

NUMBER

TDA8752H/6
TDA8752H/8 80

1997 Jun 04 2

NAME DESCRIPTION VERSION

QFP100

plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm

PACKAGE SAMPLING

FREQUENCY

(MHz)

SOT317-2

60

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

DDD

V

CCD

V

CCO

V

CCA(PLL)

V

CCO(PLL)

I

CCA

I

DDD

I

CCD

I

CCO

I

CCA(PLL)

I

CCO(PLL)

f

CLK

f

ref(PLL)

f

VCO

INL DC integral non linearity from analog input to

DNL DC differential non linearity from analog input to

∆G

amp

B amplifier bandwidth −3 dB; T
t

set

j

PLL(rms)

DR

PLL

P

tot

analog supply voltage for R, G and B channels 4.75 5.0 5.25 V
logic supply voltage for I2C-bus and 3-wire 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
output stages supply voltage for R, G and B channels 4.75 5.0 5.25 V
analog PLL supply voltage 4.75 5.0 5.25 V
output PLL supply voltage 4.75 5.0 5.25 V
analog supply current − 120 − mA
logic supply current for I2C-bus and 3-wire − 1.0 − mA
digital supply current − 40 − mA
output stages supply current f

= 80 MHz;

CLK

− 6 − mA

ramp input
analog PLL supply current − 28 − mA
output PLL supply current − 5 − mA
maximum clock frequency TDA8752/6 60 −−MHz

TDA8752/8 80 −−MHz
PLL reference clock frequency 15 − 280 kHz
VCO output clock frequency 12 − 80 MHz

−±0.5 tbf LSB
digital output; full-scale;
ramp input;
f

=80MHz

CLK

−±0.5 tbf LSB
digital output; full-scale;
ramp input;

=80MHz

f

CLK

/T amplifier gain stability as a function of

temperature

settling time of the ADC block plus AGC input signal settling

V

= 2.5 V with

ref

100 ppm/°C maximum

=25°C 250 −−MHz

amb

time < 1 ns; T

amb

=25°C

−−200 ppm/°C

−−6ns

maximum PLL phase jitter (RMS value) − 0.2 − ns
PLL divider ratio without divide-by-2 15 − 2047
total power consumption f

= 80 MHz;

CLK

− 1.0 tbf W
ramp input

1997 Jun 04 3

Philips Semiconductors Preliminary specification

o

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

BLOCK DIAGRAM

RCLP

RBOT

R0 to R7

9

7

86

DGND

AGNDPLL

OGNDG

SSD

V

AGNDG

k, full pagewidth

CLP

CCA(PLL)

V

CCOB

V

CCOR

V

CCAB

V

CCAR

V

82

96

OGNDPLL

48

OGNDB

60
70

OGNDR

41
29

AGNDB

21
13

AGNDR

89

85

CCO(PLL)

99

V

95

CCD

V

59
69

CCOG

V

79

40

DDD

V

27
19

CCAG

V

11

6

71 to 78

CLAMP

8

12

TCK

TDO

353645

OUTPUTS

ADC

MUX

10

ROR

3

GBOT

G0 to G7

GCLP

17

15

61 to 68

RED CHANNEL

14

20

16

GOR

46

GREEN CHANNEL

18

BBOT

BCLP

OE

87

25

23

49, 52 to 58

B0 to B7

BOR

47

84

CKBO

CKADCO

83

CKAO

81

CKREFO

928091

CKEXT

PLL

TDA8752

BLUE CHANNEL

HSYNCI

22

24

28

26

REGULATOR

C-BUS

2

SERIAL

I

INTERFACE

3334384239

OR

COAST

INV

93

94

C-bus; 1-bit

2

(H level)

I

3-WIRE

32

37

CKREF

MGG363

CZ

CP

PWOFF

DEC2DEC1HSYNCn.c.

4 2 88 97 98

90

1, 5, 30, 31, 43 , 44

50, 51, 100

Fig.1 Block diagram.

RAGC

RIN

RGAINC

RDEC

ref

V

GAGC

GIN

GGAINC

GDEC

BAGC

1997 Jun 04 4

BIN

BGAINC

BDEC

ADD2

ADD1

SEN

SCL

SDA

DIS

C/3W

2

I

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

CLP RAGC CKAOUT

handbook, full pagewidth

RCLP

V

ref

RIN

V

P

150

kΩ

3
kΩ

45
kΩ

DAC

5

REGISTER

FINE GAIN ADJUST

I2C-bus; 5 bits

(Fr)

MUX

CLAMP

CONTROL

AGC

V

CCAR

ADC

ADC

8

D

D ≥ R

R

1

1

COARSE GAIN ADJUST

8

7

REGISTER

2

I

C-bus; 7 bits

(Cr)

DAC

8

REGISTER

2

I

C-bus; 8 bits

(Or)

OUTPUTS

SERIAL

2

I

C-BUS

TDA8752

ROR

8

R0 to R7

OE

RBOT

HSYNCI

RGAINC

Fig.2 Red channel diagram.

1997 Jun 04 5

MGG364

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

CKREF

edge selector

2

I

C-bus;
1 bit
(edge)

2

I

C-bus; 1 bit

(V level)

COAST

PHASE

FREQUENCY

DETECTOR

2

I

C-bus; 5 bits

(Ip, Up, Do)

DIV N (15 to 2047)

2

I

C-bus; 11 bits (Di)

C

z

CZ CP

loop filter

2

I

C-bus;

3 bits (Z)

÷ 2

2 bits (VCO)

C

p

VCO

2

I

C-bus;

12 to

80 MHz

phase selector A

2

I

C-bus;

5 bits (Pa)

phase selector B

2

I

C-bus; 5 bits (Pb)

CKEXT INV

MUX

2

I

C-bus;

1 bit (Cka)

0°/180°

CLK

ADC

TDA8752

2

C-bus;

I

1 bit (Ckb)

CKADCO

CKBO

CKAO

Fig.3 PLL diagram.

SYNCHRO

CKREFO

MGG370

1997 Jun 04 6

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
DEC2 2 main regulator decoupling input
V

ref

DEC1 4 main regulator decoupling input
n.c. 5 not connected
RAGC 6 red channel AGC output
RBOT 7 red channel ladder decoupling input (BOT)
RGAINC 8 red channel gain capacitor input
RCLP 9 red channel gain clamp capacitor input
RDEC 10 red channel gain regulator decoupling input
V

CCAR

RIN 12 red channel gain analog input
AGNDR 13 red channel gain analog ground
GAGC 14 green channel AGC output
GBOT 15 green channel ladder decoupling input (BOT)
GGAINC 16 green channel gain capacitor input
GCLP 17 green channel gain clamp capacitor input
GDEC 18 green channel gain regulator decoupling input
V

CCAG

GIN 20 green channel gain analog input
AGNDG 21 green channel gain analog ground
BAGC 22 blue channel AGC output
BBOT 23 blue channel ladder decoupling input (BOT)
BGAINC 24 blue channel gain capacitor input
BCLP 25 blue channel gain clamp capacitor input
BDEC 26 blue channel gain regulator decoupling input
V

CCAB

BIN 28 blue channel gain analog input
AGNDB 29 blue channel gain analog ground
n.c. 30 not connected
n.c. 31 not connected
I2C/3W 32 selection input between I2C-bus (active HIGH) and 3-wire serial bus (active LOW)
ADD1 33 I2C-bus address control input 1
ADD2 34 I2C-bus address control input 2
TCK 35 scan test mode (active HIGH)

3 gain stabilizer voltage reference input

11 red channel gain analog power supply

19 green channel gain analog power supply

27 blue channel gain analog power supply

1997 Jun 04 7

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

SYMBOL PIN DESCRIPTION

TDO 36 scan test output
DIS 37 I2C and 3W disable control input (disable at HIGH level)
SEN 38 select enable for 3-wire serial bus input (see Fig.9)
SDA 39 I2C/3W serial data input
V

DDD

V

SSD

SCL 42 I
n.c. 43 not connected
n.c. 44 not connected
ROR 45 red channel ADC output bit overflow
GOR 46 green channel ADC output bit overflow
BOR 47 blue channel ADC output bit overflow
OGNDB 48 blue channel ADC output ground
B0 49 blue channel ADC output bit 0 (LSB)
n.c. 50 not connected
n.c. 51 not connected
B1 52 blue channel ADC output bit 1
B2 53 blue channel ADC output bit 2
B3 54 blue channel ADC output bit 3
B4 55 blue channel ADC output bit 4
B5 56 blue channel ADC output bit 5
B6 57 blue channel ADC output bit 6
B7 58 blue channel ADC output bit 7 (MSB)
V

CCOB

OGNDG 60 green channel ADC output ground
G0 61 green channel ADC output bit 0 (LSB)
G1 62 green channel ADC output bit 1
G2 63 green channel ADC output bit 2
G3 64 green channel ADC output bit 3
G4 65 green channel ADC output bit 4
G5 66 green channel ADC output bit 5
G6 67 green channel ADC output bit 6
G7 68 green channel ADC output bit 7 (MSB)
V

CCOG

OGNDR 70 red channel ADC output ground
R0 71 red channel ADC output bit 0 (LSB)

40 logic I2C/3W digital power supply
41 logic I2C/3W digital ground

2

C/3W serial clock input

59 blue channel ADC output power supply

69 green channel ADC output power supply

TDA8752

1997 Jun 04 8

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

SYMBOL PIN DESCRIPTION

R1 72 red channel ADC output bit 1
R2 73 red channel ADC output bit 2
R3 74 red channel ADC output bit 3
R4 75 red channel ADC output bit 4
R5 76 red channel ADC output bit 5
R6 77 red channel ADC output bit 6
R7 78 red channel ADC output bit 7 (MSB)
V

CCOR

CKREFO 80 reference output clock
CKAO 81 PLL clock output 3 (in phase with reference output clock)
OGNDPLL 82 PLL digital ground
CKBO 83 PLL clock output 2
CKADCO 84 PLL clock output 1 (in phase with internal ADC clock)
V

CCO(PLL)

DGND 86 digital ground
OE 87 output enable not (when OE is HIGH, the outputs are in high-impedance)
PWOFF 88 power off control input (IC is in power-down mode when this pin is HIGH)
CLP 89 clamp pulse input (clamp active HIGH)
HSYNC 90 horizontal synchronization input pulse
INV 91 PLL clock output inverter command input (invert when HIGH)
CKEXT 92 external clock input
COAST 93 PLL coast command input
CKREF 94 PLL reference clock input
V

CCD

AGNDPLL 96 PLL analog ground
CP 97 PLL filter input
CZ 98 PLL filter input
V

CCAPLL

n.c. 100 not connected

79 red channel ADC output power supply

85 PLL output power supply

95 digital power supply

99 PLL analog power supply

TDA8752

1997 Jun 04 9

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

n.c.

DEC2

V

DEC1

n.c.

RAGC

RBOT

RGAINC

RCLP

RDEC

V

CCAR

RIN

AGNDR

GAGC

GBOT

GGAINC

GCLP

GDEC

V

CCAG

GIN

AGNDG

BAGC
BBOT

BGAINC

BCLP

BDEC

V

CCAB

BIN

AGNDB

n.c.

ref

CCA(PLL)

n.c.

V

CZCPAGNDPLL

99989796959493929190898887868584838281

100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CCD

V

CKREF

COAST

CKEXT

INV

HSYNC

TDA8752

CLP

PWOFFOEDGND

CCO(PLL)

V

CKADCO

CKBO

OGNDPLL

CKAO

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52

51

CKREFO
V

CCOR

R7
R6
R5
R4
R3
R2
R1
R0
OGNDR

V

CCOG

G7
G6
G5
G4
G3
G2
G1
G0
OGNDG

V

CCOB

B7
B6
B5
B4
B3
B2
B1
n.c.

TDA8752

31323334353637383940414243444546474849

n.c.

C/3W

2

I

ADD1

ADD2

TCK

TDO

DIS

SEN

SDA

V

Fig.4 Pin configuration.

1997 Jun 04 10

DDD

SSD

V

SCL

n.c.

n.c.

ROR

GOR

BOR

B0

OGNDB

50

n.c.

MGG362

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

FUNCTIONAL DESCRIPTION

This triple high-speed 8-bit ADC is designed to convert
RGB signals, from a PC or work station, into data used by
a LCD driver (pixel clock up to 160 MHz, using 2 ICs).

IC analog video inputs

The video inputs are internally DC polarized. These inputs
are AC coupled externally.

Clamps

Three independent parallel clamping circuits are used to
clamp the video input signals on the black level and to
control the contrast level. The clamping code is
programmable between code −63.5 and +64 in steps of

1

⁄2LSB. The programming of the clamp value is achieved

via an 8-bit DAC. Each clamp must be able to correct an
offset from±0.1 V to±10 mV within 300 ns, and correct the
total offset in 10 lines.

The clamps are controlled by an external TTL positive
going pulse (pin CLP). The drop of the video signal is
<1 LSB.

Normally, the circuit operates with a 0 code clamp,
corresponding to the 0 ADC code. This clamp code can be
changed from −63,5 to +64 as represented in Fig.6, in
steps of1⁄2LSB. The digitized video signal is always
between code 0 and code 255 of the ADC.

Variable gain amplifier

Three independent variable gain amplifiers are used to
provide, to each channel, a full-scale input range signal to
the 8-bit ADC. The gain adjustment range is designed so
that, for an input range varying from 0.4 to 1.2 V (p-p), the
output signal corresponds to the ADC full-scale input of
1 V (p-p).

To ensure that the gain does not vary over the whole
operating temperature range, an external reference of
+2.5 V DC, (V
supplied externally, is used to calibrate the gain at the
beginning of each video line before the clamp pulse using
the following principle:

A differential of 0.156 V(p-p) (1⁄16V
generated internally from the reference voltage (V
During the synchronization part of the video line, the
multiplexer, controlled by the TTL synchronization signal
(HSYNCI, coming from HSYNC; see Fig.1) with a width
equal to one of the video synchronization signals
(e.g. signal coming from a synchronization separator), is
switched between the two amplifiers.

with a 100 ppm/°C maximum variation)

ref

) reference signal is

ref

ref

).

TDA8752

The output of the multiplexer is either the normal video
signal or the 0.156 V reference signal (during HSYNC).

The corresponding ADC outputs are then compared to a
pre-set value loaded in a register. Depending on the result
of the comparison, the gain of the variable gain amplifiers
is adjusted (coarse gain control; see Figs 1 and 7).
The three 7-bit registers receive data via a serial interface
to enable the gain to be programmed.

The pre-set value loaded in the 7-bit register is chosen
between approximately 67 codes to ensure the full-scale
input range (see Fig.7).

A fine correction using three 5-bit DACs, also controlled via
the serial interface, is used to finely tune the gain of the
three channels (fine gain control; see Figs 1 and 8) and to
compensate the channel-to-channel gain mismatch.

With a full scale ADC input, the resolution of the fine
register corresponds to

To use these gain controls correctly, it is recommended to
fix the coarse gain (to have a full-scale ADC input signal)
to within 4LSB and then adjust it with the fine gain.
The gain is adjusted during HSYNC. During this time the
output signal is not related to the amplified input signal.
The outputs, when the coarse gain system is stable, is
related to the programmed coarse code (see Fig.7).

ADCs

The ADCs are 8-bit with a maximum clock frequency of
80 Msps. The ADCs input range is 1 V (p-p) full-scale.
One overflow bit exists per channel (ROR, GOR and
BOR). It will be at logic 1 when the signal is over the full
scale of the ADCs.

Pipeline delay in the ADCs is 1 clock cycle from sampling
to data output.

The ADCs reference ladders regulators are integrated.

ADC outputs

ADC outputs are straight binary. An output enable pin

OE; active LOW) enables the output status between

(
active and high-impedance (OE = HIGH) to be switched;
it is recommended to load the outputs with a 10 pF
capacitive load. The timing must be checked very carefully
if the capacitive load is more than 10 pF.

1

⁄2LSB peak-to-peak variation.

1997 Jun 04 11

Philips Semiconductors Preliminary specification



Triple high speed Analog-to-Digital
Converter (ADC)

Phase-locked loop

The ADCs are clocked either by an internal PLL locked to
the CKREF clock, (all of the PLL is on-chip except the loop
filter capacitance) or an external clock, CKEXT.
Selection is performed via the serial interface bus.

The reference clock (CKREF) range is between
15 and 280 kHz. Consequently, the VCO minimum
frequency is 12 MHz and the maximum frequency 80 MHz
for the TDA8752/8 and 60 MHz for the TDA8752/6.
The gain of the VCO part can be controlled via the serial
interface, depending on the frequency range to which the
PLL is locked.

To increase the bandwidth of the PLL, the charge pump
current, controlled by the serial interface, must also be
increased. The relationship between the bandwidth and
the current is given by the following equation:

KOI

Cz( CP) N+

z

P

W

1



and ξ



n

×=

------- -

-- ­2

W

z

W

---------------------------------- -=

n

Where:

= the natural PLL bandwidth

W

n

KO= the VCO gain
N = the division number
Cz and CP= capacitors of the PLL filter.

The other PLL equation is as follows:

W

1

=

-----------------

z

RC

×

Where:

Wz= the natural VCO frequency
R = the chosen resistance for the filter
ξ = the damping factor.

Different resistances for the filter can be programmed via
the serial interface.

It is possible to control (independently) the phase of the
ADC clock and the phase of an additional clock output
(which could be used to drive a second TDA8752).
For this, two serial interface-controlled digital phase-shift
controllers are included (controlled by 5-bit registers,
phase shift controller steps are 11.25° each on the whole
PLL frequency range).

TDA8752

CKREF is resynchronized, by the synchro block, on the
CKAO clock. The output is CKREFO. CKAO is the clock at
the output of the phase selector A. This clock can be used
as the clocks for CKBO and CKADCO.

The COAST pin is used to disconnect the PLL phase
frequency detector during the frame flyback or the
unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.

The clock output is able to drive an external 10 pF load
(for the on-chip ADCs).

The PLL can be used in three different methods:

1. The IC can be used as stand-alone with a sampling
frequency of up to 80 MHz. For the TDA8752/8 and
60 MHz for the TDA8752/6.

2. When an RGB signal is at a pixel frequency exceeding
80 MHz to 160 MHz, it is possible to follow one of the
two possibilities given below;

a) Using one TDA8752; the sampling rate can be

reduced by a factor of two, by sampling the even
pixels in the even frame and the odd pixels in the
odd frame. The INV pin is used to toggle between
frames.

b) Using two TDA8752s: the PLL of the master

TDA8752 is used to drive both ADC clocks.
The PLL of the slave TDA8752 is disconnected and
the CKBO of the master TDA8752 is connected to
pin CKEXT of the slave TDA8752. The CKADCO
and CKBO phases are adjustable via the phase
selector of the master TDA8752.

The master TDA8752 is used to sample the even
pixels and the slaveTDA8752 for odd pixels, using
a 180° phase shift between the clocks (CKADCO
pins). To do this it is necessary to adjust phase A
of the PLL master device to acquire the right even
pixels. CKBO pin of the master device is then
connected to CKEXT of the slave device. It is
necessary to adjust the phase B of the PLL master
device to acquire the right odd pixels (see Fig.5).

1997 Jun 04 12

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

CKREF

COAST CKEXT INV

phase selector A

5 bits (Pa)

PLL

phase selector B

2

I

C-bus; 5 bits (Pb)

Master TDA8752

(even pixels)

12 to

80 MHz

2

I

C-bus;

MUX

2

I

C-bus;

1 bit (Cka)

(Cka = 0)

SYNCHRO

0°/180°

TDA8752

CKADCO

CLK
ADC

CKBO

I2C-bus;

1 bit (Ckb)

(Ckb = 1)

CKAO

CKREFO

COAST CKEXT INV

12 to

80 MHz

phase selector A

2

I

CKREF

PLL

C-bus;

5 bits (Pa)

phase selector B

2

I

C-bus; 5 bits (Pb)

I

1 bit (Cka)

(Cka = 1)

Slave TDA8752

(odd pixels)

Slave at 180° phase shift with respect to pin CKADCO of the master TDA8752.

Fig.5 Dual TDA8752 solution for pixel clock rate (80 MHz to 160 MHz).

MUX

2

C-bus;

SYNCHRO

0°/180°

CKADCO

CLK
ADC

CKBO

I2C-bus;

1 bit (Ckb)

(Ckb = 0)

CKAO

CKREFO

MGL112

I2C-bus and 3-wire serial bus interface

The I2C-bus and 3-wire serial buses control the status of the different control DACs and registers. Control pin DIS
enables or disables the full serial interface function (disable at HIGH level). Four ICs can be used in the same system
and programmed by the same bus. Therefore, two pins (ADD1 and ADD2) are available to set each address respectively,
for use with the I2C-bus interface. All programming is described in Chapter “I2C-bus and 3-wire interfaces”.

1997 Jun 04 13

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

handbook, full pagewidth

handbook, full pagewidth

video signal

CLP

N

coarse
code

255

digitized

Fig.6 Clamp definition.

video

signal

code 64
code 0
code −63.5

clamp

programming

MGG368

ADC output

code

TDA8752

handbook, full pagewidth

coarse

register

value

(67 codes)

coarse

register

value

(67 codes)

127

99

32

0

ADC

output code

255

227

N

COARSE

160

G

0.156 =

(max)

V

16

ref

0.2

G

(min)

Fig.7 Coarse gain control.

G

(max)

0.6

G

NCOARSE

255

227

160
128

G

(min)

V

i (p-p)

2

MGG366

128

NFINE = 31

Fig.8 Fine gain correction for a coarse gain G

1997 Jun 04 14

NFINE = 0

NCOARSE

V

ref

MGG367

.

1997 Jun 04 15

I2C-BUS AND 3-WIRE INTERFACES
Register definitions

The configuration of the different registers is as follows:

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

Converter (ADC)

Table 1 I

FUNCTION

NAME

SUBADDR −−−−−−−− X X X Mode Sa3 Sa2 Sa1 Sa0 xxx10000
OFFSETR XXXX0000Or7Or6Or5Or4Or3Or2Or1Or001111111
COARSER XXXX0001 X Cr6Cr5Cr4Cr3Cr2Cr1Cr0x010 0000
FINER XXXX0010 X X XFr4Fr3Fr2Fr1Fr0xxx0 0000
OFFSETG XXXX0011Og7Og6Og5Og4Og3Og2Og1Og001111111
COARSEG XXXX0100 X Cg6Cg5Cg4Cg3Cg2Cg1Cg0x010 0000
FINEG XXXX0101 X X XFg4Fg3Fg2Fg1Fg0xxx0 0000
OFFSETB XXXX0110Ob7Ob6Ob5Ob4Ob3Ob2Ob1Ob001111111
COARSEB XXXX0111 X Cb6Cb5Cb4Cb3Cb2Cb1Cb0x010 0000
FINEB XXXX1000 X X XFb4Fb3Fb2Fb1Fb0xxx0 0000
CONTROL XXXX1001V level H level edge Up Do Ip2 Ip1 Ip0 0000 0100
VCO XXXX1010Z2 Z1Z0Vco1 Vco0 Di10 Di9 Di8 0110 0001
DIVIDER

(LSB)
PHASEA XXXX1100 X XCkaPa4Pa3Pa2Pa1Pa0xx00 0000
PHASEB XXXX1101 X XCkbPb4Pb3Pb2Pb1Pb0xx00 0000

2

C-bus and 3-wire registers

SUBADDRESS BIT DEFINITION

A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB

XXXX1011Di7Di6Di5Di4Di3Di2Di1Di01001 0000

DEFAULT

VALUE

2

All the registers are defined by a subaddress of 8 bits; bit A4 refers to the mode which is used with the I
subaddress of each register.

The bit mode, used only with the I2C-bus, enables two modes to be programmed:

• If Mode = 0, each register is programmed independently by giving its subaddress and its content

• If Mode = 1, all the registers are programmed one after the other by giving this initial condition (xxx1 1111) as the subaddress state; thus, the registers

are charged following the predefined sequence of 16 bytes (from subaddress 0000 to 1101).

C-bus interface; bits Sa3 to Sa0 are the

TDA8752

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

OFFSET REGISTER
This register controls the clamp level for the RGB

channels. The relationship between the programming
code and the level of the clamp code is given in Table 2.

Table 2 Coding

PROGRAMMED

CODE

0 −63.5 underflow
1 −63
2 −62.5

↓↓

127 0 0

↓↓↓

254 63.5 63 or 64
255 64 64

The default programmed value is:

• Programmed code = 127

• Clamp code = 0

• ADC output = 0.

C

OARSE AND FINE REGISTERS

These two registers enable the gain control, the AGC gain
with the coarse register and the reference voltage with the
fine register. The coarse register programming equation is
as follows:

N

GAIN

N

COARSE

------------------------------------------------­512 N

V

ref

Where: V

COARSE

----------------------------------------------



V



ref

–()

FINE

= 2.5 V.

ref

The gain correspondence is given in Table 3. The gain is
linear with reference to the programming code (N

CLAMP CODE ADC OUTPUT

1+

1

=

×=

-----­16

1

N

–

------------------­32 16×

FINE

1+

32×

FINE

= 0).

TDA8752

Table 3 Gain correspondence (COARSE)

N

COARSE

GAIN

32 0.825 1.212
99 2.5 0.4

The default programmed value is as follows:

• N

COARSE

=32

• Gain = 0.825

• Vi to be full-scale = 1.212.

To modulate this gain, the fine register is programmed
using the above equation. With a full-scale ADC input, the

1

fine register resolution is a
(see Table 4 for N

COARSE

⁄2LSB peak-to-peak

= 32).

Table 4 Gain correspondence (FINE)

N

FINE

GAIN

0 0.825 1.212

31 0.878 1.139

The default programmed value is: N

C

ONTROL REGISTER

FINE

Coast and HSYNC signals can be inverted by setting the
I2C-bus control bits V level and H level respectively. When
V level and H level are set to zero respectively, COAST
and HSYNC are active HIGH.

The bit ‘edge’ defines the rising or falling edge of CKREF
to synchronise the PLL. It will be on the rising edge if the
bit is at logic 0 and on the falling edge if the bit is at logic 1.

The bits Up and Do are used for the test, to force the
charge pump current. These bits have to be logic 0 during
normal use.

The bits Ip0, Ip1 and Ip2 control the charge pump current,
to increase the bandwidth of the PLL, as shown in Table 5.

Vi TO BE

FULL-SCALE

Vi TO BE

FULL-SCALE

=0.

1997 Jun 04 16

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

Table 5 Charge-pump current control

Ip2 Ip1 Ip0

0 0 0 6.25
0 0 1 12.5
010 25
011 50
100 100
101 200
110 400
111 700

The default programmed value is as follows:

• Charge pump current = 100 µA

• Test bits: no test mode: bits Up and Do at logic 0

• Rising edge of CKREF: bit edge at logic 0

• COAST and HSYNC inputs are active HIGH: V level and

H level at logic 0.

VCO

REGISTER

The bits Z2, Z1 and Z0 enable the internal resistance for
the VCO filter to be selected.

CURRENT

(µA)

TDA8752

Table 7 VCO gain control

V

CO1

V

CO0

VCO gain

(MHz/V)

0 0 15 2.5 to 25
0 1 30 5 to 50
1 0 60 8 to 80
1 1 100 15 to 150

The bits V

CO1

and V

control the VCO gain.

CO0

The default programmed value is as follows:

• Internal resistance = 16 kΩ

• VCO gain = 15 MHz/V.

D

IVIDER REGISTER

This register controls the PLL frequency. The bits are the
LSB bits.

The default programmed value including the divide-by-2 is:
001 1001 0000 = 800 (binary)

The MSB bits (Di10, Di9 and Di8) have to be programmed
before the LSB bits (Di7 to Di0) to have the required
divider ratio.

FREQUENCY

RANGE (MHz)

Table 6 VCO register bits

Z2 Z1 Z0

RESISTANCE

(kΩ)

0 0 0 high impedance
001 128
010 32
011 16
100 8
101 4
110 2
111 1

PHASEA

AND PHASEB REGISTERS

The bit Cka is logic 0 when the used clock is the PLL clock,
and logic 1 when the used clock is the external clock.

The bit Ckb is logic 0 when the second clock is not used.
The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program

the phase shift for the clock, CKADCO, CKAO and CKBO
(see Table 8).

1997 Jun 04 17

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

Table 8 Phase registers bits

Pa4, Pb4 Pa3, Pb3 Pa2, Pb2 Pa1, Pb1 Pa0, Pb0 PHASE SHIFT (°)

00000 0

0000111.25

↓↓↓↓↓ ↓
↓↓↓↓↓ ↓

11110337.5

11111348.75

The default programmed value is as follows:

• No external clock: CKA at logic 0

• No use of the second clock: CKA at logic 0

• Phase shift for CKAO and CKADCO = 0°

• Phase shift for CKBO = 0°.

2

C-bus protocol

I

2

Table 9 I

C-bus address

A7 A6 A5 A4 A3 A2 A1 A0

10011ADD2 ADD1 0

2

C-bus address of the circuit is 10011 xx0.

The I
Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752s can be used on the same

system, using the addresses for ADD1 and ADD2 with the I2C-bus. The A0 bit must always be equal to logic 0 because
it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences
are available, see Tables 10 and 11.

Table 10 Address sequence for mode 0

S IC ADDRESS ACK SUBADDRESS

REGISTER1

Where: S = START condition, ACK = acknowledge and P = STOP condition.

Table 11 Address sequence for mode 1

S IC ADDRESS ACK SUBADDRESS

xxx1 1111

Where: S = START condition, ACK = acknowledge and P = STOP condition.

ACK DATA

REGISTER1

(see Table 1)

ACK DATA

REGISTER1

(see Table 1)

ACK SUBADDRESS

REGISTER2

ACK DATA

REGISTER2

ACK .... P

ACK .... P

1997 Jun 04 18

1997 Jun 04 19

3-wire protocol

For the 3-wire serial bus the first byte refers to the register address which is programmed. The second byte refers to the data to be sent to the chosen
register (see Table 1). The acquisition is achieved via SEN.

Using the 3-wire interface, an indefinite number of ICs can operate on the same system. Pin SEN is used to validate the circuits.

SEN

t

SCL

= 600 ns

r3W

1199

t

s3W

= 100 ns

t

h3W

= 100 ns

100 ns

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

Converter (ADC)

SDA

XXXXA3A2A1A0XD7D6D5D4D3D2D1D0X

Fig.9 3-wire serial bus protocol.

MGG365

TDA8752

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

DDD

V

CCO

∆V

V

i(RGB)

I

o

T

stg

T

amb

T

j

CC

analog supply voltage −0.3 +7.0 V
digital supply voltage −0.3 +7.0 V
logic input voltage −0.3 +7.0 V
output stages supply voltage −0.3 +7.0 V
supply voltage differences

V
V
V
V

CCA
CCO
CCA
CCA

− V

− V

− V

− V

CCD

CCD
DDD
CCO

, V

, V

CCO

CCD

− V

− V

DDD

DDD

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

−1.0 +1.0 V

RGB input voltage range referenced to AGND −0.3 +7.0 V
output current − 10 mA
storage temperature −55 +150 °C
operating ambient temperature 0 70 °C
junction temperature − 150 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 52 K/W

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

1997 Jun 04 20

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

CHARACTERISTICS

V

= V11 (or V19, V27 or V99) referenced to AGND (V13, V21, V29 or V96 = 4.75 to 5.25 V; V

CCA

referenced to DGND (V86) = 4.75 to 5.25 V; V

= V40 referenced to V

DDD

(V41) = 4.75 to 5.25 V; V

SSD

(or V69, V79 or V85) referenced to OGND (V48, V60, V70 or V82) = 4.75 to 5.25 V; AGND, DGND, OGND and V
shorted together. T

= 0 to 70 °C; typical values measured at V

amb

CCA=VDDD=VCCD=VCCO

= 5 V and T

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

CCA

V

CCD

V

DDD

V

CCO

I

CCA

I

DDD

I

CCD

I

CCO

I

CCO(PLL)

I

CCA(PLL)

∆V

CC

P

tot

P

off

analog supply voltage 4.75 5.0 5.25 V
digital supply voltage 4.75 5.0 5.25 V
logic supply voltage 4.75 5.0 5.25 V
output stages supply voltage 4.75 5.0 5.25 V
analog supply current − 120 − mA
logic supply current for I2C-bus and 3-wire − 1.0 − mA
digital supply current − 40 − mA
output stages supply current ramp input; f

=80MHz − 6 − mA

CLK

output PLL supply current − 5 − mA
analog PLL supply current − 28 − mA
supply voltage differences

V

CCA−VCCD

V

CCO−VCCD

V

CCA

V

CCA

− V

− V

DDD
CCO

, V
, V

CCO

CCD

− V

− V

DDD
DDD

total power consumption ramp input; f
power consumption in

=80MHz − 1.0 − W

CLK

−0.25 − +0.25 V

−0.25 − +0.25 V

−0.25 − +0.25 V

−0.25 − +0.25 V

− 87 − mW

power-off mode

CCD

= V95

CCO

amb

= V59

=25°C,

SSD

R, G and B amplifiers

B bandwidth −3 dB; T
t

set

settling time of the block ADC
plus AGC

full-scale (black-to-white)
transition; input signal

amb

settling time<1ns;
1 to 99%; T

G

COARSE

coarse gain range V

= 2.5 V; minimum

ref

coarse gain register;
code = 32; (see Fig.6)

maximum coarse gain
register; code = 99;
(see Fig.6)

G

FINE

fine gain correction range fine register input code = 0;

(see Fig.7)
fine register input

code = 31; (see Fig.7)

1997 Jun 04 21

=25°C 250 −−MHz

− 4.5 6 ns

=25°C

amb

−−1.67 − dB

− 8 − dB

− 0 − dB

−−0.5 − dB

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆G

/T amplifier gain stability as a

amp

function of temperature

I

GC

t

stab

gain current −±20 −µA
amplifier gain adjustment

speed

V

i(p-p)

input voltage range
(peak-to-peak value)

t

r(Vi)

t

f(Vi)

G

E(rms)

input voltage rise time fi= 80 MHz; square wave −−1ns
input voltage fall time fi= 80 MHz; square wave −−1ns
channel-to-channel gain

matching (RMS value)

Clamps

P

CLP

t

COR1

precision black level noise on RGB

clamp correction time to within
±10 mV

t

COR2

clamp correction time to less
than 1 LSB

t

W(CLP)

CLP

E

clamp pulse width 500 − 2000 ns
channel-to-channel clamp

matching

A

off

code clamp reference clamp register input

V

= 2.5 V with

ref

100 ppm/°C maximum
variation

HSYNC active; capacitors
on pins 8, 16 and 24 = 22 nF

corresponding to full-scale
output

maximum coarse gain;
T

=25°C

amb

minimum coarse gain;

=25°C

T

amb

channels = 10 mV (max.)
(RMS value); T

amb

=25°C

±100 mV black level input
variation

±100 mV black level input
variation

code = 0
clamp register input

code = 255

−−200 ppm/°C

− 25 − mdB/µs

0.4 − 1.2 V

− 1 − %

− 2 − %

−1 − +1 LSB

−−300 ns

−−10 lines

−1 − +1 LSB

−−63.5 − LSB

− 64 − LSB

Phase-locked loop

j

PLL(rms)

long term PLL jitter
(RMS value)

f

=60MHz − 450 − ps

CLK

f

=80MHz − 250 − ps

CLK

DR divider ratio without divide-by-2 15 − 2047
f

ref

reference clock frequency

15 − 280 kHz

range

f

PLL

t

COASTmax

t

recap

t

cap

Φ

step

output clock frequency range 12 − 80 MHz
maximum coast mode time −−40 lines
PLL recapture time when coast mode is aborted − 3 − lines
PLL capture time in start-up conditions −−5ms
phase shift step T

=25°C − 11.25 − deg

amb

1997 Jun 04 22

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ADCs

f

s

INL DC integral non linearity from IC analog input to

DNL DC differential non linearity from IC analog input to

ENOB effective number of bits from IC analog input to

Signal-to-noise ratio

S/N signal-to-noise ratio maximum gain;

Spurious free dynamic range

SFDR spurious free dynamic range maximum gain;

Clock timing output (CKADCO, CKBO and CKAO)

η

ext

f

CLK(max)

maximum sampling frequency TDA8752/6 60 −−MHz

TDA8752/8 80 −−MHz

−±0.5 tbf LSB
digital output; ramp input;
f

=80MHz

CLK

−±0.5 tbf LSB
digital output; ramp input;
f

=80MHz

CLK

− 7.4 − bits
digital output; 10 kHz sine
wave input; ramp input;
f

= 80 MHz; note 1

CLK

− tbf − dB

=80MHz

f

CLK

minimum gain;
f

=80MHz

CLK

− tbf − dB

− tbf − dB

f

=80MHz

CLK

minimum gain;
f

=80MHz

CLK

− tbf − dB

ADC clock duty cycle 80 MHz output 45 50 55 %
maximum clock frequency 80 −−MHz

Clock timing input (CKEXT)

f

CLK(max)

t

CPH

t

CPL

Data timing (see Fig.10); f
t

s(d)

t

o(d)

t

o(h)

maximum clock frequency 80 −−MHz
clock pulse width HIGH 5.7 −−ns
clock pulse width LOW 5.7 −−ns

= 80 MHz; CL= 10 pF; note 2

CLK

sampling delay time referenced to CKADCO −−6−ns
output delay time − 6.5 tbf ns
output hold time − 3.5 tbf ns

3-state output delay time; (see Fig.11)
t

dZH

t

dZL

t

dHZ

t

dLZ

output enable HIGH − tbf − ns
output enable LOW − tbf − ns
output disable HIGH − tbf − ns
output disable LOW − tbf − ns

1997 Jun 04 23

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

TTL outputs; ADC data outputs and PLL clock output

V

OL

V

OH

I

OL

I

OH

TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP)

V

IL

V

IH

I

IL

I

IH

Z

i

C

i

3-wire serial bus

t

reset

t

su

t

h

2

I

C-bus; (see note 3)

f

SCL

t

BUF

t

HD;STA

t

SU;STA

t

CKL

t

CKH

t

SU;DAT

t

HD;DAT

t

r

t

f

t

SU;STOP

C

L(bus)

LOW level output voltage Io=1mA −−0.8 V
HIGH level output voltage Io= − 1 mA 2.4 −−V
LOW level output current VOL= 0.4 V − tbf − mA
HIGH level output current VOH= 2.7 V − tbf − mA

LOW level input voltage −−0.8 V
HIGH level input voltage 2.0 −−V
LOW level input current VIL= 0.4 V 400 −−µA
HIGH level input current VIH= 2.7 V −−100 µA
input impedance − 4 − kΩ
input capacitance − 4.5 − pF

reset time of the chip before

− 600 − ns

3-wire communication
data set-up time − 100 − ns

data hold time − 100 − ns

clock frequency 0 − 100 kHz
time the bus must be free

4.7 −−µs

before new transmission can
start

start condition hold time 4.0 −−µs
start condition set-up time repeated start 4.7 −−µs
LOW level clock period 4.7 −−µs
HIGH level clock period 4.0 −−µs
data set-up time 250 −−ns
data hold time tbf −−ns
SDA and SCL rise time for f
SDA and SCL fall time for f

= 100 kHz −−1.0 µs

SCL

= 100 kHz −−300 ns

SCL

stop condition set-up time 4.0 −−µs
capacitive load for each bus

−−400 pF

line

1997 Jun 04 24

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

Notes to the characteristics

1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST
frequency). Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

2. Output data acquisition is available after the maximum delay time td, which is the time during which the data is
available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then
be rechecked.

3. The I2C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of
400 kbit/s (400 kHz).

handbook, full pagewidth

CKADCO

t

CPH

n

t

CPL

50 % = 1.4 V

DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR

V

lN

I

n − 1

I

n

t

ds

sample N

sample N + 1

Fig.10 Timing diagram.

2.4 V

I

n + 1

t

d

t

h

sample N + 2

I

n + 2

1.4 V

0.4 V

MGL103

1997 Jun 04 25

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

OE

output

data

output

data

V

CCD

t

dLZ

LOW

10%

HIGH

t

dZL

handbook, full pagewidth

50%

t

dHZ

HIGH

90%

LOW

TDA8752

50%

t

dZH

50%

3.3 kΩ

10 pF

S1

TDA8752

V

CCD

tOE= 100 kHz.

Fig.11 Timing diagram and test conditions of 3-state output delay time.

Table 12 Test conditions for Fig.11

TEST SWITCH S1

t

dLZ

t

dZl

t

dHZ

t

dZH

V

CCD

V

CCD

GND
GND

OE

MGD695

1997 Jun 04 26

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

APPLICATION INFORMATION

handbook, full pagewidth

40 nF

CZ

V

CCA(PLL)

n.c.

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

n.c.

DEC2

V

ref

DEC1

n.c.

RAGC

RBOT

RCLP
RDEC
CCAR

RIN

GAGC
GBOT

GCLP
GDEC
CCAG

GIN

BAGC

BBOT

BCLP

CCAB

BIN

n.c.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 40 4132 4233 4334 4435 4536 4637 4738 4839 49 50

2.5 V

RIN

GIN

BIN

10 nF

10 nF

100 nF

75 Ω or 50 Ω

10 nF

10 nF

100 nF

75 Ω or 50 Ω

10 nF

10 nF

100 nF

75 Ω or 50 Ω

10 nF

1.5 nF

22 nF

10 nF

22 nF

10 nF

22 nF

10 nF

RGAINC

V

AGNDR

GGAINC

V

AGNDG

BGAINC

BCDEC
V

AGNDB

150 pF

CP

AGNDPLL

V

CCD

COAST

CKREF

CKEXT

INV

TDA8752

HSYNC

PWOFF

CLP

OE

V

CCO(PLL)

DGND

CKBO

CKADCO

OGNDPLL

CKAO

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

TDA8752

CKREFO
V

CCOR
R7
R6
R5
R4
R3
R2
R1
R0
OGNDR

V

CCOG
G7
G6
G5
G4
G3
G2
G1
G0
OGNDG

V

CCOB
B7
B6
B5
B4
B3
B2
B1
n.c.

n.c.

ADD1

TCK

2

I

C/3W

ADD2

All supply pins have to be decoupled, with two capacitors:
one for high frequencies (approximately 1 nF) and one for the low frequencies (approximately 100 nF or higher).

DIS

TDO

SEN

SCL

V

DDD

V

V

DDD

SSD

4.7
kΩ

SDA

V

DDD

4.7
kΩ

Fig.12 Application diagram.

1997 Jun 04 27

BORRORn.c.

B0

n.c.GORn.c.

OGNDB

MGG371

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

PACKAGE OUTLINE

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

80 51

81

50

Z

A

E

TDA8752

SOT317-2

pin 1 index

100

1

w M

b

e

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

p

D

H

D

cE

0.25

0.14

D

20.1

19.9

p

0.40

0.25

0 5 10 mm

(1)

(1) (1)(1)

14.1

13.9

30

Z

D

scale

eH

H

24.2

0.65

23.6

31

D

e

H

E

w M

b

p

v M

A

B

v M

B

LLpQZywv θ

E

18.2

17.6

1.0

0.6

A

2

A

E

1.4

1.2

A

1

detail X

0.15 0.10.21.95

Q

(A )

3

θ

L

p

L

Z

E

D

1.0

0.6

o

7

o

0

0.8

0.4

OUTLINE

VERSION

SOT317-2

IEC JEDEC EIAJ

REFERENCES

1997 Jun 04 28

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17
95-02-04

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

TDA8752

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1997 Jun 04 29

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital

TDA8752

Converter (ADC)

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Short-form specification The data in this specification is extracted from a full data sheet with the same type

number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2

PURCHASE OF PHILIPS I

C COMPONENTS

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

2

C components conveys a license under the Philips’ I2C patent to use the

1997 Jun 04 30

Philips Semiconductors Preliminary specification

Triple high speed Analog-to-Digital
Converter (ADC)

TDA8752

NOTES

1997 Jun 04 31

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
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Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

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Hungary: seeAustria
India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd.

Worli, MUMBAI 400 018, Tel. [phone], Fax. [phone]

Indonesia: see Singapore
Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,

TEL AVIV 61180, Tel. [phone], Fax. [phone]
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,

20124 MILANO, Tel. [phone], Fax. [phone]
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,

Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

Tel. [phone], Fax. [phone]
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

Tel. [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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South America: Rua do Rocio 220, 5th floor, Suite 51,
04552-903 São Paulo, SÃO PAULO - SP, Brazil,
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Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone], Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547047/1200/03/pp32 Date of release: 1997 Jun 04 Document order number: 9397 750 02265