Datasheet TDA8730 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8730

PLL FM demodulator for DBS
signals

Preliminary specification
File under Integrated Circuits, IC02

March 1991

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

FEATURES

• Broadband IF amplifier

• PLL demodulator, consisting of:

– a multiplier
– a voltage controlled oscillator
– a loop amplifier

GENERAL DESCRIPTION

The TDA8730 is a sensitive PLL
demodulator for the second IF and
direct broadcasting satellite (DBS)
receivers. It provides AGC output and
threshold adjustment for optimal signal
level at the input of the demodulator.

• AGC detector and DC amplifier

• LOW impedance video and data output

• Power supply voltage stabilizer

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V
I
V
f
f

V
V

DD

DD

I
osc
osc

O

AGC

supply voltage − 9 − V
supply current − 75 − mA
input voltage level − 70 − dBµV
minimum oscillator frequency − 130 − MHz
maximum oscillator frequency − 720 − MHz
video output signal amplitude (peak-to-peak

value)
AGC output voltage 1.8 − V

note 1 − 1.1 − V

DD

V

Note

1. ∆f = 13.5 MHz (peak-to-peak value)

ORDERING AND PACKAGE INFORMATION

EXTENDED TYPE

NUMBER

PINS PIN POSITION MATERIAL CODE

PACKAGE

TDA8730 16 DIL plastic SOT38GE

Note

1. SOT38-1; 1996 December 4.

(1)

March 1991 2

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

PINNING

SYMBOL PIN DESCRIPTION

AGCO 1 AGC output
AGCFC 2 AGC frequency compensation
OSCIN1 3 oscillator input 1
GND 4 GND
OSCIN2 5 oscillator input 2
GND1 6 ground 1
VDO 7 variable capacitor drive output
FI 8 feedback input
VO 9 video output
GND2 10 ground 2
SDN 11 stabilizer decoupling node

Fig.1 Pinning diagram.

V

DD

RFIN2 13 RF input 2
RFIN1 14 RF input 1
RFGND 15 RF ground
AGCTS 16 AGC threshold setting

12 supply voltage +9V

APPLICATIONS

Direct broadcasting satellite (DBS) receivers.

March 1991 3

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

Fig.2 Block diagram.

March 1991 4

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

FUNCTIONAL DESCRIPTION

The TDA8730 is a PLL FM
demodulator intended for use in
satellite tuners. It can
demodulate frequency
deviations ranging from

13.5 MHz

(DBS services) up

(p-p)

to 25 MHz(p-p) (FSS services)
and offers a high demodulation
linearity. The circuit is optimized
for operation at 479.5 MHz (the
European IF for satellite tuners)
and can handle the various
broadcasting standards that are
in use (including MAC).
Due to the PLL principle,
demodulation noise threshold
extension is possible. The high
sensitivity of the balanced IF
input reduces the additional
gain, required in the tuner.
An on chip AGC circuit delivers a
gain control signal for use by the
tuner IF amplifier, and a voltage
regulator makes the circuit
insensitive supply voltage
changes.

LIMITING VALUES

In accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

I

DD

I

O(source)

V

AGC

t

sc

V

AGC(adj)

T

stg

T

j

T

amb

supply voltage −0.3 11 V
input voltage −0.3 V

DD

output source current − 10 mA
AGC output voltage − 11 V
max short circuit time of outputs 10 − s
AGC threshold adjustment voltage −0.3 V

DD

storage temperature −55 150 °C
junction temperature − 150 °C
operating ambient temperature −25 85 °C

THERMAL RESISTANCE

SYMBOL PARAMETER TYP. MAX. UNIT

R

th j-a

from-junction-to-ambient in free air 55 − K/W

V

V

March 1991 5

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

CHARACTERISTICS

= 9V;T

V

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.UNIT

Supply

V

DD

I

DD

Frequency demodulator

f

osc

f

osc

V

i

S11

Kd phase detector constant (level at pin 13 is 70 dBµV) − 0.45 − V/rad.
Ko VCO constant − 12 − MHz/V
Ao open loop gain of loop amplifier pin 7 to pin 8 − 40 − dB
f-3 dB open loop bandwidth of loop amplifier − 2.8 − MHz
Z

in

Z

out

le VCO linearity error over ∆f = ±10 MHz note 4 − 1 − %

V

VCO

G

d

φ

d

MOD intermodulation note 6 −−70 − dB

= 25 °C; f = 480 MHz; Input level 70 dBµV; measured in circuit of Fig.4 unless otherwise specified.

amb

supply voltage V
supply current I

to pin 10 or pin15 8.1 9.0 9.9 V

pin 12

; note 1 − 75 90 mA

pin 12

minimum oscillator frequency −−130 − MHz
maximum oscillator frequency −−720 − MHz
operating input level pin 13; note 2 − 70 74 dBµV
input reflection coefficient S11
unbalanced; pin 14 decoupled (50 Ω

reference)

pin 13; note 3 − 0.07 −

balanced; 100 Ω reference pin 13 to pin 14 − 0.11 −

input impedance of feedback input pin 8 − 930 −Ω
output impedance of loop amplifier pin 7 − 30 50 Ω

shift of DC level at video output for
∆V

= ±10%

DD

pin 9 −−±50 mV

with unmodulated 480 MHz input signal
drift of DC level at video output for

= 25 to 50 °C

T

amb

pin 9 −−+50 mV

with unmodulated 480 MHz input signal
VCO capture range ±14 −−MHz
differential gain note 5 −−±4%
differential phase note 5 −−±2 deg.

AGC

V

IAGC

AGC threshold (IAGC = 0 mA) as a
function of voltage applied to pin 16

= 0.8 V −−67 dBµV

V

pin16

V

= 9.0 V note 7 73 −−dBµV

pin 16

pin 13

AGC steepness pin 1; note 8 − 18 − mA/dB
AGC output saturation voltage HIGH at

V

pin 1

I = −0.2 mA
AGC output saturation voltage LOW at

I = 0.2 mA

March 1991 6

to pin 10 or pin 15

VDD-0.5 − V

DD

− 1.8 2.3 V

V

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX.UNIT

Video output

V

O

video output signal amplitude
(∆f = 13.5 MHz p-p)

V

O(DC)

Z

O

Z

L

DC level of video output pin 9 to pin 10 or pin 15;

output impedance pin 9 − 30 50 Ω
AC load impedance pin 9; note 10 600 −−Ω

Voltage regulator

V
V
I

load

ref

reg

reference voltage for  I
line regulation 8.1 V ≤ VIN ≤ 9.9 V pin 11 − 70 − mV
allowable load current pin 11 −1 − 0mA

≤1 mA pin 11; note 11 − 7 − V

load

Notes

1. The supply current is the consumption of the circuit only.
The current consumption of this application is given by the addition of the supply current of the circuit plus the current
consumption of external components in the application given. In this event (Fig.4) the typical current is 80 mA.

2. The circuit of Fig.4 is designed for an input level of 70 dBµV.
The maximum allowable input level for PLL design is 74 dBµV.
However, for levels other than 70 dBµV the optimum loop filter values will be different from those given in Fig.4.

3. In the application circuit of Fig.4 the RF input is asymmetrically driven.
In order to reduce the influence of oscillator signal coupling to the RF inputs, it is recommended to use a symmetrical
drive at both inputs.

4. The linearity is specified as the maximum difference between the slope df/dV at the channel centre frequency
(480 MHz) and the slope at 480 MHz ± 10 MHz.

5. Measurements with test signals in accordance with CCIR Rec. 473-3; Fm signal with DBS parameters: pre-and
de-emphasis in accordance with CCIR Rec. 405-1, 625 lines PAL TV system. Modulator sensitive 13.5 MHz/V at
pre-emphasis cross over frequency 1 V(p-p) video signal at pre-emphasis filter input.

6. For the intermodulation measurement, an FM test signal is applied having the following modulating components:

1.5 MHz reference sinewave with a deviation of 9.45 MHz(p-p), 5.5 and 5.75 MHz sinewaves with deviation

5.6 MHz(p-p) (so 4.5 dB below the reference, see Fig.3). At the demodulator output the 2nd order intermodulation is
defined according to Fig.3. The video output is loaded with 500 Ω resistor + DC blocking capacitor.

7. The voltage applied at pin 16 is allowed to be higher than the minimum supply voltage (8.1 V).

8. The voltage at the AGC output (pin 1) decreases when the RF input level at pin 13 increases above the adjusted
AGC threshold.

9. The DC level at the video output decreases when the RF input frequency increases.
The DC level at the video output (pin 9) is measured with the VCO switched off because when the oscillator is
operating, the DC level is dependent on the application (oscillator into the input).

10. The load impedance must have at least the minimum value for a frequency range from DC to the bandwidth of the
i.f. filter (usually 27 MHz) since wide-band noise components will also appear at the video output.

11. It is possible to use the regulator output voltage (pin 11). The maximum current allowed is 1 mA.
Possible application as voltage reference source for AFC circuit.

pin 9 to pin 10 or pin 15

note 9

− 1.1 − V

3.1 3.5 3.9 V

March 1991 7

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

Fig.3 IM2 product.

Fig.4 Application information.

March 1991 8

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

PACKAGE OUTLINE

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

D

seating plane

L

Z

16

pin 1 index

e

b

b

1

9

SOT38-1

M

E

A

2

A

A

1

w

M

E

c

(e )

1

M

H

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

UNIT

mm

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

A

max.

4.7 0.51 3.7

OUTLINE
VERSION

SOT38-1

min.

A

1 2

max.

0.15

IEC JEDEC EIAJ

050G09 MO-001AE

b

1.40

1.14

0.055

0.045

b

0.53

0.38

0.021

0.015

1

cEe M

0.32

0.23

0.013

0.009

REFERENCES

(1) (1)

D

21.8

21.4

0.86

0.84

March 1991 9

8

6.48

6.20

0.26

0.24

e

0.30

1

0.15

0.13

M

L

3.9

3.4

E

8.25

7.80

0.32

0.31

EUROPEAN

PROJECTION

H

9.5

0.2542.54 7.62

8.3

0.37

0.010.100.0200.19

0.33

ISSUE DATE

w

92-10-02
95-01-19

Z

max.

2.2

0.087

(1)

Philips Semiconductors Preliminary specification

PLL FM demodulator for DBS signals TDA8730

SOLDERING
Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and
surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for
surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often
used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

Soldering by dipping or by wave

The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the
joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
be necessary immediately after soldering to keep the temperature within the permissible limit.

(order code 9398 652 90011).

). If the printed-circuit board has been pre-heated, forced cooling may

stg max

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more
than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

March 1991 10