• High signal-to-noise ratio over a large analog input
frequency range (7.7 effective bits at 4.43 MHz
full-scale input at f
= 80 MHz)
clk
• Overflow/underflow 3-state TTL output
APPLICATIONS
High-speed analog-to-digital conversion for:
• video data digitizing
• radar pulse analysis
• transient signal analysis
• high energy physics research
•Σ∆ modulators
• medical imaging.
• TTL compatible digital inputs
• Low-level AC clock input signal allowed
GENERAL DESCRIPTION
• External reference voltage regulator
• Power dissipation only 340 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
The TDA8714 is an 8-bit high-speed Analog-to-Digital
Converter (ADC) for professional video and other
applications. It converts the analog input signal into 8-bit
binary-coded digital words at a maximum sampling rate of
80 MHz. All digital inputs and outputs are TTL compatible,
although a low-level sine wave clock input signal is
allowed.
QUICK REFERENCE DATA
SYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNIT
V
V
V
I
CCA
I
CCD
I
CCO
CCA
CCD
CCO
analog supply voltage4.755.05.25V
digital supply voltage4.755.05.25V
output stages supply voltage4.755.05.25V
analog supply current−2530mA
digital supply current−2733mA
output stages supply current−1620mA
INLDC integral non-linearity−±0.4±0.5LSB
DNLDC differential non-linearity−±0.2±0.35LSB
AINLAC integral non-linearitynote 1−±0.5±1.0LSB
f
D11data output; bit 1
D02data output; bit 0 (LSB)
n.c.3not connected
V
RB
n.c.5not connected
AGND6analog ground
V
CCA
V
I
V
RT
n.c.10not connected
O/UF11overflow/underflow data output
D712data output; bit 7 (MSB)
D613data output; bit 6
D514data output; bit 5
D415data output; bit 4
CLK16clock input
DGND17digital ground
V
CCD
V
CCO1
OGND20output ground
V
CCO2
CE22chip enable input (TTL level input,
D323data output; bit 3
D224data output; bit 2
4reference voltage BOTTOM input
7analog supply voltage (+5 V)
8analog input voltage
9reference voltage TOP input
18digital supply voltage (+5 V)
19supply voltage for output stages 1
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOLPARAMETERCONDITIONSMIN.MAX.UNIT
V
CCA
V
CCD
V
CCO
∆V
∆V
∆V
V
I
V
clk(p-p)
I
O
T
stg
T
amb
T
j
CC
CC
CC
analog supply voltagenote 1−0.3+7.0V
digital supply voltagenote 1−0.3+7.0V
output stages supply voltagenote 1−0.3+7.0V
supply voltage differences between
V
and V
CCA
CCD
supply voltage differences between
V
and V
CCO
CCD
supply voltage differences between
V
and V
CCA
CCO
−1.0+1.0V
−1.0+1.0V
−1.0+1.0V
input voltagereferenced to AGND−0.3+7.0V
AC input voltage for switching
may have any value between −0.3 V and +7.0 V provided the difference
CCD
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOLPARAMETERVALUEUNIT
R
th j-a
thermal resistance from junction to ambient in free air
analog supply voltage4.755.05.25V
digital supply voltage4.755.05.25V
output stages supply voltage4.755.05.25V
analog supply current−2530mA
digital supply current−2733mA
output stages supply current−1620mA
C
LOCK INPUT CLK (REFERENCED TO DGND); note 1
V
IL
V
IH
I
IL
I
IH
Z
I
C
I
LOW level input voltage0−0.8V
HIGH level input voltage2.0−V
LOW level input currentV
HIGH level input currentV
input impedancef
input capacitancef
INPUT CE (REFERENCED TO DGND); see Table 2
V
IL
V
IH
I
IL
I
IH
LOW level input voltage0−0.8V
HIGH level input voltage2.0−V
LOW level input currentVIL= 0.4 V−400−−µA
HIGH level input currentVIH= 2.7 V−−20µA
VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
I
IL
I
IH
Z
I
C
I
LOW level input currentVI= 1.2 V−0−µA
HIGH level input currentVI= 3.5 V60130280µA
input impedancefi= 4.43 MHz−10−kΩ
input capacitancefi= 4.43 MHz−14−pF
Reference voltages for the resistor ladder; see Table 1
V
V
V
I
ref
R
TC
V
V
V
RB
RT
diff
LAD
RLAD
osB
osT
i(p-p)
reference voltage BOTTOM1.21.31.6V
reference voltage TOP3.53.63.9V
differential reference voltage VRT− V
RB
reference current−11.5−mA
resistor ladder−200−Ω
temperature coefficient of the resistor ladder−0.24−ppm
offset voltage BOTTOMnote 2275285295mV
offset voltage TOPnote 2305315325mV
analog input voltage (peak-to-peak value)1.451.752.15V
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.
2. Analog input voltages producing code 00 up to and including FF:
a) V
b) V
3. Full-scale sine wave (fi= 4.43 MHz; f
4. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.
No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.
5. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
6. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
7. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
8. Measurement carried out using video analyser VM700A where the video analog signal is reconstructed through a
digital-to-analog converter.
9. Output data acquisition: the output data is available after the maximum delay time of td; in the event of 80 MHz clock
operation, the hardware design must take into account the tdand th limits with respect to the input characteristics of
the acquisition circuit.
(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
osB
the reference voltage BOTTOM (VRB) at T
(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
The analog and digital supplies should be separated and decoupled.
The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value.
(1) VRB and VRT are decoupled to AGND.
(2) Pin 5 should be connected to AGND; pins 3 and 10 to DGND in order to prevent noise influence.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all SO and
SSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
(order code 9398 652 90011).
SSOP
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
METHOD (SO AND SSOP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
SO
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
1997 Oct 2919
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
Objective specificationThis data sheet contains target or goal specifications for product development.
Preliminary specificationThis data sheet contains preliminary data; supplementary data may be published later.
Product specificationThis data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Oct 2920
Page 21
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands547047/1200/06/pp24 Date of release: 1997 Oct 29Document order number: 9397 75002956
Page 22
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