Datasheet tda8708b DATASHEETS (Philips)

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

TDA8708B

Video analog input interface

Product speciﬁcation Supersedes data of June 1994 File under Integrated Circuits, IC02

1996 Nov 26

Page 2

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

FEATURES

• 8-bit resolution

• Sampling rate up to 32 MHz

• Binary or two’s complement 3-state TTL outputs

• TTL-compatible digital inputs and outputs

APPLICATIONS

• Video signal decoding

• Scrambled TV (encoding and decoding)

• Digital picture processing

• Frame grabbing.

• Internal reference voltage regulator

• Power dissipation of 365 mW (typical)

• Input selector circuit (one out of three video inputs)

• Clamp and Automatic Gain Control (AGC) functions for

CVBS and Y signals

• No sample-and-hold circuit required

GENERAL DESCRIPTION

The TDA8708B is an analog input interface for video signal processing. It includes a video amplifier with clamp and gain control, an 8-bit Analog-to-Digital Converter (ADC) with a sampling rate of 32 MHz and an input selector.

• The TDA8708B has no white peak control in mode 2 whereas the TDA8708A has control in modes 1 and 2

• In-range output (not TTL levels).

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V V V I

CCA

CCD

CCO

CCA CCD CCO

analog supply voltage 4.5 5.0 5.5 V digital supply voltage 4.5 5.0 5.5 V TTL output supply voltage 4.2 5.0 5.5 V analog supply current − 37 45 mA digital supply current − 24 30 mA

TTL output supply current − 12 16 mA ILE DC integral linearity error −−±1 LSB DLE DC differential linearity error −−±0.5 LSB f

clk(max)

maximum clock frequency 30 32 − MHz B maximum −3 dB bandwidth (AGC ampliﬁer) 12 18 − MHz P

tot

total power dissipation − 365 500 mW

ORDERING INFORMATION

TYPE NUMBER

TDA8708BT SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1996 Nov 26 2

PACKAGE

NAME DESCRIPTION VERSION

Page 3

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

BLOCK DIAGRAM

handbook, full pagewidth

video input 0 video input 1 video input 2

clamp capacitor

connection

AGC capacitor

connection

in-range

output

video input

selection bit 0

16 17

SELECTOR

sync level

sync pulse

video input selection bit 1

INPUT

AGC &

CLAMP

LOGIC

MODE

SELECTION

27 26

VIDEO

AMPLIFIER

black level sync pulse

analog

voltage

output

digital V

(+ 5 V)

ADC input

19 2014 15

AMP.

TDA8708B

PEAK LEVEL

DIGITAL COMPARATOR

BLACK LEVEL

DIGITAL COMPARATOR

SYNC LEVEL

DIGITAL COMPARATOR

CCD

8 22

digital

ground

clock

decoupling

input

521 7

8 - bit

ADC

analog V

CCA

(+ 5 V)

TTL outputs V (+ 5 V)

TTL

OUTPUTS

analog ground

CCO

9 1

2 3

4 10 11 12 13

output format/

chip enable

(3-state input)

D7 D6 D5 D4 D3 D2 D1 D0

MSA672

1996 Nov 26 3

Fig.1 Block diagram.

Page 4

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

PINNING

SYMBOL PIN DESCRIPTION

D7 1 data output; bit 7 (MSB) D6 2 data output; bit 6 D5 3 data output; bit 5 D4 4 data output; bit 4 CLK 5 clock input V V

CCD CCO

6 digital supply voltage (+5 V)

7 TTL outputs supply voltage (+5 V) DGND 8 digital ground OF 9 output format/chip enable

(3-state input) D3 10 data output; bit 3 D2 11 data output; bit 2 D1 12 data output; bit 1 D0 13 data output; bit 0 (LSB) I0 14 video input selection bit 0 I1 15 video input selection bit 1 VIN0 16 video input 0 VIN1 17 video input 1 VIN2 18 video input 2 ANOUT 19 analog voltage output ADCIN 20 analog-to-digital converter input DEC 21 decoupling input V

CCA

22 analog supply voltage (+5 V) AGND 23 analog ground CLAMP 24 clamp capacitor connection AGC 25 AGC capacitor connection GATE B 26 black level synchronization pulse GATE A 27 sync level synchronization pulse IR 28 in-range output

CLK

CCD

CCO

DGND

OF D3 D2 D1 D0

TDA8708B

9 10 11 12 13

MSA671

Fig.2 Pin configuration.

28 27 26 25 24 23 22 21 20 19 18 17 16 1514

IR GATE A GATE B

AGC

CLAMP

AGND

CCA

DEC ADCIN ANOUT VIN2

VIN1 VIN0

1996 Nov 26 4

Page 5

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

FUNCTIONAL DESCRIPTION

The TDA8708B provides a simple interface for decoding video signals.

The TDA8708B operates in configuration mode 1 (see Fig.4) when the video signals are weak (i.e. when the gain of the AGC amplifier has not yet reached its optimum value). This enables a fast recovery of the synchronization pulses in the decoder circuit. When the pulses at the GATE A and GATE B inputs become distinct (GATE A and GATE B pulses are synchronization pulses occurring during the sync period and rear porch respectively) the TDA8708B automatically switches to configuration mode 2 (see Fig.5).

When the TDA8708B is in configuration mode 1, the gain of the AGC amplifier will be roughly adjusted (sync level to a digital output level of 0 and the peak level to a digital output level of 255).

The voltage across the capacitor connected to the AGC pin controls the gain of the video amplifier. This is the gain control loop.

The sync level comparator is active during a positive-going pulse at the GATE A input. This means that the sync pulse of the composite video signal is used as an amplitude reference. The bottom of the sync pulse is adjusted to obtain a digital output of logic 0 at the converter output. As the black level is at digital level 64, the sync pulse will have a digital amplitude of 64 LSBs.

The use of nominal signals will prevent the output from exceeding a digital code of 213.

The clamp level control is accomplished by using the same techniques as used for the gain control. The black-level digital comparator is active during a positive-going pulse at the GATE B input. The clamp capacitor will be charged or discharged to adjust the digital output to code 64.

In configuration mode 2 the digital output of the ADC is compared to internal digital reference levels.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V V V ∆V

V I

T T T

CCA CCD CCO

stg amb j

analog supply voltage −0.3 +7.0 V digital supply voltage −0.3 +7.0 V TTL output supply voltage −0.3 +7.0 V supply voltage differences:

− V

V V V

CCA CCO CCA

− V

CCD

CCO

input voltage −0.3 V

−1.0 +1.0 V

CCA

output current 0 +10 mA storage temperature −55 +150 °C operating ambient temperature 0 +70 °C junction temperature 0 +125 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

th j-a

thermal resistance from junction to ambient in free air 70 K/W

1996 Nov 26 5

Page 6

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

CHARACTERISTICS

CCA=V22

shorted together; V T

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

CCA

CCD

CCO

CCA

CCD

CCO

Video ampliﬁer inputs

VIN0 V

I(p-p)

 input impedance fi= 6 MHz 10 20 − kΩ

Z

I0 AND I1 TTL INPUTS (see Table 1) V

GATE A AND GATE B TTL INPUTS (see Figs 4 and 5) V

AGC INPUT (PIN 25) V

25(min)

25(max)

CLAMP V

to V23= 4.5 to 5.5 V; V

CCA

to V

= −0.5 to +0.5 V; V

CCD

CCD=V6

to V8= 4.5 to 5.5 V; V

= 0 to +70 °C; typical readings taken at V

analog supply voltage 4.5 5.0 5.5 V digital supply voltage 4.5 5.0 5.5 V TTL output supply voltage 4.2 5.0 5.5 V analog supply current − 37 45 mA digital supply current − 24 30 mA TTL output supply current TTL load (see Fig.8) − 12 16 mA

TO VIN2 INPUTS

input voltage (peak-to-peak value) AGC load with external

input capacitance fi= 6 MHz − 1 − pF

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current VI= 0.4 V −400 −−µA HIGH level input current VI= 2.7 V −− 20 µA

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current VI= 0.4 V −400 −−µA HIGH level input current VI= 2.7 V −− 20 µA pulse width see Fig.5 2 −−µs

AGC voltage for minimum gain − 2.8 − V AGC voltage for maximum gain − 4.0 − V AGC output current see Table 2

INPUT (PIN 24)

clamp voltage for code 128 output − 3.5 − V clamp output current see Table 3

to V

CCO

CCA=VCCD=VCCO

= −0.5 to +0.5 V; V

CCD

capacitor; note 1

CCO=V7

= 5 V and T

to V8= 4.2 to 5.5 V; AGND and DGND

to V

CCA

=25°C; unless otherwise speciﬁed.

amb

= −0.5 to +0.5 V;

CCO

0.6 − 1.5 V

CCD

1996 Nov 26 6

Page 7

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Video ampliﬁer outputs

ANOUT OUTPUT (PIN 19) V

19(p-p)

AC output voltage (peak-to-peak value)

O(p-p)

internal current source RL= ∞ 2.0 2.5 − mA output current driven by the load V

DC output voltage for black level note 3 − V output impedance − 20 −Ω

Video ampliﬁer dynamic characteristics

diff

crosstalk between VIN inputs V differential gain V

differential phase V

B −3 dB bandwidth 12 −−MHz S/N signal-to-noise ratio note 4 60 −−dB SVRR1 supply voltage ripple rejection note 5 − 45 − dB ∆G gain range see Fig.10 −4.5 − +6.0 dB G

stab

gain stability as a function of supply voltage and temperature

= 1.33 V (p-p);

VIN

− 1.33 − V

V25= 3.6 V

ANOUT

= 1.33 V (p-p);

−− 1.0 mA

note 2

− 2.24 − V

CCA

= 4.75 to 5.25 V −−50 −45 dB

CCA

= 1.33 V (p-p);

VIN

− 2 − %

V25= 3.6 V

= 1.33 V (p-p);

VIN

− 0.8 − deg

V25= 3.6 V

see Fig.10 −− 5%

Analog-to-digital converter inputs

INPUT (PIN 5)

CLK V

| input impedance f

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current V HIGH level input current V

input capacitance f OF INPUT (3-STATE; see Table 4) V

LOW level input voltage 0 − 0.2 V

HIGH level input voltage 2.6 − V

input voltage in high impedance state − 1.15 − V

LOW level input current −370 −300 −µA

HIGH level input current − 300 450 µA

CCD

= 0.4 V −400 −−µA

clk

= 2.7 V −− 100 µA

clk

= 10 MHz − 4 − kΩ

clk

= 10 MHz − 4.5 − pF

clk

CCD

1996 Nov 26 7

Page 8

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

ADCIN INPUT (PIN 20; see Table 5) V

20(p-p)

input voltage digital output = 00 − V

input voltage digital output = 255 − V

input voltage amplitude

− 1.0 − V

(peak-to-peak value) I

 input impedance fi= 6 MHz − 50 − MΩ

Z

input current − 1.0 10 µA

input capacitance fi= 6 MHz − 1 − pF

Analog-to-digital converter outputs

OUTPUT (PIN 28)

LOW level output voltage −− 1.7 V

HIGH level output voltage 1.9 −−V

output current −500 −−µA DIGITAL OUTPUTS D0 TO D7 V

LOW level output voltage IOL= 2 mA 0 − 0.6 V

HIGH level output voltage IOL= −0.4 mA 2.4 − V

output current in 3-state mode 0.4 V < VO<V

CCD

−20 − +20 µA

Switching characteristics

clk(max)

Analog signal processing (f

diff

maximum clock input frequency see Fig.6; note 6 30 32 − MHz

= 32 MHz); see Fig.8

clk

differential gain V20= 1.0 V (p-p);

− 2 − %

see Fig.7; note 7

diff

all

differential phase see Fig.7; note 7 − 2 − deg

fundamental harmonics (full-scale) fi= 4.43 MHz; note 7 −− 0dB

harmonics (full-scale);

fi= 4.43 MHz; note 7 −−55 − dB

all components SVRR2 supply voltage ripple rejection note 8 − 1 5 %/V

− 2.42 − V

CCA

− 1.41 − V

CCA

CCD

Transfer function (see Fig.8) ILE DC integral linearity error −− ±1 LSB

DLE DC differential linearity error −− ±0.5 LSB ILE AC integral linearity error note 9 −− ±2 LSB

Timing (f

IGITAL OUTPUTS (C

dEZ

dDZ

= 32 MHz) see Figs 6, 7 and 8

clk

sampling delay time − 2 − ns

output hold time 6 8 − ns

output delay time − 16 20 ns

3-state delay time; output enable − 19 25 ns

3-state delay time; output disable − 14 20 ns

1996 Nov 26 8

= 15 pF; IOL= 2 mA; RL=2kΩ)

Page 9

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

Notes

1. 0 dB is obtained at the AGC amplifier when applying V

2. The output current at pin 19 should not exceed 1 mA. The load impedance RL should be referenced to V defined as:

a) AC impedance ≥1kΩ and the DC impedance >2.7 kΩ. b) The load impedance should be coupled directly to the output of the amplifier so that the DC voltage supplied by

the clamp is not disturbed.

3. Control mode 2 is selected.

i(p-p)

= 1.33 V.

CCA

and

4. Signal-to-noise ratio measured with 5 MHz bandwidth: .

20 log

--- N

ANOUTC p p–()

------------------------------------------------ V

ANOUTY (RMSnoise)

atB=5MHz=

5. The voltage ratio is expressed as:

SVRR1 20log

∆V

-----------------V

CCA

for V

×=

-------∆ G

= 1 V (p-p), gain at 100 kHz = 1 and 1 V supply variation.

6. It is recommended that the rise and fall times of the clock are ≥2 ns. In addition, a ‘good layout’ for the digital and analog grounds is recommended.

7. These measurements are realized on analog signals after a digital-to-analog conversion (TDA8702 is used).

8. The supply voltage rejection is the relative variation of the analog signal (full-scale signal at input) for 1 V of supply variation:

∆ V

I00()VIFF()

SVRR2

-----------------------------------------------------------------------------------------------------

9. Full-scale sine wave (f

–()V

∆V

CCA

= 4.4 MHz; f

–()+

I00()VIFF()

= 27 MHz).

clk

1996 Nov 26 9

Page 10

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

Table 1 Video input selection (CVBS)

I1 I0 SELECTED INPUT

0 0 VIN0 0 1 VIN1 1 0 VIN2 1 1 VIN2

Table 2 AGC output current

GATE A GATE B

DIGITAL

OUTPUT

AGC

MODE

(1)

1 1 output < 255 −2.5 µA1

output > 255 130 µA1

(2)

− 0 µA2

1 0 output < 0 +2.5 µA2

output > 0 −2.5 µA2

Notes

1. Mode 2 can only be initialized with successive pulses on GATE A and GATE B (see Fig.5).

2. X = don’t care.

Table 3 CLAMP output current

GATE A GATE B

DIGITAL OUTPUT

CLAMP

1 1 output < 0 130 µA1

output > 0 −2.5 µA1

(1)

0X 0µA2

0 1 output < 64 +50 µA2

64 < output −50 µA2

Note

1. X = don't care.

Table 4 OF input coding

OF D0 TO D7

0 active, two’s complement 1 high impedance

(1)

open circuit

active, binary

Note

1. Use C ≥ 10 pF to DGND.

MODE

Table 5 Output coding and input voltage (typical values)

BINARY OUTPUTS TWO’S COMPLEMENT

STEP V

ADCIN

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Underﬂow − 0000000010000000

− 2.41 V 0000000010000000

CCA

1 − 0000000110000001

. − ................

254 − 1111111001111110 255 V

− 1.41 V 1111111101111111

CCA

Overﬂow − 1111111101111111

1996 Nov 26 10

Page 11

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

handbook, full pagewidth

0.25 V

5 MHz sine wave

1.0 V

0.25 V

, full pagewidth

digital

output

level

255

64 µs

MBB959

Fig.3 Test signal on the ADCIN pin for differential gain and phase measurements.

MBB969

peak-level gain control

black-level

clamping

sync-level gain control

GATE A

time

1996 Nov 26 11

GATE B

MODE 1

Fig.4 Control mode 1.

Page 12

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

handbook, full pagewidth

digital output

level

255

MSA674

black-level

clamping

sync-level control

GATE A

GATE B

MODE 2

time

Fig.5 Control mode 2.

handbook, full pagewidth

CLK input

analog input (ADCIN)

data outputs D0 to D7)

sample N 2

sample N 1

data N 1

Fig.6 Timing diagram for data output.

1996 Nov 26 12

sample N

clock input reference level (1.5 V)

sample N 1

2.4 V

data N 1data Ndata N 2data N 3

0.4 V

MBB958

Page 13

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

handbook, full pagewidth

OF input

data outputs (D0 to D7)

two's complement

Fig.7 Output format timing diagram.

handbook, halfpage

dDZ

high impedance

dEZ

CCO

open

2.4 V

binary

0.4 V

MBB968

2 kΩ

Fig.8 Load circuit for timing measurement; data outputs (OF = LOW or open-circuit).

1996 Nov 26 13

D0 to D7

MBD865

15 pF

DGND

IN916

IN3064

Page 14

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

CCO

handbook, halfpage

2 kΩ

D0 to D7

MBB955

kΩ

DGND

IN916

IN3064

Fig.9 Load circuit for timing measurement; 3-state outputs (OF: fi= 1 MHz; VOF= 3 V).

MSA676

G

(dB)

5 %

(1) Typical value (V (2) Minimum and maximum values (temperature and supply).

CCA=VCCD

1996 Nov 26 14

= 5 V; T

2.6 4.6

=25°C).

amb

3 3.4 3.8 4.2

(1) (2)

Fig.10 Gain control curve.

V (V)

Page 15

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

INTERNAL PIN CIRCUITRY

CCA

CCO

pin 6

CCD

pin 7

pin 22

pin 24

CLAMP

pin 8

DGND

pin 23

AGND

CCA

CCD

AGC

pin 25

CCD

pins 26 or 27

GATE A or GATE B

CCD

pin 28

DGND

AGND

DGND

CCA

TDA8708B

AGND

CCA

top

CCA

mid V

REF

2.5

bottom

AGND

MSA675

pin 21

pin 20

pin 19

DEC

ADCIN

handbook, full pagewidth

ANOUT

Fig.11 Internal pin configuration.

DGND

CCO

pins 1 to 4

data outputs

and 10 to 13

DGND

CCD

1.5 V

DGND

pin 5

clock input

1996 Nov 26 15

CCD

4 V

chip enable

binary/

pin 9

two's complement

REF

DGND

CCA

kΩ

pins 14 or 15

I ,I

AGND

pins 16 to 18

VIN0, VIN1 and VIN2

AGND

Page 16

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

APPLICATION INFORMATION

Additional information can be found in the laboratory report of TDA8708A

handbook, full pagewidth

clock

5 V

data outputs

100 Ω

(1)

22 Ω

data outputs

33 pF

22 nF

10 pF

TDA8708B

(2)

horizontal sync

horizontal clamp

220 nF

18 nF

1 µF

4.7 µF

“FBL/AN9308”

10 nF

1µH

5 V

LOW PASS

FILTER

4.7 µF

75 Ω

5 V

(3)

75 Ω

(1) It is recommended to decouple V

device. (2) When IR is not used, it must be connected to ground via a 47 pF capacitor. (3) See Figs 13 and 15 for examples of the low-pass filters.

1996 Nov 26 16

through a 22 Ω resistor especially when the output data of TDA8708B interfaces with a capacitive CMOS load

CCO

MSA673

75 Ω

Fig.12 Application diagram.

Page 17

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

22 µH

book, full pagewidth

ANOUT (pin 19)

This filter can be adapted to various applications with respect to performance requirements. An input and output impedance of at least 680 Ω and 2.2 kΩ must in any event be applied.

680 Ω

12 pF 12 pF

27 pF 68 pF 27 pF

22 µH

CCA

(pin 22)

2.2 kΩ

MBB966 - 1

ADCIN

(pin 20)

Fig.13 Example of a low-pass filter for CVBS and Y signals.

Characteristics of Fig.14:

• Order 5; adapted CHEBYSHEV

handbook, halfpage

(dB)

MSA682

• Ripple ρ≤0.4 dB

• f = 6.5 MHz at −3dB

• f

= 9.75 MHz.

notch

120

160

010 30

Fig.14 Frequency response for filter shown in

Fig.13.

1996 Nov 26 17

f (MHz)

Page 18

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

handbook, full pagewidth

This filter can be adapted to various applications with respect to performance requirements. An input and output impedance of at least 680 Ω and 2.2 kΩ must in any event be applied.

ADOUT (pin 19)

680 Ω

82 µH

2.2 kΩ

15 pF 15 pF

CCA

(pin 22)

MSA678

ADCIN

(pin 20)

Fig.15 Example of an economical low-pass filter for CVBS and Y signals.

Characteristics of Fig.16:

• Order 5; adapted CHEBYSHEV

handbook, halfpage

(dB)

MSA681

• Ripple ρ≤0.4 dB

• f = 6.5 MHz at −3 dB.

010 30

f (MHz)

Fig.16 Frequency response for filter shown in

Fig.15.

1996 Nov 26 18

Page 19

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

PACKAGE OUTLINE

SO28: plastic small outline package; 28 leads; body width 7.5 mm

pin 1 index

w M

SOT136-1

detail X

(A )

v M

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE VERSION

SOT136-1

max.

2.65

0.10

0.30

0.10

0.012

0.004

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1996 Nov 26 19

0 5 10 mm

A2A

2.45

2.25

0.096

0.089

IEC JEDEC EIAJ

075E06 MS-013AE

0.25

0.01

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

(1)E(1) (1)

18.1

7.6

17.7

7.4

0.71

0.30

0.69

0.29

REFERENCES

scale

eHELLpQ

1.27

0.050

10.65

10.00

0.42

0.39

1.4

0.055

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

0.25

0.25 0.1

0.01

EUROPEAN

PROJECTION

ywv θ

0.9

0.4

0.004

ISSUE DATE

0.035

0.016

91-08-13

95-01-24

o o

Page 20

Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

Reﬂow soldering

Reflow soldering techniques are suitable for all SO packages.

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

(order code 9398 652 90011).

Wave soldering

Wave soldering techniques can be used for all SO packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.

• The longitudinal axis of the package footprint must be parallel to the solder flow.

• The package footprint must incorporate solder thieves at the downstream end.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

1996 Nov 26 20

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Philips Semiconductors Product speciﬁcation

Video analog input interface TDA8708B

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

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