Datasheet TDA8705T-C3, TDA8705T-C2, TDA8705T-C1 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of November 1994
File under Integrated Circuits, IC02

1996 Jan 12

INTEGRATED CIRCUITS

TDA8705

6-bit high-speed dual
Analog-to-Digital Converter (ADC)

1996 Jan 12 2

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

FEATURES

• 2 times 6-bit resolution

• Sampling rate up to 40 MHz

• High signal-to-noise ratio over a large analog input

frequency range (5.8 effective bits at 10 MHz full-scale
input at f

clk

= 40 MHz

• TTL output

• Two separated inputs (AC-coupling)

• TTL compatible digital inputs

• Low-level AC clock input signal allowed

• Internal reference voltage regulator

(external reference regulation possible)

• Power dissipation only 250 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

APPLICATIONS

High-speed analog-to-digital conversion for:

• DBS (Digital Broadcast Satellite)

• QPSK (Quadrature Phase Shift Keying) demodulation

• Video.

GENERAL DESCRIPTION

The TDA8705 is a 6-bit high-speed dual analog-to-digital
converter (ADC) for satellite video and other applications.
It converts the two analog input signals into two 6-bit
binary-coded digital words at a maximum sampling rate of
40 MHz. All digital inputs and outputs are TTL compatible,
although a low-level sine wave clock input signal is
allowed.

QUICK REFERENCE DATA

Note

1. Full-scale sine wave (f

i

= 10 MHz; f

clk

= 40 MHz).

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current 20 27 32 mA

I

CCD

digital supply current 10 14 18 mA

I

CCO

output stages supply current 10 14 18 mA
ILE DC integral linear error −±0.25 ±0.5 LSB
DLE DC differential linearity error −±0.25 ±0.5 LSB
AILE AC integral linearity error note 1 −±0.5 ±1.0 LSB
f

clk(max)

maximum clock frequency 40 −−MHz
P

tot

total power dissipation − 250 − mW

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8705T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1996 Jan 12 3

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital

Converter (ADC)

TDA8705

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BLOCK DIAGRAM

handbook, full pagewidth

7
AGND

10

DEC

V

RTA

V

CCA

V

CCD

V

CCO

17

18

19

16 D1B

D2B

D3B

D4B

1520D0B

D5B

TTL OUTPUTS

LATCHES

ANALOG -TO-DIGITAL

CONVERTER

B

MLC113

TDA8705

analog ground

data

outputs

LSB

MSB

6

25

26

27

24 D1A

D2A

D3A

D4A

2328D0A

D5A

TTL OUTPUTS

LATCHES

ANALOG -TO-DIGITAL

CONVERTER

A

data

outputs

LSB

MSB

6

9

5

12
14

REGULATOR

CLOCK DRIVER

V

RBA

V

RMA

V

RTB

V

RMB

4

V

IA

R

INTA

R

INTB

6

V

RBB

13

V

IB

11

8 2 21

3
DGND

1

CLK

digital ground

22
OGND

output ground

reference

voltage TOP

A

reference

voltage TOP

B

analog

voltage input

A

reference

voltage BOTTOM

A

analog

voltage input

B

reference

voltage BOTTOM

B

reference

voltage MIDDLE

A

reference

voltage MIDDLE

B

Fig.1 Block diagram.

1996 Jan 12 4

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input
V

CCD

2 digital supply voltage (+5 V)
DGND 3 digital ground
V

RBA

4 reference voltage BOTTOM for

ADC A (decoupling)

V

RTA

5 reference voltage TOP for ADC A

(decoupling)

V

IA

6 analog input voltage for ADC A
AGND 7 analog ground
V

CCA

8 analog supply voltage (+5 V)
V

RMA

9 reference voltage MIDDLE for ADC A

(decoupling)
DEC 10 decoupling input
V

IB

11 analog input voltage for ADC B

V

RTB

12 reference voltage TOP for ADC B

(decoupling)
V

RBB

13 reference voltage BOTTOM for

ADC B (decoupling)
V

RMB

14 reference voltage MIDDLE for ADC B

(decoupling)
D0B 15 data output; bit 0 (LSB), ADC B
D1B 16 data output; bit 1, ADC B
D2B 17 data output; bit 2, ADC B
D3B 18 data output; bit 3, ADC B
D4B 19 data output; bit 4, ADC B
D5B 20 data output; bit 5 (MSB), ADC B
V

CCO

21 supply voltage for output stages

(+5 V)
OGND 22 output ground
D0A 23 data output; bit 0 (LSB), ADC A
D1A 24 data output; bit 1, ADC A
D2A 25 data output; bit 2, ADC A
D3A 26 data output; bit 3, ADC A
D4A 27 data output; bit 4, ADC A
D5A 28 data output; bit 5 (MSB), ADC A

Fig.2 Pin configuration.

handbook, halfpage

1
2
3
4
5
6
7
8

9
10
11
12
13

28
27
26
25
24
23
22
21

20
19
18
17
16
1514

TDA8705

CLK

DGND

V

IA

V

CCD

V

RBA

V

RTA

V

RMA

V

IB

V

RTB

V

RBB

V

RMB

V

CCA

AGND

DEC

D5B
D4B
D3B

D2B
D1B

D0B

D3A

D2A
D1A
D0A

V

CCO

OGND

D5A
D4A

MLC114

1996 Jan 12 5

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Note

1. The supply voltages V

CCA

, V

CCO

and V

CCD

may have any value between −0.3 V and +7.0 V provided the difference

between V

CCA

, V

CCO

and V

CCD

is between −1 V and +1 V.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage note 1 −0.3 +7.0 V

V

CCD

digital supply voltage note 1 −0.3 +7.0 V

V

CCO

output stages supply voltage note 1 −0.3 +7.0 V

∆V

CC

supply voltage differences
between V

CCA

and V

CCD

−1.0 +1.0 V

∆V

CC

supply voltage differences
between V

CCO

and V

CCD

−1.0 +1.0 V

∆V

CC

supply voltage differences
between V

CCA

and V

CCO

−1.0 +1.0 V

V

I

input voltage referenced to AGND −0.3 +7.0 V

V

clk(p-p)

AC input voltage for switching
(peak-to-peak value)

referenced to DGND − V

CCD

V

I

O

output current − 10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 +70 °C

T

j

junction temperature − +150 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 70 K/W

1996 Jan 12 6

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

CHARACTERISTICS

V

CCA=V8

to V7= 4.75 to 5.25 V; V

CCD=V2

to V3= 4.75 to 5.25 V; V

CCO=V21

to V22= 4.75 to 5.25 V; AGND, OGND

and DGND shorted together; V

CCA

to V

CCD

= −0.25 to +0.25 V; V

CCO

to V

CCD

= −0.25 to +0.25 V;

V

CCA

to V

CCO

= −0.25 to +0.25 V; T

amb

= 0 to +70 °C; typical values measured at V

CCA=VCCD=VCCO

= 5 V and

T

amb

=25°C; CL= 15 pF; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply

V

CCA

analog supply voltage 4.75 5.0 5.25 V

V

CCD

digital supply voltage 4.75 5.0 5.25 V

V

CCO

output stages supply voltage 4.75 5.0 5.25 V

I

CCA

analog supply current 20 27 32 mA

I

CCD

digital supply current 10 14 18 mA

I

CCO

output stages supply current 10 14 18 mA

Inputs

C

LOCK INPUT CLK; REFERENCED TO DGND; note 1

V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current V

clk

= 0.4 V −1 − +1 µA

I

IH

HIGH level input current V

clk

= 2.7 V −−20 µA

Z

I

input impedance f

clk

= 40 MHz − 2 − kΩ

C

I

input capacitance f

clk

= 40 MHz − 2 − pF

V

I

ANALOG INPUT VOLTAGE FOR A AND B; REFERENCED TO AGND

R

I

DC parallel input resistance 20 −−kΩ

C

I

parallel input capacitance fi = 10 MHz − 1.5 − pF

α

CT

crosstalk between VIA and V

IB

fi = 10 MHz 40 −−dB
Reference voltages for the resistor ladder A and B; see Table 1
V

RB

reference voltage BOTTOM 1.9 2.0 2.1 V

V

RT

reference voltage TOP 2.8 2.9 3.0 V

V

diff

differential reference voltage VRT− V

RB

0.85 0.90 0.95 V

I

ref

reference current − 2 − mA

R

LAD

resistor ladder − 450 −Ω

TC

RLAD

temperature coefficient of the resistor
ladder

− 3280 − ppm

V

osB

offset voltage BOTTOM note 2 − 200 − mV

V

osT

offset voltage TOP note 2 − 200 − mV

V

i(p-p)

input voltage amplitude
(peak-to-peak value)

0.45 0.50 0.55 V

Outputs; A and B

D

IGITAL OUTPUTS D5 TO D0; REFERENCED TO DGND

V

OL

LOW level output voltage IO = 1 mA 0 − 0.4 V

V

OH

HIGH level output voltage IO = −1 mA 2.4 − V

CCD

V

1996 Jan 12 7

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

Switching characteristics

CLOCK INPUT CLK; note 1; see Fig.3
f

clk(max)

maximum clock frequency 40 −−MHz

t

CPH

clock pulse width HIGH 10 −−ns

t

CPL

clock pulse width LOW 10 −−ns

Analog signal processing

L

INEARITY

ILE DC integral linearity error −±0.25 ±0.5 LSB
DLE DC differential linearity error −±0.25 ±0.5 LSB
AILE AC integral linearity error note 3 −±0.5 ±1.0 LSB
OFE offset error between A and B f

i

= 10 MHz;

f

clk

= 40 MHz; note 4

±1 −±2 LSB

GE gain error between A and B f

i

= 10 MHz;

f

clk

= 40 MHz; note 4

±1 −±2 LSB

MID middle scale output code A and B input voltage floating 31 − 32
B

ANDWIDTH;f

clk

=40MHz

B −0.5 dB analog bandwidth full-scale sine wave;

note 5

− 50 − MHz

t

STLH

analog input settling time LOW-to-HIGH full-scale square wave;

Fig.4; note 6

− 8 − ns

t

STHL

analog input settling time HIGH-to-LOW full-scale square wave;

Fig.4; note 6

− 5 − ns

HARMONICS;f

clk

=40MHZ; see Fig.5

h

1

fundamental harmonics (full scale) fi= 10 MHz −−0dB

h

all

harmonics (full scale);
all components

fi= 10 MHz

second harmonics −−49 − dB
third harmonics −−51 − dB

THD total harmonic distortion f

i

= 10 MHz −−46 −40 dB
SIGNAL-TO-NOISE RATIO; note 7; see Fig.5
S/N signal-to-noise ratio (full scale) without harmonics;

f

clk

= 40 MHz;

fi= 10 MHz

34 37 − dB

EFFECTIVE BITS; note 7; see Figs 5 and 6
EB effective bits f

clk

= 40 MHz

f

i

= 10 MHz − 5.8 − bits

f

i

= 20 MHz − 5.6 − bits
TWO-TONE; note 8
TTIR two-tone intermodulation rejection f

clk

= 40 MHz − 48 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Jan 12 8

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 1 ns.

2. Analog input voltages producing code 00 up to and including 3F:
a) V

osB

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (VRB) at T

amb

=25°C.

b) V

osT

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

produces data outputs equal to 3F at T

amb

=25°C.

3. Full-scale sine wave (fi= 10 MHz; f

clk

= 40 MHz).

4. The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both
ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE
(mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B.

5. The −0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a
full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence.

6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.

7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency
(NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

8. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.1 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

9. Output data acquisition: the output data is available after the maximum delay time of td.

B

IT ERROR RATE

BER bit error rate f

clk

= 40 MHz;
fi= 10 MHz;
VI= ±16 LSB at code 32

− 10

−13

− times/

samples

Timing; f

clk

= 40 MHz; CL= 15 pF; note 9; see Fig.3

t

ds

sampling delay time −−2ns

t

h

output hold time 5 −−ns

t

d

output delay time −−14 ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Jan 12 9

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

Table 1 Output coding and input voltage (typical values; referenced to AGND)

STEP

V

I(p-p)

A or B

(V)

BINARY OUTPUT BITS

D5 D4 D3 D2 D1 D0

Underflow <2.2 000000

0 2.2 000000
1 2.208 000001

. . ......

. . ......

62 2.692 111110
63 2.7 111111

Overflow >2.7 111111

Fig.3 Timing diagram for data output.

handbook, full pagewidth

ds

t

sample N + 1

sample N

CLK

MLC115

sample N + 2

1.4 V

V

l(n)

DATA
D0 to D5

t

d

t

h

CPH

t

CPL

t

2.4 V

0.4 V

1.4 V

DATA

N + 1

DATA

N

DATA

N - 1

DATA

N - 2

Fig.4 Analog input settling-time diagram.

handbook, full pagewidth

MLC116

50 %

STLH

t

2 ns

code 0

code 63

I(n)

50 %

0.5 ns

50 %

2 ns

STHL

t

50 %

0.5 ns

CLK

V

1996 Jan 12 10

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

Fig.5 Typical Fast Fourier Transform; f

clk

= 40 MHz; fi= 10 MHz.

Effective bits: 5.83; THD = −46.31 dB;
Harmonic levels (dB): 2nd = −51.85; 3rd = −51.11; 4th = −55.73; 5th = −59.89; 6th = −52.68.

handbook, full pagewidth

7.53

0

120

0 2.51 5.02

MLC372

40

80

17.610.0 12.6 15.1 20.1
f (MHz)

100

20

60

amplitude

(dB)

Fig.6 Typical Fast Fourier Transform; f

clk

= 40 MHz; fi= 20 MHz.

Effective bits: 5.65; THD = −41.79 dB;
Harmonic levels (dB): 2nd = −51.73; 3rd = −42.51; 4th = −65.18; 5th = −57.48; 6th = −58.98.

handbook, full pagewidth

7.51

0

120

0 2.50 5.0

MLC373

40

80

17.510.0 12.5 15.0 20.0
f (MHz)

100

20

60

amplitude

(dB)

1996 Jan 12 11

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

APPLICATION INFORMATION

Fig.7 Application diagram.

The analog and digital supplies should be separated and decoupled.
V

RT(n)

, V

RM(n)

and V

RB(n)

and DEC inputs are decoupled to AGND.

(1) In the event of AC-coupling, C

LA

and CLB values are chosen in accordance with the classical low frequencies cut-off formulae

where input resistance R

I

is the value measured under DC conditions.

In the event of DC-coupling, C

LA

and CLB capacitors are omitted. The DC biassing and AC modulation signal directly applied to inputs (pin 6 and 11),

must be in the range of V

RT(n)

− V

RB(n)

.

(2) When pin 10 (DEC) is short-circuited to AGND, an external regulator can be connected to V

RT(n)

and V

RB(n)

.

f

CL

1

2 π RICL×××

------------------------------------- -

=

handbook, full pagewidth

MLC117

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

5 V

CLK

V

CCD

DGND

V

IA

V

RBA

V

RTA

V

RMA

V

IB

V

RTB

V

RBB

V

RMB

V

CCA

AGND

DEC

D5B
D4B
D3B
D2B
D1B
D0B

D3A
D2A
D1A
D0A

V

CCO

OGND

D5A
D4A

5 V

5 V

input A

input B

TDA8705

100 nF

100 nF

100 nF
100 nF

100 nF
100 nF

1 nF

100 nF
100 nF
100 nF

(2)

C

C

(1)

(1)

LA

LB

1996 Jan 12 12

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

PACKAGE OUTLINE

UNIT

A

max.

A

1

A2A3b

p

cD

(1)E(1) (1)

eHELLpQ

Z

ywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

18.1

17.7

7.6

7.4

1.27

10.65

10.00

1.1

1.0

0.9

0.4

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT136-1

X

14

28

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

c

L

v M

A

e

15

1

(A )

3

A

y

0.25

075E06 MS-013AE

pin 1 index

0.10

0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.71

0.69

0.30

0.29

0.050

1.4

0.055

0.419

0.394

0.043

0.039

0.035

0.016

0.01

0.25

0.01

0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO28: plastic small outline package; 28 leads; body width 7.5 mm

SOT136-1

95-01-24
97-05-22

1996 Jan 12 13

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SO
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Jan 12 14

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1996 Jan 12 15

Philips Semiconductors Product specification

6-bit high-speed dual Analog-to-Digital
Converter (ADC)

TDA8705

NOTES

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SCDS47 © Philips Electronics N.V. 1996

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537021/1100/02/pp16 Date of release: 1996 Jan 12
Document order number: 9397 750 00568