Datasheet tda8705 DATASHEETS (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

TDA8705

6-bit high-speed dual Analog-to-Digital Converter (ADC)

Product speciﬁcation Supersedes data of November 1994 File under Integrated Circuits, IC02

1996 Jan 12

Page 2

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

FEATURES

• 2 times 6-bit resolution

• Sampling rate up to 40 MHz

• High signal-to-noise ratio over a large analog input

frequency range (5.8 effective bits at 10 MHz full-scale input at f

• TTL output

• Two separated inputs (AC-coupling)

• TTL compatible digital inputs

• Low-level AC clock input signal allowed

• Internal reference voltage regulator

(external reference regulation possible)

• Power dissipation only 250 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

= 40 MHz

clk

TDA8705

APPLICATIONS

High-speed analog-to-digital conversion for:

• DBS (Digital Broadcast Satellite)

• QPSK (Quadrature Phase Shift Keying) demodulation

• Video.

GENERAL DESCRIPTION

The TDA8705 is a 6-bit high-speed dual analog-to-digital converter (ADC) for satellite video and other applications. It converts the two analog input signals into two 6-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V V V I

CCA

CCD

CCO

CCA CCD CCO

analog supply voltage 4.75 5.0 5.25 V digital supply voltage 4.75 5.0 5.25 V output stages supply voltage 4.75 5.0 5.25 V analog supply current 20 27 32 mA digital supply current 10 14 18 mA

output stages supply current 10 14 18 mA ILE DC integral linear error −±0.25 ±0.5 LSB DLE DC differential linearity error −±0.25 ±0.5 LSB AILE AC integral linearity error note 1 −±0.5 ±1.0 LSB f

clk(max)

tot

maximum clock frequency 40 −−MHz

total power dissipation − 250 − mW

Note

1. Full-scale sine wave (f

= 10 MHz; f

= 40 MHz).

clk

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8705T SO28 plastic small outline package; 28 leads; body width 7.5 mm SOT136-1

1996 Jan 12 2

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Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

BLOCK DIAGRAM

data

outputs

D2A

D3A

TTL OUTPUTS

LATCHES

24 D1A

LSB

D0A 23

CCO

CCD

MSB

D5A 28

D4A 27

TDA8705

MSB

D5B 20

D4B 19

data

outputs

D2B

D3B

TTL OUTPUTS

LATCHES

16 D1B

TDA8705

LSB

D0B 15

MLC113

CLK

CLOCK DRIVER

CCA

DEC

8 2 21

REGULATOR

RTA

reference

voltage TOP

CONVERTER

ANALOG -TO-DIGITAL

analog

voltage input

DGND

digital ground

INTA

RBA

reference

voltage BOTTOM

9512

RMA

reference 

voltage MIDDLE

RTB

RMB

reference

voltage TOP

INTB

reference 

voltage MIDDLE

CONVERTER

ANALOG -TO-DIGITAL

analog

voltage input

RBB

reference

voltage BOTTOM

AGND

OGND

handbook, full pagewidth

Fig.1 Block diagram.

analog ground

output ground

1996 Jan 12 3

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Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input V

CCD

DGND 3 digital ground V

RBA

RTA

AGND 7 analog ground V

CCA

RMA

DEC 10 decoupling input V

RTB

RBB

RMB

D0B 15 data output; bit 0 (LSB), ADC B D1B 16 data output; bit 1, ADC B D2B 17 data output; bit 2, ADC B D3B 18 data output; bit 3, ADC B D4B 19 data output; bit 4, ADC B D5B 20 data output; bit 5 (MSB), ADC B V

CCO

OGND 22 output ground D0A 23 data output; bit 0 (LSB), ADC A D1A 24 data output; bit 1, ADC A D2A 25 data output; bit 2, ADC A D3A 26 data output; bit 3, ADC A D4A 27 data output; bit 4, ADC A D5A 28 data output; bit 5 (MSB), ADC A

2 digital supply voltage (+5 V)

4 reference voltage BOTTOM for

ADC A (decoupling)

5 reference voltage TOP for ADC A

(decoupling)

6 analog input voltage for ADC A

8 analog supply voltage (+5 V) 9 reference voltage MIDDLE for ADC A

(decoupling)

11 analog input voltage for ADC B 12 reference voltage TOP for ADC B

(decoupling)

13 reference voltage BOTTOM for

ADC B (decoupling)

14 reference voltage MIDDLE for ADC B

(decoupling)

21 supply voltage for output stages

(+5 V)

handbook, halfpage

CLK

CCD

DGND

RBA

RTA

AGND

CCA

RMA DEC

RTB

RBB

RMB

TDA8705

9 10 11 12 13

MLC114

Fig.2 Pin configuration.

TDA8705

D5A

D4A

D3A

26 25

D2A D1A

D0A

OGND

CCO

D5B

D4B

D3B

18 17

D2B

D1B D0B

1514

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Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

CCA

CCD

CCO

∆V

clk(p-p)

stg

amb

analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage differences

between V

CCA

and V

CCD

supply voltage differences between V

CCO

and V

CCD

supply voltage differences between V

CCA

and V

CCO

−1.0 +1.0 V

input voltage referenced to AGND −0.3 +7.0 V AC input voltage for switching

referenced to DGND − V

CCD

(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C operating ambient temperature 0 +70 °C junction temperature − +150 °C

TDA8705

Note

1. The supply voltages V between V

CCA

, V

CCO

CCA

and V

, V

and V

CCO

is between −1 V and +1 V.

CCD

may have any value between −0.3 V and +7.0 V provided the difference

CCD

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

th j-a

thermal resistance from junction to ambient in free air 70 K/W

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Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital

TDA8705

Converter (ADC)

CHARACTERISTICS

CCA=V8

and DGND shorted together; V V

CCA

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply

CCA

CCD

CCO

CCA

CCD

CCO

Inputs

LOCK INPUT CLK; REFERENCED TO DGND; note 1

ANALOG INPUT VOLTAGE FOR A AND B; REFERENCED TO AGND

Reference voltages for the resistor ladder A and B; see Table 1 V

diff

ref

LAD

osB

osT

i(p-p)

to V7= 4.75 to 5.25 V; V

to V

= −0.25 to +0.25 V; T

CCO

CCA

CCD=V2

to V

amb

to V3= 4.75 to 5.25 V; V

= −0.25 to +0.25 V; V

CCD

= 0 to +70 °C; typical values measured at V

=25°C; CL= 15 pF; unless otherwise speciﬁed.

analog supply voltage 4.75 5.0 5.25 V digital supply voltage 4.75 5.0 5.25 V output stages supply voltage 4.75 5.0 5.25 V analog supply current 20 27 32 mA digital supply current 10 14 18 mA output stages supply current 10 14 18 mA

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current V HIGH level input current V input impedance f input capacitance f

DC parallel input resistance 20 −−kΩ parallel input capacitance fi = 10 MHz − 1.5 − pF crosstalk between VIA and V

reference voltage BOTTOM 1.9 2.0 2.1 V reference voltage TOP 2.8 2.9 3.0 V differential reference voltage VRT− V reference current − 2 − mA resistor ladder − 450 −Ω

RLAD

temperature coefﬁcient of the resistor ladder

offset voltage BOTTOM note 2 − 200 − mV offset voltage TOP note 2 − 200 − mV input voltage amplitude

(peak-to-peak value)

CCO=V21

to V

CCO

= 0.4 V −1 − +1 µA

clk

= 2.7 V −−20 µA

clk

= 40 MHz − 2 − kΩ

clk

= 40 MHz − 2 − pF

clk

to V22= 4.75 to 5.25 V; AGND, OGND

= −0.25 to +0.25 V;

CCD

CCA=VCCD=VCCO

= 5 V and

CCD

fi = 10 MHz 40 −−dB

0.85 0.90 0.95 V

− 3280 − ppm

0.45 0.50 0.55 V

Outputs; A and B

IGITAL OUTPUTS D5 TO D0; REFERENCED TO DGND

LOW level output voltage IO = 1 mA 0 − 0.4 V HIGH level output voltage IO = −1 mA 2.4 − V

1996 Jan 12 6

CCD

Page 7

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital

TDA8705

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Switching characteristics

CLOCK INPUT CLK; note 1; see Fig.3 f

clk(max)

CPH

CPL

Analog signal processing

INEARITY

ILE DC integral linearity error −±0.25 ±0.5 LSB DLE DC differential linearity error −±0.25 ±0.5 LSB AILE AC integral linearity error note 3 −±0.5 ±1.0 LSB OFE offset error between A and B f

GE gain error between A and B f

MID middle scale output code A and B input voltage ﬂoating 31 − 32

ANDWIDTH;f

B B −0.5 dB analog bandwidth full-scale sine wave;

STLH

STHL

HARMONICS;f h

all

THD total harmonic distortion f SIGNAL-TO-NOISE RATIO; note 7; see Fig.5 S/N signal-to-noise ratio (full scale) without harmonics;

EFFECTIVE BITS; note 7; see Figs 5 and 6 EB effective bits f

TWO-TONE; note 8 TTIR two-tone intermodulation rejection f

maximum clock frequency 40 −−MHz clock pulse width HIGH 10 −−ns clock pulse width LOW 10 −−ns

= 40 MHz

clk

= 10 MHz;

= 40 MHz; note 4

clk

= 10 MHz;

= 40 MHz; note 4

clk

±1 −±2 LSB

− 50 − MHz

note 5

analog input settling time LOW-to-HIGH full-scale square wave;

− 8 − ns

Fig.4; note 6

analog input settling time HIGH-to-LOW full-scale square wave;

− 5 − ns

Fig.4; note 6

=40MHZ; see Fig.5

clk

fundamental harmonics (full scale) fi= 10 MHz −−0dB harmonics (full scale);

fi= 10 MHz

all components

second harmonics −−49 − dB third harmonics −−51 − dB

= 10 MHz −−46 −40 dB

34 37 − dB

= 40 MHz;

clk

fi= 10 MHz

= 40 MHz

clk

= 10 MHz − 5.8 − bits

= 20 MHz − 5.6 − bits

= 40 MHz − 48 − dB

clk

1996 Jan 12 7

Page 8

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital

TDA8705

Converter (ADC)

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

IT ERROR RATE

BER bit error rate f

= 40 MHz;

clk

− 10 fi= 10 MHz; VI= ±16 LSB at code 32

Timing; f

= 40 MHz; CL= 15 pF; note 9; see Fig.3

clk

sampling delay time −−2ns output hold time 5 −−ns output delay time −−14 ns

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns.

2. Analog input voltages producing code 00 up to and including 3F: a) V

b) V

3. Full-scale sine wave (fi= 10 MHz; f

(voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

osB

the reference voltage BOTTOM (VRB) at T

(voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

osT

produces data outputs equal to 3F at T

= 40 MHz).

clk

amb

=25°C.

amb

=25°C.

4. The Offset Error (OFE) and Gain Error (GE) are determined by taking results from a simultaneous acquisition on both ADCs of a sine wave greater than full-scale. The occurrences of code 0 and 63 are used to calculate the OFE (mid-scale-to-mid-scale) and the GE (amplitude difference) between the two converters A and B.

5. The −0.5 dB analog bandwidth is determined by the 0.5 dB reduction in the reconstructed output, the input being a full-scale sine wave. It is determined with a beat frequency method; no glitches occurrence.

6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data.

7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.

8. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.1 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.

9. Output data acquisition: the output data is available after the maximum delay time of td.

−13

− times/

samples

1996 Jan 12 8

Page 9

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital

TDA8705

Converter (ADC)

Table 1 Output coding and input voltage (typical values; referenced to AGND)

A or B

STEP

I(p-p)

(V)

D5 D4 D3 D2 D1 D0

Underﬂow <2.2 000000

0 2.2 000000 1 2.208 000001

. . ......

62 2.692 111110 63 2.7 111111

Overﬂow >2.7 111111

handbook, full pagewidth

CLK

CPL

CPH

BINARY OUTPUT BITS

1.4 V

handbook, full pagewidth

l(n)

DATA D0 to D5

code 63

code 0

CLK

sample N

DATA

N - 2

sample N + 1

DATA

N - 1

DATA

Fig.3 Timing diagram for data output.

STLH

I(n)

50 %

2 ns

50 %

sample N + 2

2 ns

STHL

50 %

DATA

N + 1

2.4 V

1.4 V

0.4 V

MLC115

1996 Jan 12 9

MLC116

0.5 ns

Fig.4 Analog input settling-time diagram.

0.5 ns

Page 10

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

amplitude

(dB)

100

120

0 2.51 5.02

7.53

handbook, full pagewidth

TDA8705

MLC372

17.610.0 12.6 15.1 20.1 f (MHz)

Effective bits: 5.83; THD =−46.31 dB; Harmonic levels (dB): 2nd =−51.85; 3rd =−51.11; 4th = −55.73; 5th = −59.89; 6th = −52.68.

Fig.5 Typical Fast Fourier Transform; f

handbook, full pagewidth

amplitude

(dB)

100

120

0 2.50 5.0

Effective bits: 5.65; THD = −41.79 dB; Harmonic levels (dB): 2nd = −51.73; 3rd = −42.51; 4th = −65.18; 5th = −57.48; 6th = −58.98.

7.51

= 40 MHz; fi= 10 MHz.

clk

MLC373

17.510.0 12.5 15.0 20.0 f (MHz)

1996 Jan 12 10

Fig.6 Typical Fast Fourier Transform; f

= 40 MHz; fi= 20 MHz.

clk

Page 11

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

APPLICATION INFORMATION

handbook, full pagewidth

input A

input B

5 V

100 nF

100 nF 100 nF

1 nF C

100 nF 100 nF 100 nF

5 V

CLK

CCD

DGND V

RBA

RTA

(1)

AGND

CCA

RMA

(2)

DEC

(1)

RTB

RBB

RMB

1 2 3 4 5 6 7

TDA8705

8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

MLC117

D5A D4A D3A D2A D1A D0A OGND

CCO D5B D4B D3B D2B D1B D0B

TDA8705

5 V

100 nF

The analog and digital supplies should be separated and decoupled. V

, V

RT(n)

(1) In the event of AC-coupling, C

(2) When pin 10 (DEC) is short-circuited to AGND, an external regulator can be connected to V

and V

RM(n)

------------------------------------- -

2 π RICL×××

In the event of DC-coupling, C must be in the range of V

and DEC inputs are decoupled to AGND.

RB(n)

where input resistance R

and CLB values are chosen in accordance with the classical low frequencies cut-off formulae

and CLB capacitors are omitted. The DC biassing and AC modulation signal directly applied to inputs (pin 6 and 11),

− V

RB(n)

RT(n)

is the value measured under DC conditions.

Fig.7 Application diagram.

1996 Jan 12 11

RT(n)

and V

RB(n)

Page 12

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

PACKAGE OUTLINE

SO28: plastic small outline package; 28 leads; body width 7.5 mm

TDA8705

SOT136-1

v M

pin 1 index

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

max.

2.65

0.10

0.30

0.10

0.012

0.004

A2A3b

2.45

0.25

2.25

0.096

0.01

0.089

0.49

0.36

0.019

0.014

0.32

0.23

0.013

0.009

(1)E(1) (1)

18.1

7.6

17.7

7.4

0.71

0.30

0.69

0.29

scale

eHELLpQ

1.27

0.050

w M

10.65

10.00

0.42

0.39

1.4

0.055

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

detail X

0.25

0.01

0.25 0.1

0.01

(A )

ywv θ

0.9

0.4

0.035

0.004

0.016

OUTLINE VERSION

SOT136-1

1996 Jan 12 12

REFERENCES

IEC JEDEC EIAJ

075E06 MS-013AE

EUROPEAN

PROJECTION

ISSUE DATE

91-08-13

95-01-24

Page 13

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital Converter (ADC)

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

Reﬂow soldering

Reflow soldering techniques are suitable for all SO packages.

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.

(order code 9398 652 90011).

TDA8705

Wave soldering

Wave soldering techniques can be used for all SO packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.

• The longitudinal axis of the package footprint must be parallel to the solder flow.

• The package footprint must incorporate solder thieves at the downstream end.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

1996 Jan 12 13

Page 14

Philips Semiconductors Product speciﬁcation

6-bit high-speed dual Analog-to-Digital

TDA8705

Converter (ADC)

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1996 Jan 12 14