Datasheet TDA8703T-C4, TDA8702T-C2 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02

1996 Aug 23

INTEGRATED CIRCUITS

TDA8702

8-bit video digital-to-analog
converter

1996 Aug 23 2

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

FEATURES

• 8-bit resolution

• Conversion rate up to 30 MHz

• TTL input levels

• Internal reference voltage generator

• Two complementary analog voltage outputs

• No deglitching circuit required

• Internal input register

• Low power dissipation

• Internal 75 Ω output load (connected to the analog

supply)

• Very few external components required.

APPLICATIONS

• High-speed digital-to-analog conversion

• Digital TV including:

– field progressive scan
– line progressive scan

• Subscriber TV decoders

• Satellite TV decoders

• Digital VCRs.

GENERAL DESCRIPTION

The TDA8702 is an 8-bit Digital-to-Analog Converter
(DAC) for video and other applications. It converts the
digital input signal into an analog voltage output at a
maximum conversion rate of 30 MHz. No external
reference voltage is required and all digital inputs are TTL
compatible.

QUICK REFERENCE DATA

Note

1. D0 to D7 connected to V

CCD

and CLK connected to DGND.

2. The analog output voltages (V

OUT

and V

OUT

) are negative with respect to V

CCA

(see Table 1). The output resistance

between V

CCA

and each of these outputs is typically 75 Ω.

3. The −3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.5 5.0 5.5 V

V

CCD

digital supply voltage 4.5 5.0 5.5 V

I

CCA

analog supply current note 1 − 26 32 mA

I

CCD

digital supply current note 1 − 23 30 mA

V

OUT

− V

OUT

full-scale analog output voltage
(peak-to-peak value)

note 2
Z

L

=10kΩ−1.45 −1.60 −1.75 V

Z

L

=75kΩ−0.72 −0.80 −0.88 V
ILE DC integral linearity error −−±1/2 LSB
DLE DC differential linearity error −−±1/2 LSB
f

CLK

maximum conversion rate −−30 MHz

B −3 dB analog bandwidth f

CLK

= 30 MHz; note 3 − 150 − MHz

P

tot

total power dissipation − 250 340 mW

1996 Aug 23 3

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8702 DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
TDA8702T SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

Fig.1 Block diagram.

handbook, full pagewidth

BAND-GAP

REFERENCE

CURRENT

REFERENCE

LOOP

CURRENT

GENERATORS

CURRENT

SWITCHES

REGISTERS

CLOCK INPUT

INTERFACE

MSA659

DATA

INPUT

INTERFACE

12
11
3
4
10
9
8
7

5

1

2

6

REF

100 nF

DGND
AGND

CLK

(LSB) D0

D1
D2
D3
D4
D5
D6

(MSB) D7

75

Ω

75

Ω

16

15
14

V

CCA

V

OUT

V

OUT

V

CCD

TDA8702/

TDA8702T

13

1996 Aug 23 4

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

PINNING

SYMBOL PIN DESCRIPTION

REF 1 voltage reference (decoupling)
AGND 2 analog ground
D2 3 data input; bit 2
D3 4 data input; bit 3
CLK 5 clock input
DGND 6 digital ground
D7 7 data input; bit 7
D6 8 data input; bit 6
D5 9 data input; bit 5
D4 10 data input; bit 4
D1 11 data input; bit 1
D0 12 data input; bit 0
V

CCD

13 positive supply voltage for digital

circuits (+5 V)

V

OUT

14 analog voltage output

V

OUT

15 complementary analog voltage output

V

CCA

16 positive supply voltage for analog

circuits (+5 V)

Fig.2 Pin configuration.

handbook, halfpage

MSA658

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

TDA8702/

TDA8702T

V

CCA

V

OUT

V

OUT

V

CCD

D0
D1
D4
D5

D6

D7

D3

D2

DGND

CLK

AGND

REF

1996 Aug 23 5

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL RESISTANCE

SYMBOL PARAMETER MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

CCA

− V

CCD

supply voltage differential −0.5 +0.5 V
AGND − DGND ground voltage differential −0.1 +0.1 V
V

I

input voltage (pins 3 to 5 and 7 to 12) −0.3 V

CCD

V

I

OUT/IOUT

total output current (pins 14 and 15) −5 +26 mA
T

stg

storage temperature −55 +150 °C
T

amb

operating ambient temperature 0 +70 °C
T

j

junction temperature − +125 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

from junction to ambient in free air

SOT38-1 70 K/W
SOT162-1 90 K/W

1996 Aug 23 6

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

CHARACTERISTICS

V

CCA=V16

− V2= 4.5 V to 5.5 V; V

CCD=V13

− V6= 4.5 V to 5.5 V; V

CCA

− V

CCD

= −0.5 V to +0.5 V; V

REF

decoupled to

AGND by a 100 nF capacitor; T

amb

=0°C to +70 °C; AGND and DGND shorted together; unless otherwise specified

(typical values measured at V

CCA=VCCD

= 5 V and T

amb

=25°C).

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

analog supply voltage 4.5 5.0 5.5 V

V

CCD

digital supply voltage 4.5 5.0 5.5 V

I

CCA

analog supply current note 1 − 26 32 mA

I

CCD

digital supply current note 1 − 23 30 mA

AGND − DGND ground voltage differential −0.1 − +0.1 V

Inputs

DIGITAL INPUTS (D7 TO D0) AND CLOCK INPUT (CLK)
V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current VI= 0.4 V −−0.3 −0.4 mA

I

IH

HIGH level input current VI= 2.7 V − 0.01 20 µA

f

CLK

maximum clock frequency −−30 MHz

Outputs (note 2; referenced to V

CCA

)

V

OUT

− V

OUT

full-scale analog output voltages
(peak-to-peak value)

ZL=10kΩ−1.45 −1.60 −1.75 V
Z

L

=75Ω−0.72 −0.80 −0.88 V

V

OS

analog offset output voltage code = 0 −−3−25 mV

V

OUT

/TC full-scale analog output voltage

temperature coefficient

−−200 µV/K

V

OS

/TC analog offset output voltage

temperature coefficient

−−20 µV/K

B −3 dB analog bandwidth note 3; f

CLK

= 30 MHz − 150 − MHz

G

diff

differential gain − 0.6 − %

Φ

diff

differential phase − 1 − deg

Z

O

output impedance − 75 −Ω

Transfer function (f

CLK

= 30 MHz)

ILE DC integral linearity error −−±1/2 LSB
DLE DC differential linearity error −−±1/2 LSB

1996 Aug 23 7

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

Note

1. D0 to D7 are connected to V

CCD

, CLK is connected to DGND.

2. The analog output voltages (V

OUT

and V

OUT

are negative with respect to V

CCA

(see Table 1). The output resistance

between V

CCA

and each of these outputs is 75 Ω (typ.).

3. The −3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).

4. The worst case characteristics are obtained at the transition from input code 0 to 255 and if an external load
impedance greater than 75 Ω is connected between V

OUT

or V

OUT

and V

CCA

. The specified values have been

measured with an active probe between V

OUT

and AGND. No further load impedance between V

OUT

and AGND has
been applied. All input data is latched at the rising edge of the clock. The output voltage remains stable (independent
of input data variations) during the HIGH level of the clock (CLK = HIGH). During a LOW-to-HIGH transition of the
clock (CLK = LOW), the DAC operates in the transparent mode (input data will be directly transferred to their
corresponding analog output voltages (see Fig.5).

5. The data set-up (t

SU;DAT

) is the minimum period preceding the rising edge of the clock that the input data must be
stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the rising
edge of the clock and still be recognized. The data hold time (t

HD;DAT

) is the minimum period following the rising edge
of the clock that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge of the clock and still be recognized.

6. The definition of glitch energy and the measurement set-up are shown in Fig.6. The glitch energy is measured at the
input transition between code 127 to 128 and on the falling edge of the clock.

Switching characteristics (f

CLK

= 30 MHz); notes 4 and 5; see Figs 3, 4 and 5

t

SU;DAT

data set-up time −0.3 −−ns

t

HD;DAT

data hold time 2.0 −−ns

t

PD

propagation delay time −−1.0 ns

t

S1

settling time 10% to 90% full-scale

change to ±1 LSB

− 1.1 1.5 ns

t

S2

settling time 10% to 90% full-scale

change to ±1 LSB

− 6.5 8.0 ns

t

d

input to 50% output delay time − 3.0 5.0 ns

Output transients (glitches; (f

CLK

= 30 MHz); note 6; see Fig.6

E

g

glitch energy from code transition 127 to 128 −−30 LSB.ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Aug 23 8

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

Table 1 Input coding and output voltages (typical values; referenced to V

CCA

, regardless of the offset voltage)

CODE

INPUT DATA

(D7 TO D0)

DAC OUTPUT VOLTAGES

Z

L

=10KΩ ZL=75Ω

V

OUT

V

OUT

V

OUT

V

OUT

0 000 00 00 0 −1.6 0 −0.8
1 000 000 01 −0.006 −1.594 −0.003 −0.797

. ........

128 100 000 00 −0.8 −0.8 −0.4 −0.4

. ........

254 111 11110 −1.594 −0.006 −0.797 −0.003
255 111 111 11 −1.6 0 −0.8 0

Fig.3 Data set-up and hold times.

The shaded areas indicate when the input data may change and be correctly registered. Data input update must be completed within 0.3 ns after the
first rising edge of the clock (t

SU;DAT

is negative; −0.3ns). Data must be held at least 2 ns after the rising edge (t

HD;DAT

= +2 ns).

handbook, full pagewidth

HD; DAT

t

input data

CLK

MBC912

SU; DAT

t

3.0 V

1.3 V
0 V

3.0 V

1.3 V
0 V

stable

1996 Aug 23 9

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

Fig.4 Switching characteristics.

handbook, full pagewidth

MBC913

CLK

1.3 V

code 255

1.3 V

code 0

input data
(example of a
full-scale input
transition)

10 %

50 %

90 %

1 LSB

1 LSB

V

CCA

1.6 V

(code 255)

t

d

S1

t

S2

t

PD

t

V

OUT

V

CCA

(code 0)

Fig.5 Latched and transparent mode.

During the transparent mode (CLK = LOW), any change of input data will be seen at the output. During the latched mode (CLK = HIGH), the analog
output remains stable regardless of any change at the input. A change of input data during the latched mode will be seen on the falling edge of the clock
(beginning of the transparent mode).

handbook, full pagewidth

MBC914 - 1

transparent

mode

latched

mode

1.3 V

CLK

input
codes

V

OUT

transparent

mode

latched mode

(stable output)

beginning of

transparent

mode

analog
output
voltage

1996 Aug 23 10

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

Fig.6 Glitch energy measurement.

handbook, full pagewidth

MSA660

HP8082A

HP8082A

PULSE

GENERATOR

(SLAVE)

PULSE

GENERATOR

(SLAVE)

DIVIDER

( 10)

f

CLK/10

(1)

f

CLK/10

(2)

D7 MSB
D6
D5

D4
D3
D2
D1
D0 (LSB)

V

OUT

V

OUT

TDA8702/

TDA8702T

f

CLK

PULSE

GENERATOR

(MASTER)

MODEL EH107

f

CLK

(3)

DYNAMIC

PROBE

OSCILLO-

SCOPE

TEK P6201 TEK7104 and TEK7A26

R = 100 kΩ
C = 3 pF

bandwidth = 20 MHz

clock

3

1

2

timing diagram

code 128

V

OUT

code 127

1 LSB

time

The value of the glitch energy is the sum of the shaded area measured in LSB.ns.

1996 Aug 23 11

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

INTERNAL PIN CONFIGURATIONS

Fig.7 Reference voltage generator decoupling.

handbook, full pagewidth

MBC911 - 1

CCA

V

AGND

V

REF

regulation loop

output current
generators

REF

Fig.8 AGND and DGND.

handbook, halfpage

MBC908

AGND

DGND

substrate

Fig.9 D7 to D0 and CLK.

handbook, halfpage

MBC910

CCA

V

AGND

D0 to D7,
CLK

1996 Aug 23 12

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

Fig.10 Digital supply.

handbook, halfpage

MBC907

V

CCD

DGND

Fig.11 Analog outputs.

handbook, halfpage

MBC909 - 1

CCA

V

OUT

V

bit

n

bit
n

switches and

current generators

AGND

75 Ω75 Ω

V

OUT

Fig.12 Analog supply.

handbook, halfpage

MBC906

V

CCA

AGND

1996 Aug 23 13

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

APPLICATION INFORMATION

Additional application information will be supplied upon request (please quote number FTV/8901).

Fig.13 Analog output voltage without external load (VO= −V

OUT

; see Table 1, ZL=10kΩ).

(1) This is a recommended value for decoupling pin 1.

handbook, halfpage

MSA661

TDA8702/

TDA8702T

V

OUT

AGND

REF

100 nF

(1)

V

CCA

V

O

V

OUT

Fig.14 Analog output voltage with external load (external load ZL=75Ωto ∞).

(1) This is a recommended value for decoupling pin 1.

handbook, full pagewidth

MSA662

TDA8702/

TDA8702T

V

OUT

AGND

REF

100 nF

(1)

V

CCA

Z

L

VOZL/

()

75Z

L

1996 Aug 23 14

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

Fig.15 Analog output with AGND as reference.

(1) This is a recommended value for decoupling pin 1.

handbook, halfpage

MSA663

TDA8702/

TDA8702

V

OUT

AGND

REF

AGND

100 nF

(1)

100 µF

75 Ω

V

CCA

2

V

O

Fig.16 Example of anti-aliasing filter (analog output referenced to AGND).

handbook, full pagewidth

MSA665

39 pF 100 pF 56 pF

390 Ω

27 pF 12 pF

10 µH 12 µH

V

o

390 Ω

100 µF

V

OUT

(pin 15)

or

V

OUT

(pin 14)

TDA8702

[390/(780+75)]

1996 Aug 23 15

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

Fig.17 Frequency response for filter shown in Fig.16.

Characteristics

Order 5; adapted CHEBYSHEV.
Ripple at ≤ 0.1 dB.
f

(−3 dB)

= 6.7 MHz.

f

(NOTCH)

= 9.7 MHz and 13.3 MHz.

handbook, halfpage

01020 40

0

100

20

MSA657

30

40

60

80

f (MHz)

α

(dB)

i

Fig.18 Differential mode (improved supply voltage ripple rejection).

(1) This is a recommended value for decoupling pin 1.

handbook, full pagewidth

MSA664

TDA8702/

TDA8702T

V

OUT

V

OUT

AGND

REF

AGND

100 nF

(1)

100 µF

100 µF

2 X V (R2/R1)

O

R2

R1

R1

R2

1996 Aug 23 16

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

PACKAGE OUTLINES

UNIT

A

max.

1 2

b

1

cEe M

H

L

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT38-1

92-10-02
95-01-19

A

min.

A

max.

b

max.

w

M

E

e

1

1.40

1.14

0.055

0.045

0.53

0.38

0.32

0.23

21.8

21.4

0.86

0.84

6.48

6.20

0.26

0.24

3.9

3.4

0.15

0.13

0.2542.54 7.62

0.30

8.25

7.80

0.32

0.31

9.5

8.3

0.37

0.33

2.2

0.087

4.7 0.51 3.7

0.15

0.021

0.015

0.013

0.009

0.010.100.0200.19

050G09 MO-001AE

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

e

D

A

2

Z

16

1

9

8

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1) (1)

D

(1)

Z

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

1996 Aug 23 17

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

UNIT

A

max.

A

1

A2A

3

b

p

cD

(1)E(1) (1)

eHELLpQ

Z

ywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

10.5

10.1

7.6

7.4

1.27

10.65

10.00

1.1

1.0

0.9

0.4

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT162-1

8

16

w M

b

p

D

detail X

Z

e

9

1

y

0.25

075E03 MS-013AA

pin 1 index

0.10

0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.41

0.40

0.30

0.29

0.050

1.4

0.055

0.419

0.394

0.043

0.039

0.035

0.016

0.01

0.25

0.01

0.004

0.043

0.016

0.01

X

θ

A

A

1

A

2

H

E

L

p

Q

E

c

L

v M

A

(A )

3

A

0 5 10 mm

scale

SO16: plastic small outline package; 16 leads; body width 7.5 mm

SOT162-1

95-01-24
97-05-22

1996 Aug 23 18

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

DIP

SOLDERING BY DIPPING OR BY WA VE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.
Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

W

AVE SOLDERING

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Aug 23 19

Philips Semiconductors Product specification

8-bit video digital-to-analog converter TDA8702

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.