Datasheet TDA8703-C4 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02

1996 Aug 26

INTEGRATED CIRCUITS

TDA8703

8-bit high-speed analog-to-digital
converter

1996 Aug 26 2

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital
converter

TDA8703

FEATURES

• 8-bit resolution

• Sampling rate up to 40 MHz

• High signal-to-noise ratio over a large analog input

frequency range (7.1 effective bits at 4.43 MHz
full-scale input)

• Binary or two's complement 3-state TTL outputs

• Overflow/underflow 3-state TTL output

• TTL compatible digital inputs

• Low-level AC clock input signal allowed

• Internal reference voltage generator

• Power dissipation only 290 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

APPLICATIONS

• General purpose high-speed analog-to-digital
conversion

• Digital TV, IDTV

• Subscriber TV decoder

• Satellite TV decoders

• Digital VCR.

GENERAL DESCRIPTION

The TDA8703 is an 8-bit high-speed Analog-to-Digital
Converter (ADC) for video and other applications.
It converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 40 MHz.
All digital inputs and outputs are TTL compatible, although
a low-level AC clock input signal is allowed.

ORDERING INFORMATION

TYPE

NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8703 DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1
TDA8703T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

1996 Aug 26 3

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

QUICK REFERENCE DATA

Notes

1. Full-scale sinewave (f

i

= 4.4 MHz; f

CLK

; f

CLK

= 27 MHz).

2. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).

3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling

on the LOW-to-HIGH transition of the input clock signal.

b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling

on the HIGH-to-LOW transition of the input clock signal.

c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V

(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.

d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF

capacitor.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

analog supply voltage 4.5 5.0 5.5 V

V

CCD

digital supply voltage 4.5 5.0 5.5 V

V

CCO

output stages supply voltage 4.2 5.0 5.5 V

I

CCA

analog supply current − 28 36 mA

I

CCD

digital supply current − 19 25 mA

I

CCO

output stages supply current − 11 14 mA
ILE DC integral linearity error −−±1 LSB
DLE DC differential linearity error −−±1/2 LSB
AILE AC integral linearity error note1 −−±2 LSB
B −3 dB bandwidth note 2; f

CLK

= 40 MHz − 19.5 − MHz

f

CLK/fCLK

maximum conversion rate note 3 40 −−MHz
P

tot

total power dissipation − 290 415 mW

1996 Aug 26 4

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

4

89VI

V

RB

V

RT

19

181716

CLK

CLK

V

CCD

7

V

CCA

23

15

13

24 D2

D3

D4

D5

D6

1
2

12

D1
D0

D7

TTL OUTPUTS

CLOCK DRIVER

TDA8703
TDA8703T

analog

voltage input

clock inputs

overflow /
underflow

output

data outputs

LSB

MSB

14

ANALOG - TO - DIGITAL

CONVERTER

LATCHES

MGA015

20
DGND

3
AGND

analog ground digital ground

11

21 22

TC CE

STABILIZER

TTL OUTPUT

OVERFLOW / UNDERFLOW

LATCH

V

CCO

5DEC

1996 Aug 26 5

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

PINNING

SYMBOL PIN DESCRIPTION

D1 1 data output; bit 1
D0 2 data output; bit 0 (LSB)
AGND 3 analog ground
V

RB

4 reference voltage bottom (decoupling)

DEC 5 decoupling input (internal stabilization

loop decoupling)
n.c. 6 not connected
V

CCA

7 positive supply voltage for analog

circuits (+5 V)
VI 8 analog voltage input
V

RT

9 reference voltage top (decoupling)
n.c. 10 not connected
O/UF 11 overflow/underflow data output
D7 12 data output; bit7 (MSB)
D6 13 data output; bit6
D5 14 data output; bit5
D4 15 data output; bit4
CLK 16 clock input
CLK 17 complementary clock input
V

CCD

18 positive supply voltage for digital

circuits (+5 V)

V

CCO

19 positive supply voltage for output

stages (+5 V)
DGND 20 digital ground
TC 21 input for two's complement output (TTL

level input, active LOW)
CE 22 chip enable input (TTL level input,

active LOW)
D3 23 data output; bit 3
D2 24 data output; bit 2

Fig.2 Pin configuration.

handbook, halfpage

1
2
3
4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

TDA8703/

TDA8703T

MLB034

D1
D0

AGND

V

RB

DEC

n.c.

V

CCA

VI

V

RT

n.c.

O/UF

D7

D6

D5

D4

CLK

V

CCD

V

CCO

DGND

D3

D2

CE
TC

CLK

1996 Aug 26 6

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. The circuit has two clock inputs CLK and

CLK. There are four modes of operation:

a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling

on the LOW-to-HIGH transition of the input clock signal.

b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling

on the HIGH-to-LOW transition of the input clock signal.

c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V

(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.

d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF

capacitor.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL RESISTANCE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

analog supply voltage −0.3 +7.0 V

V

CCD

digital supply voltage −0.3 +7.0 V

V

CCO

output stages supply voltage −0.3 +7.0 V

V

CCA

− V

CCD

supply voltage differences −1.0 +1.0 V

V

CCO

− V

CCD

supply voltage differences −1.0 +1.0 V

V

CCA

− V

CCO

supply voltage differences −1.0 +1.0 V

V

VI

input voltage range referenced to AGND −0.3 +7.0 V

V

CLK/VCLK

AC input voltage for switching
(peak-to-peak value)

note 1; referenced to DGND − 2.0 V

I

O

output current − +10 mA

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature 0 +70 °C

T

j

junction temperature − +125 °C

SYMBOL PARAMETER VALUE UNIT

R

th j-a

from junction to ambient in free air

SOT101-1 55 K/W
SOT137-1 75 K/W

1996 Aug 26 7

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

CHARACTERISTICS

V

CCA=V7−V3

= 4.5 V to 5.5 V; V

CCD=V18

− V20= 4.5 V to 5.5 V; V

CCO=V19

− V20= 4.5 V to 5.5 V; AGND and

DGND shorted together; V

CCA

− V

CCD

= −0.5 V to +0.5 V; V

CCO

− V

CCD

= −0.5 V to +0.5 V;

V

CCA

− V

CCD

= −0.5 V to +0.5 V; T

amb

=0°C to +70 °C; unless otherwise specified (typical values measured at

V

CCA=VCCD=VCCO

= 5 V and T

amb

=25°C).

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

CCA

analog supply voltage 4.5 5.0 5.5 V

V

CCD

digital supply voltage 4.5 5.0 5.5 V

V

CCO

output stages supply voltage 4.2 5.0 5.5 V

I

CCA

analog supply current − 28 36 mA

I

CCD

digital supply current − 19 25 mA

I

CCO

output stage supply current all outputs LOW − 11 14 mA

Inputs

C

LOCK INPUT CLK AND CLK (note 1; REFERENCED TO DGND)

V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current V

CLK/VCLK

= 0.4 V −400 −−µA

I

IH

HIGH level input current V

CLK/VCLK

= 0.4 V −−100 µA

V

CLK/VCLK=VCCD

−−300 µA

Z

i

input impedance f

CLK/fCLK

=10MHz − 4 − kΩ

C

i

input capacitance f

CLK/fCLK

=10MHz − 4.5 − pF

V

CLK

− V

CLK

AC input voltage for switching
(peak-to-peak value)

note 1; DC level = 1.5 V 0.5 − 2.0 V

TC AND CE (REFERENCED TO DGND)
V

IL

LOW level input voltage 0 − 0.8 V

V

IH

HIGH level input voltage 2.0 − V

CCD

V

I

IL

LOW level input current VIL= 0.4 V −400 −−µA

I

IH

HIGH level input current VIH= 2.7 V −−20 µA
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
V

VI(B)

input voltage (bottom) 1.33 1.41 1.48 V
V

VI(0)

input voltage output code = 0 1.455 1.55 1.635 V
V

OS(B)

offset voltage (bottom) V

VI(0)

− V

VI(B)

0.125 − 0.155 V

V

VI(T)

input voltage (top) 3.2 3.36 3.5 V
V

VI(255)

input voltage output code = 255 3.115 3.26 3.385 V
V

OS(T)

offset voltage (top) V

VI(T)

− V

VI(255)

0.085 − 0.115 V

V

VI(p-p)

input voltage amplitude (peak-to-peak value) 1.66 1.71 1.75 V
I

IL

LOW level input current VVI= 1.4 V − 0 −µA
I

IH

HIGH level input current VVI= 3.6 V 60 120 180 µA
Z

i

input impedance fi= 1 MHz − 10 − kΩ
C

i

input capacitance fi= 1 MHz − 14 − pF

1996 Aug 26 8

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

Reference resistance

R

ref

reference resistance VRTto V

RB

− 220 −Ω

Outputs

D

IGITAL OUTPUTS (D7 - D0) (REFERENCED TO DGND)

V

OL

LOW level output voltage IO= 1 mA 0 − 0.4 V
V

OH

HIGH level output voltage IO= −0.4 mA 2.7 − V

CCD

V

I

OZ

output current in 3-state mode 0.4 V < VO< V

CCD

−20 − +20 µA
Switching characteristics (note 2; see Fig.3)
f

CLK/fCLK

maximum clock frequency 40 −−MHz

Analog signal processing (f

CLK

= 40 MHz)

B −3 dB bandwidth note 3 − 19.5 − MHz
G

d

differential gain note 4 − 0.6 − %

φ

d

differential phase note 4 − 0.8 − deg

f

1

fundamental harmonics (full-scale) fi= 4.43 MHz −−0dB

f

all

harmonics (full-scale), all components fi= 4.43 MHz −−55 − dB
SVRR1 supply voltage ripple rejection note 5 −−28 −25 dB
SVRR2 supply voltage ripple rejection note 5 − 1 2.5 %/V

Transfer function

ILE DC integral linearity error −−±1 LSB
DLE DC differential linearity error −−±1/2 LSB
AILE AC integral linearity error note 6 −−±2 LSB
EB effective bits f

i

= 4.43 MHz − 7.1 − bits

Timing (note 7; see Figs 3 to 6; f

CLK

= 40 MHz)

t

dS

sampling delay −−2ns
t

HD

output hold time 6 −−ns
t

dLH

output delay time LOW-to-HIGH transition − 810ns
t

dHL

output delay time HIGH-to-LOW transition − 16 20 ns
t

dZH

3-state output delay times enable-to-HIGH − 19 25 ns
t

dZL

3-state output delay times enable-to-LOW − 16 20 ns
t

dHZ

3-state output delay times disable-to-HIGH − 14 20 ns
t

dLZ

3-state output delay times disable-to-LOW − 912ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1996 Aug 26 9

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

Notes

1. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling

on the LOW-to-HIGH transition of the input clock signal.

b) TTL (mode 2); CLK decoupled to DGND by a capacitor.CLK input is TTL threshold voltage of 1.5 V and sampling

on the HIGH-to-LOW transition of the input clock signal.

c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V

(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.

d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF

capacitor.

2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 2 ns.

3. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the input).

4. Low frequency ramp signal (V

VI(p-p)

= 1.8 V and fi= 15 kHz) combined with a sinewave input voltage (V

VI(p-p)

= 0.5 V,

fi= 4.43 MHz) at the input.

5. Supply voltage ripple rejection:
a) SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V:

SVRR1 = 20 log (∆V

VI(127)

/ ∆V

CCA

)

b) SVRR2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V:

SVR2 = {∆(V

VI(0)

− V

VI(255)

)/(V

VI(0)

− V

VI(255)

)} ÷∆V

CCA

.

6. Full-scale sinewave (fi= 4.4 MHz; f

CLK

; f

CLK

= 27 MHz).

7. Output data acquisition:
a) Output data is available after the maximum delay of t

dHL

and t

dLH

.

1996 Aug 26 10

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

Table 1 Output coding and input voltage (referenced to AGND; typical values)

Table 2 Mode selection

Note

1. X = don’t care.

BINARY OUTPUT BITS TWO'S COMPLEMENT OUTPUT BITS

STEP V

VI(p-p)

O/UF D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Underflow <1.55 1 0 000000010000000
0 1.55 0 0 000000010000000
1 − 0 0000000110000001

. . . ................

. . . ................

254 . 0 1111111001111110
255 3.26 0 1 111111101111111
Overflow >3.26 1 1 111111101111111

TC CE D7-D0 O/UF

X

(1)

1 high impedance high impedance
0 0 active; two’s complement active
1 0 active; binary active

Fig.3 Timing diagram.

handbook, full pagewidth

t

dHL

2.4 V

0.4 V

dS

t

HD

t

t

dLH

sample N + 1

1.3 V data N + 1data N – 1 data N

sample N + 2

sample N

1.3 V

CLK

VI

D0 - D7

MEA105

1996 Aug 26 11

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

Fig.4 3-state delay timing diagram.

handbook, full pagewidth

MLB035 - 1

2.4 V

0.4 V

reference
level
(1.4 V)

t

dHZ

t

dLZ

t

dZH

t

dZL

data

outputs

CE

input

Fig.5 Load circuit for timing measurement; data

outputs (CE = LOW).

handbook, halfpage

MGD691

D0 to D7

IN916

or

IN3064

2 kΩ

DGND

V

CCO

15 pF

Fig.6 Load circuit for timing measurement;

3-state outputs (CE: fi= 1 MHz; VVI= 3 V);
see Table 3.

handbook, halfpage

MBB955

D0 to D7

C5

kΩ

S1

2 kΩ

V

CCO

S2

DGND

IN916

or

IN3064

1996 Aug 26 12

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

Table 3 Mode selection

TIMING MEASUREMENT SWITCH S1 SWITCH S2 CAPACITOR

t

dZH

open closed 15 pF

t

dZL

closed open 15 pF

t

dHZ

closed closed 5 pF

t

dLZ

closed closed 5 pF

INTERNAL PIN CONFIGURATIONS

Fig.7 TTL data and overflow/underflow outputs.

handbook, halfpage

MGD692

DGND

D7 to D0

O/U

V

CCO

Fig.8 Analog inputs.

handbook, halfpage

MLB037

AGND

V

CCA

(x 90)

V

I

Fig.9 CE (3-state) input.

handbook, halfpage

MGD693

DGND

V

CCO

CE

Fig.10 TC (two’s complement) input.

handbook, halfpage

MLB039

DGND

V

CCD

TC

1996 Aug 26 13

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

Fig.11 VRB, VRT and DEC.

handbook, full pagewidth

V

RB

V

RT

V

CCA

DEC

AGND

MCD188

Fig.12 CLK and CLK inputs.

handbook, full pagewidth

30 kΩ 30 kΩ

V

V

CCD

CLK

DGND

MCD189 - 1

ref

1996 Aug 26 14

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

APPLICATION INFORMATION

Additional application information will be supplied upon request (please quote number FTV/8901).

Fig.13 Application diagram.

handbook, full pagewidth

MGA014 - 1

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

TDA8703
TDA8703T

D0

D1 D2

D3

D4

D5

D6

DGND

CLK

AGND

DEC

VI

O / UF

D7

n.c.

CLK

CE

V

RB

V

RT

V

CCA

V

CCD

n.c.

V

CCO

TC

DGND

AGND

100 pF

47 pF

4.7 µF 22 nF

22 nF

22 nF

5 V

22 Ω

(1)

4.7 µF

CLK should be decoupled to the DGND with a 100 nF capacitor, if a TTL signal is used on CLK (see Chapter “Characteristics”, note 1).
CLK and CLK can be used in a differential mode (see Chapter “Characteristics”, note 1).
VRB and VRT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
If it is required to use the TDA8703 in a parallel system configuration, the references (VRB and VRT) of each TDA8703 can be connected together.

Code 0 will be identical and code 255 will remain in the 1 LSB variation for each TDA8703.
Analog and digital supplies should be separated and decoupled.
Pins 6 and 10 should be connected to AGND in order to prevent noise influence.
(1) It is recommended to decouple V

CCO

through a 22 Ω resistor especially when the output data of the TDA8703 interfaces with a capacitive CMOS

load device.

1996 Aug 26 15

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

PACKAGE OUTLINES

UNIT

A

max.

1 2

b

1

cD E e M

H

L

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

SOT101-1

92-11-17
95-01-23

A

min.

A

max.

b

w

M

E

e

1

1.7

1.3

0.53

0.38

0.32

0.23

32.0

31.4

14.1

13.7

3.9

3.4

0.252.54 15.24

15.80

15.24

17.15

15.90

2.25.1 0.51 4.0

0.066

0.051

0.021

0.015

0.013

0.009

1.26

1.24

0.56

0.54

0.15

0.13

0.010.10 0.60

0.62

0.60

0.68

0.63

0.0870.20 0.020 0.16

051G02 MO-015AD

M

H

c

(e )

1

M

E

A

L

seating plane

A

1

w M

b

1

e

D

A

2

Z

24

1

13

12

b

E

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

Z

max.

(1)

(1)(1)

DIP24: plastic dual in-line package; 24 leads (600 mil)

SOT101-1

1996 Aug 26 16

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

UNIT

A

max.

A1A2A3b

p

cD

(1)E(1) (1)

eHELLpQ

Z

ywv θ

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

2.65

0.30

0.10

2.45

2.25

0.49

0.36

0.32

0.23

15.6

15.2

7.6

7.4

1.27

10.65

10.00

1.1

1.0

0.9

0.4

8
0

o
o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

1.1

0.4

SOT137-1

X

12

24

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

c

L

v M

A

13

(A )

3

A

y

0.25

075E05 MS-013AD

pin 1 index

0.10

0.012

0.004

0.096

0.089

0.019

0.014

0.013

0.009

0.61

0.60

0.30

0.29

0.050

1.4

0.055

0.42

0.39

0.043

0.039

0.035

0.016

0.01

0.25

0.01

0.004

0.043

0.016

0.01

92-11-17

95-01-24

e

1

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

1996 Aug 26 17

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

DIP

S

OLDERING BY DIPPING OR BY WA VE

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.
Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

W

AVE SOLDERING

Wave soldering techniques can be used for all SO
packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1996 Aug 26 18

Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.