
Philips Semiconductors Product specification
Class-H high-output voltage level line
driver
PINNING
SYMBOL PIN DESCRIPTION
V
CCL
INL 2 input voltage left channel
SVRL 3 SVRR left channel
INML 4 inverting input left channel
INMR 5 inverting input right channel
SVRR 6 SVRR right channel
INR 7 input voltage right channel
V
CCR
CR+ 9 lift capacitor (+) right channel
CR− 10 lift capacitor (−) right channel
RGND 11 ground right channel
OUTR 12 output voltage right channel
OUTL 13 output voltage left channel
LGND 14 ground left channel
CL− 15 lift capacitor (−) left channel
CL+ 16 lift capacitor (+) left channel
1 supply voltage left channel
8 supply voltage right channel
handbook, halfpage
V
1
CCL
INL
2
3
SVRL
4
INML
INMR
SVRR
INR
V
CCR
TDA8576T
5
6
7
8
MGE670
Fig.2 Pin configuration.
TDA8576T
16
CL+
15
CL−
14
LGND
13
OUTL
12
OUTR
11
RGND
10
CR−
9
CR+
FUNCTIONAL DESCRIPTION
Lift amplifier
The lift amplifier, referred to as LIFT AMP. in Fig.1, is used
as a non-inverting amplifier with a voltage gain of 6 dB set
by an internal feedback network. If the output voltage of
the signal amplifier is low, the external lift capacitor is
recharged by the lift amplifier. As soon as the output
voltage of the signal amplifier increases above 0.87 × V
CC
the lift amplifier switches the voltage of the lift capacitor in
series with the supply voltage V
The voltage at the
CC.
positive side of the lift capacitor is referred to as lifted
supply voltage.
Signal amplifier
The signal amplifier, referred to as SIGNAL AMP. in Fig.1,
is used as a non-inverting amplifier. The voltage gain G
is
v
set by the feedback resistors according to the formula:
R
G
v
2
1
+=
------ R
1
and should be set to 6 dB. The LIFT AMP. and SIGNAL
AMP. must have equal voltage gain Gv.
The rail-to-rail output stage of the signal amplifier uses the
lifted supply voltage to increase the output voltage swing.
The DC output level is set to ≈0.87 × V
. The maximum
CC
peak-to-peak output voltage of the signal amplifier is
calculated with the formula:
V
op p–()max()
2 0.87V
CC
0.4–()×≈
Buffers
The buffers prevent loading of the internal voltage divider
network made by a series connection of resistors. For a
good supply voltage ripple rejection this internal voltage
divider network has to be decoupled by an external
capacitor.
Reference
This circuit supplies all currents needed in the device.
1998 Oct 16 4

Philips Semiconductors Product specification
Class-H high-output voltage level line
TDA8576T
driver
DC CHARACTERISTICS
VCC=9V; RL=10kΩ; T
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CC
I
CC
V
O
supply voltage Vi=0V 6912V
supply current − 14 20 mA
DC output voltage note 1 − 7.8 − V
Note
1. The DC output voltage with respect to ground is ≈0.87 ×VCC.
AC CHARACTERISTICS
V
=9V; RL=10kΩ; f = 1 kHz; T
CC
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
G
v
∆G
channel unbalance −−0.5 dB
v
α
cs
f
Ir
f
hr
Z
input impedance 14 20 28 kΩ
i
Z
output impedance −−10 Ω
o
V
o(max)(rms)
voltage gain 567dB
channel separation Rs= 600 Ω; V
low frequency roll-off −1 dB; note 2 −−5Hz
high frequency roll-off −1dB 20 −−kHz
maximum output voltage
(RMS value)
V
no
noise input voltage unweighted; note 3 − 79µV
THD + N total harmonic distortion plus
noise
SVRR supply voltage ripple
rejection
=25°C; in accordance with application diagram (see Fig.3).
amb
=25°C; in accordance with application diagram (see Fig.3); note 1.
amb
= 1 V; note 1 80 90 − dB
o(rms)
THD+N=0.1% 5.0 5.3 − V
A-weighted; note 4 − 5 −µV
f = 1 kHz; V
=3V
O
; note 5 − 0.005 0.01 %
rms
f = 17 Hz to 20 kHz; note 6 − 0.01 − %
note 7 40 65 − dB
f = 20 Hz to 20 kHz; note 8 − 55 − dB
Notes
1. The channel separation is determined by the parasitic capacitance between the inverting input left channel (pin 4)
and the inverting input right channel (pin 5). The PCB layout has a major contribution to the parasitic capacitance.
To obtain best results the PCB tracks to pin 4 and pin 5 should be separated as much as possible.
2. The frequency response is externally fixed by the input coupling capacitors.
3. Noise output voltage is measured in a bandwidth of 20 Hz to 20 kHz with a source resistor R
= 600 Ω.
s
4. Noise output voltage is measured in a bandwidth of 20 Hz to 20 kHz with an A-weighted filter with a source resistor
Rs= 600 Ω.
5. Distortion is measured at a frequency of 1 kHz using an A-weighted filter.
6. Distortion is measured at an output voltage of 3.0 V (RMS) at frequencies between 17 Hz and 20 kHz.
7. Ripple rejection is measured at the output, using a source resistor Rs= 600 Ω and a ripple amplitude of
100 mV (RMS) at a frequency of 1 kHz.
8. Ripple rejection is measured at the output, using a source resistor Rs= 600 Ω and a ripple amplitude of
100 mV (RMS) at frequencies between 20 Hz and 20 kHz.
1998 Oct 16 6

Philips Semiconductors Product specification
Class-H high-output voltage level line
driver
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
Reflow soldering
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
TDA8576T
Wave soldering
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1998 Oct 16 12

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© Philips Electronics N.V. 1998 SCA60
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Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 545102/25/03/pp16 Date of release: 1998 Oct 16 Document order number: 9397 750 04394