Datasheet TDA8362-N5, TDA8362-N4, TDA8362-N3, TDA8361-N5, TDA8361-N4 Datasheet (Philips)

DATA SH EET

Objective specification
File under Integrated Circuits, IC02

March 1994

INTEGRATED CIRCUITS

Philips Semiconductors

TDA8360; TDA8361; TDA8362

Integrated PAL and PAL/NTSC TV
processors

March 1994 2

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

FEATURES
Available in TDA8360, TDA8361

and TDA8362

• Vision IF amplifier with high
sensitivity and good differential
gain and phase

• Multistandard FM sound
demodulator (4.5 MHz to 6.5 MHz)

• Integrated chrominance trap and
bandpass filters (automatically
calibrated)

• Integrated luminance delay line

• RGB control circuit with linear RGB

inputs and fast blanking

• Horizontal synchronization with two
control loops and alignment-free
horizontal oscillator without
external components

• Vertical count-down circuit
(50/60 Hz) and vertical preamplifier

• Low dissipation (700 mW)

• Small amount of peripheral

components compared with
competition ICs

• Only one adjustment (vision IF
demodulator)

• The supply voltage for the ICs is
8 V. They are mounted in a shrink
DIL envelope with 52 pins and are
pin compatible.

Additional features

TDA8360

• Alignment-free PAL colour decoder
for all PAL standards, including
PAL-N and PAL-M.

TDA8361

• PAL/NTSC colour decoder with
automatic search system

• Source selection for external
audio/video (A/V) inputs (separate
Y/C signals can also be applied).

TDA8362

• Multistandard vision IF circuit
(positive and negative modulation)

• PAL/NTSC colour decoder with
automatic search system

• Source selection for external
A/V inputs (separate Y/C signals
can also be applied)

• Easy interfacing with the TDA8395
(SECAM decoder) for
multistandard applications.

GENERAL DESCRIPTION

The TDA8360, TDA8361 and
TDA8362 are single-chip TV
processors which contain nearly all
small signal functions that are
required for a colour television
receiver. For a complete receiver the
following circuits need to be added:
a base-band delay line (TDA4661),
a tuner and output stages for audio,
video and horizontal and vertical
deflection.

Because of the different functional
contents of the ICs the set maker can
make the optimum choice depending
on the requirements for the receiver.

The TDA8360 is intended for simple
PAL receivers (all PAL standards,
including PAL-N and PAL-M are
possible).

The TDA8361 contains a PAL/NTSC
decoder and has an A/V switch.

For real multistandard applications
the TDA8362 is available. In addition
to the extra functions which are
available in the TDA8361, the
TDA8362 can handle signals with
positive modulation and it supplies
the signals which are required for the
SECAM decoder TDA8395.

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE

TDA8360 52 shrink DIL plastic SOT247AG
TDA8361 52 shrink DIL plastic SOT247AG
TDA8362 52 shrink DIL plastic SOT247AG

March 1994 3

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

P

supply voltage 7.2 8.0 8.8 V

I

P

supply current − 80 − mA

Input voltages

V

45,46(rms)

video IF amplifier sensitivity (RMS value) − 70 100 µV

V

5(rms)

sound IF amplifier sensitivity (RMS value) − 1 − mV

V

6(rms)

external audio input (RMS value) TDA8361, TDA8362 − 350 − mV

V

15(p-p)

external CVBS input (peak-to-peak value) TDA8361, TDA8362 − 1 − V

V

22,23,24(p−p)

RGB inputs (peak-to-peak value) − 0.7 − V

Output signals

V

O(p-p)

demodulated CVBS output
(peak-to-peak value)

− 2.4 − V

I

47

tuner AGC control current 0 − 5mA

V

44

AFC output voltage swing − 6 − V

V

50(rms)

audio output voltage (RMS value) − 700 − mV

V

18,19,20(p-p)

RGB output signal amplitudes
(peak-to-peak value)

− 4 − V

I

37

horizontal output current 10 −−mA

I

43

vertical output current 1 −−mA

Control voltages

V

control

control voltages for Volume, Contrast,
Saturation, Brightness, Hue and Peaking

0 − 5V

March 1994 4

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

MLA621 - 1

LUMINANCE

MATRIX

PWL

OUTPUT

STAGES

CLAMP

SWITCH

CLAMPS

SET

DEMODULATOR

PHASE

DETECTOR

MATRIX

PAL

IDENTIFICATION

COLOUR

KILLERS

XTAL

OSCILLATOR

CHROMINANCE

BANDPASS

Y DELAY

PEAKING

ACC

AMPLIFIER

TUNING

PHASE 2

TRAP AND

BYPASS

POWER

RESET

H AND V

SEPARATION

LINE

OSCILLATOR

PHASE 1

NOISE

DETECTOR

TUNING

VERTICAL

DIVIDER

VERTICAL

OUTPUT

PREAMPLIFIER

MUTE

SUPPLY

AFC AND

SAMPLE-

AND-HOLD

AGC

VOLUME

TEST

VIDEO

AMPLIFIER

DEMODULATOR

IF

AMPLIFIER

181920

17

28

29

222324

30

31

13 14 25

26

21

39 38 37 34 3543

41 42 40

4

47 48

44

45

46

49

2

3

7

50

51

5

11

910 52

12

TDA8360

33

DET

to

TDA4661

from

TDA4661

RIN

GIN

BIN

BOUT

GOUT

ROUT

CON

SAT

RGBIN

BRIPEAKIN

DEC

FT

GND2 GND1

V

P

PLLLIMITER

8

DEC

DIG

CVBS

INT

IFDEM1

IFDEM2

IFIN1

IFIN2

TUNE

ADJ

IDENT

AGCOUT

DEC

AGC

AFCOUT

VOUT

VFB

VRAMP

PH1LF

PH2LF

FBI/SCO

HOUT

XTAL1 XTAL2

AUDEEM

DEC

BG

SOIF

R-Y output

B-Y output

B-Y input

R-Y input

DEC

DEM

1

AUOUT

COINCIDENCE

DETECTOR

IFOUT

36

VSTART

flyback sandcastle

VIDEO

IDENTIFICATION

volume

control

Fig.1 Block diagram for TDA8360.

March 1994 5

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

MLA622 - 1

LUMINANCE

MATRIX

PWL

OUTPUT

STAGES

CLAMP

SWITCH

CLAMPS

SET

DEMODULATOR

PHASE

DETECTOR

MATRIX

SYSTEM

MANAGER

COLOUR

KILLERS

XTAL

OSCILLATOR

CHROMINANCE

BANDPASS

Y DELAY

PEAKING

ACC

AMPLIFIER

TUNING

PHASE 2

TRAP AND

BYPASS

POWER

RESET

H AND V

SEPARATION

LINE

OSCILLATOR

PHASE 1

NOISE

DETECTOR

TUNING

VERTICAL

DIVIDER

VERTICAL

OUTPUT

PREAMPLIFIER

MUTE

SUPPLY

AFC AND

SAMPLE-

AND-HOLD

AGC

VOLUME

TEST

VIDEO

AMPLIFIER

DEMODULATOR

IF

AMPLIFIER

181920

17

28

29

222324

30

31

13 16 25

26

21

36 39 38 37 34 3543

41 42 40

4

47 48

44

45

46

49

2

3

7

50

51

5

11

910 52

12

TDA8361

33

DET

to

TDA4661

from

TDA4661

RIN

GIN

BIN

BOUT

GOUT

ROUT

CON

SAT

RGBIN

BRI

PEAKIN

DEC

FT

GND2 GND1

V

P

PLLLIMITER

8

DEC

DIG

CVBS

INT

IFDEM1

IFDEM2

IFIN1

IFIN2

TUNE

ADJ

IDENT

AGCOUT

DEC

AGC

AFCOUT

VOUT

VFB

VRAMP

PH1LF

VSTART

PH2LF

FBI/SCO

HOUT

XTAL1 XTAL2

AUDEEM

DEC

BG

SOIF

R-Y output

B-Y output

B-Y input

R-Y input

DEC

DEM

1

AUOUT

COINCIDENCE

DETECTOR

IFOUT

HUE

CONTROL

HUE
27

CHROMINANCE

SWITCH

LUMINANCE

SWITCH

15

CVBS

EXT

CHROMA

EXTAU

6

14

VIDEO

IDENTIFICATION

volume

control

flayback

sandcastle

Fig.2 Block diagram for TDA8361.

March 1994 6

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Fig.3 Block diagram for TDA8362.

MBC214 - 1

LUMINANCE

MATRIX

PWL

OUTPUT

STAGES

CLAMP

SWITCH

CLAMPS

SET

DEMODULATOR

PHASE

DETECTOR

HUE

CONTROL

MATRIX

COLOUR

KILLERS

SYSTEM

MANAGER

XTAL

OSCILLATOR

CHROMINANCE

BANDPASS

Y DELAY

PEAKING

ACC

AMPLIFIER

COINCIDENCE

DETECTOR

TUNING

PHASE 2

CHROMINANCE

SWITCH

LUMINANCE

SWITCH

NOISE

DETECTOR

H AND V

SEPARATION

LINE

OSCILLATOR

PHASE 1

TRAP AND

BYPASS

TUNING

POWER

RESET

VERTICAL

DIVIDER

VERTICAL

OUTPUT

PLL

TEST

PREAMPLIFIER

MUTE

VIDEO

AMPLIFIER

AFC AND

SAMPLE-

AND-HOLD

AGC

LIMITER

SUPPLY

SWITCH

VOLUME

VIDEO

IDENTIFICATION

DEMODULATOR

IF

AMPLIFIER

181920

17

28

29

222324

30

31

16 13 15 14 2526 21

36 39 38 37 34 35 32 2743

41 42 40

4

50

47 48 44

45

46

49

2

3

7

1

6

51

5

8

11

910 52

12

TDA8362

33

DET

to

TDA4661

from

TDA4661

RIN

GIN

BIN

BOUT

GOUT

ROUT

CON

SAT

RGBIN

BRIPEAKINCVBS

EXT

CHROMA

DEC

FT

GND2 GND1

V

P

DEC

DIG

CVBS

INT

IFDEM1

IFDEM2

IFOUT

IFIN1

IFIN2

TUNE

ADJ

IDENT

AUOUT

AGCOUT

DEC

AGC

AFCOUT

VOUT

VFB

VRAMP

PH1LF

VSTART

PH2LF

FBI/SCO

HOUT

XTAL1 XTAL2

XTALOUT

HUE

AUDEEM

EXTAU

DEC

BG

SOIF

R-Y output

B-Y output

B-Y input

R-Y input

DEC

DEM

flyback

sandcastle

volume

control

March 1994 7

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

PINNING (TDA8362)

Fig.4 Pin configuration for

TDA8362.

1
2
3
4
5
6
7
8

9
10
11
12

13

40
39
38

37
36
35

34
33
32
31

30
29
28
27

14
15
16
17
18
19
20

22

23
24
25
26

21

42
41

43

44

45

46

47

48

49

50

51

52

MBC203

TDA8362

AUDEEM

IFDEM1
IFDEM2

IDENT

SOIF

EXTAU

IFOUT

DEC

DIG

GND1

V

P

GND2

CVBS

EXT

CHROMA

BRI

BOUT

GOUT
ROUT

RGBIN

RIN

GIN
BIN

CON

SAT

DEC

FT

CVBS

INT

PEAKIN

DEC

BG

DEC

DEM

AUOUT
TUNE

ADJ

DEC

AGC
AGCOUT
IFIN2

IFIN1
AFCOUT

VOUT
VRAMP
VFB
PH1LF
PH2LF
FBI/SCO
HOUT
VSTART
XTAL2
XTAL1
DET
XTALOUT
BYO

RYO
RYI
BYI
HUE

SYMBOL PIN DESCRIPTION

AUDEEM 1 audio de-emphasis and ± modulation switch
IFDEM1 2 IF demodulator tuned circuit
IFDEM2 3 IF demodulator tuned circuit
IDENT 4 video identification output/

MUTE input
SOIF 5 sound IF input and volume control
EXTAU 6 external audio input
IFOUT 7 IF video output
DEC

DIG

8 decoupling digital supply
GND1 9 ground 1
V

P

10 supply voltage (+8 V)
GND2 11 ground 2
DEC

FT

12 decoupling filter tuning
CVBS

INT

13 internal CVBS input
PEAKIN 14 peaking control input
CVBS

EXT

15 external CVBS input
CHROMA 16 chrominance and A/V switch input
BRI 17 brightness control input
BOUT 18 blue output
GOUT 19 green output
ROUT 20 red output
RGBIN 21 RGB insertion and blanking input
RIN 22 red input
GIN 23 green input
BIN 24 blue input
CON 25 contrast control input
SAT 26 saturation control input
HUE 27 hue control input (or chrominance output)
BYI 28 B−Y input signal
RYI 29 R−Y input signal
RYO 30 R−Y output signal
BYO 31 B−Y output signal
XTALOUT 32 4.43 MHz output for TDA8395
DET 33 loop filter burst phase detector
XTAL1 34 3.58 MHz crystal connection
XTAL2 35 4.43 MHz crystal connection
VSTART 36 supply/start horizontal oscillator
HOUT 37 horizontal output
FBI/SCO 38 flyback input/sandcastle output
PH2LF 39 phase 2 loop filter
PH1LF 40 phase 1 loop filter

March 1994 8

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

VFB 41 vertical feedback input
VRAMP 42 vertical ramp generator
VOUT 43 vertical output
AFCOUT 44 AFC output
IFIN1 45 IF input 1
IFIN2 46 IF input 2
AGCOUT 47 tuner AGC output
DEC

AGC

48 AGC decoupling capacitor

TUNE

ADJ

49 tuner take-over adjustment
AUOUT 50 audio output
DEC

DEM

51 decoupling sound demodulator
DEC

BG

52 decoupling bandgap supply

SYMBOL PIN DESCRIPTION

TDA8360

The TDA8360 has the following
differences to the pinning:

Pin 6: external audio input not
connected

Pin 15: external CVBS input not
connected

Pin 16: chrominance and A/V switch
input not connected

Pin 27: hue control input not
connected.

TDA8361

The TDA8361 has the following
differences to the pinning:

Pin 1: only audio de-emphasis
Pin 27: only hue control
Pin 32: 4.43 MHz output for TDA8395

is not connected.

FUNCTIONAL DESCRIPTION
Video IF amplifier

The IF amplifier contains
3 AC-coupled control stages with a
total gain control range of greater
than 60 dB. The sensitivity of the
circuit is comparable with that of
modern IF ICs.

The reference carrier for the video
demodulator is obtained by means of
passive regeneration of the picture
carrier. The external reference tuned
circuit is the only remaining
adjustment of the IC.

In the TDA8362 the polarity of the
demodulator can be switched so that
the circuit is suitable for both positive
and negative modulated signals.

The AFC circuit is driven with the
same reference signal as the video
demodulator. To ensure that the
video content does not disturb the
AFC operation a sample-and-hold
circuit is incorporated; the capacitor
for this function is internal. The AFC
output voltage is 6 V.

The AGC detector operates on levels,
top sync for negative modulated and
top white for positive modulated
signals.The AGC detector time
constant capacitor is connected
externally. This is mainly because of
the flexibility of the application.

The time constant of the AGC system
during positive modulation
(TDA8362) is slow, this is to avoid any
visible picture variations. This,
however, causes the system to react
very slowly to sudden changes in the
input signal amplitude.

To overcome this problem a speed-up
circuit has been included which
detects whether the AGC detector is
activated every frame period. If,
during a 3-frame period, no action is
detected the speed of the system is
increased. When the incoming signal
has no peak white information (e.g.
test lines in the vertical retrace period)
the gain would be video signal
dependent. To avoid this effect the
circuit also contains a black level
AGC detector which is activated when
the black level of the video signal
exceeds a certain level.

The TDA8361 and TDA8362 contain
a video identification circuit which is
independent of the synchronization
circuit. Therefore search tuning is
possible when the display section of
the receiver is used as a monitor. In
the TDA8360 this circuit is only used
for stable OSD at no signal input. In
the normal television mode the
identification output is connected to
the coincidence detector, this applies
to all three devices. The identification
output voltage is LOW when no
transmitter is identified. In this
condition the sound demodulator is
switched off (mute function). When a
transmitter is identified the output
voltage is HIGH. The voltage level is
dependent on the frequency of the
incoming chrominance signal.

March 1994 9

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Sound circuit

The sound bandpass and trap filters
have to be connected externally. The
filtered intercarrier signal is fed to a
limiter circuit and is demodulated by
means of a PLL demodulator. The
PLL circuit tunes itself automatically
to the incoming signal, consequently,
no adjustment is required.

The volume is DC controlled. The
composite audio output signal has an
amplitude of 700 mV RMS at a
volume control setting of −6 dB. The
de-emphasis capacitor has to be
connected externally. The
non-controlled audio signal can be
obtained from this pin via a buffer
stage. The amplitude of this signal is
350 mV RMS.

The TDA8361 and TDA8362 external
audio input signal must have an
amplitude of 350 mV RMS. The
audio/video switch is controlled via
the chrominance input pin.

Synchronization circuit

The sync separator is preceded by a
voltage controlled amplifier which
adjusts the sync pulse amplitude to a
fixed level. The sync pulses are then
fed to the slicing stage (separator)
which operates at 50% of the
amplitude.

The separated sync pulses are fed to
the first phase detector and to the
coincidence detector. The
coincidence detector is used for
transmitter identification and to detect
whether the line oscillator is
synchronized. When the circuit is not
synchronized the voltage on the
peaking control pin (pin 14) is LOW
so that this condition can be detected
externally. The first PLL has a very
high static steepness, this ensures
that the phase of the picture is
independent of the line frequency.
The line oscillator operates at twice
the line frequency.

The oscillator network is internal.
Because of the spread of internal
components an automatic adjustment
circuit has been added to the IC.
The circuit compares the oscillator
frequency with that of the crystal
oscillator in the colour decoder. This
results in a free-running frequency
which deviates less than 2% from the
typical value.

The circuit employs a second control
loop to generate the drive pulses for
the horizontal driver stage.

X-ray protection can be realised by
switching the pin of the second
control loop to the positive supply line.
The detection circuit must be
connected externally. When the X-ray
protection is active the horizontal
output voltage is switched to a high
level. When the voltage on this pin
returns to its normal level the
horizontal output is released again.

The IC contains a start-up circuit for
the horizontal oscillator. When this
feature is required a current of 6.5 mA
has to be supplied to pin 36. For an
application without start-up both
supply pins (10 and 36) must be
connected to the 8 V supply line.

The drive signal for the vertical ramp
generator is generated by means of a
divider circuit. The RC network for the
ramp generator is external.

Integrated video filters

The circuit contains a chrominance
bandpass and trap circuit. The filters
are realised by means of gyrator
circuits and are automatically tuned
by comparing the tuning frequency
with the crystal frequency of the
decoder.
In the TDA8361 and TDA8362 the
chrominance trap is active only when
the separate chrominance input pin is
connected to ground or to the positive
supply voltage and when a colour
signal is recognized.

When the pin is left open-circuit the
trap is switched off so that the circuit
can also be used for S-VHS
applications.

The luminance delay line and the
delay for the peaking circuit are also
realised by means of gyrator circuits.

Colour decoder

The colour decoder in the various ICs
contains an alignment-free crystal
oscillator, a colour killer circuit and
colour difference demodulators.
The 90° phase shift for the reference
signal is achieved internally. Because
the main differences of the 3 ICs are
found in the colour decoder the
various types will be discussed.

TDA8360

This IC contains only a PAL decoder.
Depending on the frequency of the
crystals which are connected to the IC
the decoder can demodulate all PAL
standards. Because the horizontal
oscillator is calibrated by using the
crystal frequency as a reference the

4.4 MHz crystal must be connected to
pin 35 and the 3.5 MHz crystal to
pin 34. When only one crystal is
connected to the IC the other crystal
pin must be connected to the positive
supply rail via a 47 kΩ resistor. For
applications with two 3.5 MHz
crystals both must be connected to
pin 34 and the switching between the
crystals must be made externally.
Switching of the crystals is only
allowed directly after the vertical
retrace. The circuit will indicate
whether a PAL signal has been
identified by the colour decoder via
the saturation control pin.

When two crystals are connected to
the IC the output voltage of the video
identification circuit indicates the
frequency of the incoming
chrominance signal.

March 1994 10

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

The conditions are:

• Signal identified at
f

osc

= 3.6 MHz; VO = 6 V

• Signal identified at
f

osc

= 4.4 MHz (or no colour);

VO = 8 V.

This information can be used to
switch the sound bandpass filter and
trap filter.

TDA8361

This IC contains an automatic
PAL/NTSC decoder. The conditions
for connecting the reference crystals
are the same as for the TDA8360.
The decoder can be forced to PAL
when the hue control pin is connected
to the positive supply voltage via a
5kΩ or 10 kΩ resistor
(approximately). The decoder cannot
be forced to the NTSC standard. It is
also possible to see if a colour signal
is recognized via the saturation pin.

TDA8362

In addition to the possibilities of the
TDA8361, the TDA8362 can
co-operate with the SECAM add-on
decoder TDA8395.
The communication between the two
ICs is achieved via pin 32. The
TDA8362 supplies the reference
signal (4.43 MHz) for the calibration
system of the TDA8395, identification
of the colour standard is via the same
connection. When a SECAM signal is
detected by the TDA8395 the IC will
draw a current of 150 µA. When
TDA8362 has not identified a colour
signal in this condition it will go into
the SECAM mode, that means it will
switch off the R−Y and B−Y outputs
and increase the voltage level on
pin 32.

This voltage will switch off the
colour-killer in the TDA8395 and
switch on the R−Y and B−Y outputs of
the TDA8395. Forcing the system to
the SECAM standard can be
achieved by loading pin 32 with a
current of 150 µA. Then the system
manager in the TDA8362 will not
search for PAL or NTSC signals.
Forcing to NTSC is not possible.
For PAL/SECAM applications the
input signal for the TDA8395 can be
obtained from pin 27 (hue control)
when this pin is connected to the
positive supply rail via the 5 kΩ or
10 kΩ resistor. An external source
selector is required by the
TDA8395/TDA8362 combination for
PAL/SECAM/NTSC applications.

RGB output circuit

The colour difference signals are
matrixed with the luminance signal to
obtain the RGB signals. Linear
amplifiers have been chosen for the
RGB inputs so that the circuit is
suitable for incoming signals from the
SCART connector. The contrast and
brightness controls operate on
internal and external signals.

The fast blanking pin has a second
detection level at 3.5 V.
When this level is exceeded the
RGB outputs are blanked so that
“On-Screen-Display” signals can be
applied to the outputs.
The output signal has an amplitude of
approximately 4 V, black-to-white,
with nominal input signals and
nominal control settings. The nominal
black level is 1.3 V.

March 1994 11

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

THERMAL RESISTANCE

CHARACTERISTICS

V

P

= 8 V; T

amb

= 25 °C; unless otherwise specified.

SYMBOL PARAMETER MIN. MAX. UNIT

V

P

supply voltage − 9.0 V

T

stg

storage temperature −25 +150 °C

T

amb

operating ambient temperature −25 +70 °C

T

sol

soldering temperature for 5 s − 260 °C

T

j

maximum junction temperature (operating) − 150 °C

SYMBOL PARAMETER THERMAL RESISTANCE

R

th j-a

from junction to ambient in free air 40 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

supply voltage (pin 10) 7.2 8.0 8.8 V

I

P

supply current (pin 10) − 80 − mA

I

HOSC

horizontal oscillator start current
(pin 36)

note 1 6.5 −−mA

P

tot

total power dissipation including start supply − 0.7 − W

IF circuit

V

ISION IF AMPLIFIER INPUTS (PINS 45 AND 46)

V

i(rms)

input sensitivity (RMS value) note 2

f

i

= 38.90 MHz − 70 100 µV

f

i

= 45.75 MHz − 70 100 µV

f

i

= 58.75 MHz − 70 100 µV

R

I

Input resistance (differential) note 3 − 2 − kΩ

C

I

Input capacitance (differential) note 3 − 3 − pF

G

cr

gain control range 64 −−dB

V

i(rms)

maximum input signal (RMS value) 100 −−mV

March 1994 12

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

VIDEO AMPLIFIER OUTPUT; NOTE 4(PIN 7)
V

7

negative modulation

zero signal output level note5 4.45 4.6 4.75 V
top sync level 1.9 2 2.1 V

V

7

positive modulation (TDA8362)

zero signal output level note5 1.85 2 2.15 V
white level 4.2 4.3 4.4 V

∆V

7

difference in amplitude between
negative and positive modulation

− 015%

V

7

detection level of black level for
positive modulation when no peak
white is available in the signal

− 3.1 − V

Z

O

video output impedance −−50 Ω

I

bias

internal bias current of NPN emitter
follower output transistor

1 −−mA

I

source

maximum source current −−5mA

B bandwidth of demodulated output

signal

−3dB 6 9 − MHz

G

diff

gain differential note 6 − 25%

Φ

diff

phase differential notes 6 and 7 − 1 5 deg

NL

vid

video non linearity note 8 −−5%

V

th

white spot threshold voltage level − 4.8 − V

V

ins

white spot insertion voltage level − 3.2 − V

N

clamp

noise inverter clamping voltage level − 1.4 − V

N

ins

noise inverter insertion level note 9 − 2.6 − V

δ

mod

intermodulation notes 7 and 10

blue V

o

= 0.92 or 1.1 MHz 60 66 − dB

yellow V

o

= 0.92 or 1.1 MHz 56 62 − dB

blue V

o

= 2.66 or 3.3 MHz 60 66 − dB

yellow V

o

= 2.66 or 3.3 MHz 60 66 − dB

S/N signal-to-noise ratio notes 7 and 11

V

i

= 10 mV 52 60 − dB

end of control range 52 61 − dB

V

7

residual carrier signal note 7 − 1 − mV

V

7

residual 2nd harmonic of carrier
signal

note 7 − 0.5 − mV

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 13

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

IF AND TUNER AGC; NOTE 12

Timing of IF-AGC (C48 = 2.2µF)

modulated video interference 30% AM for 1 to

100 mV; 0 to 200 Hz

−−10 %

t

inc

response time for an IF input signal
amplitude increase of 52 dB for
positive and negative modulation

− 2 − ms

t

dec

response time for an IF input signal
amplitude decrease of 52 dB

for negative modulation − 25 − ms
for positive modulation (TDA8362) − 100 − ms

I

leak

allowed leakage current of the AGC
capacitor

note 13

for negative modulation −−10 µA
for positive modulation −−200 nA

Tuner take-over adjustment (pin 49)

V

49(rms)

minimum starting level voltage for
tuner take-over (RMS value)

− 0.2 0.5 mV

V

49(rms)

maximum starting level voltage for
tuner take-over (RMS value)

100 150 − mV

V

cr

control voltage range 0.5 − 4.5 V

Tuner control output (pin 47)

V

47

maximum tuner AGC output voltage maximum gain −−V

P

+ 1 V

V

47(sat)

output saturation voltage minimum gain;

I47=2mA

−−300 mV

I

47

maximum tuner AGC output swing 5 −−mA

I

leak

leakage current RF AGC −−1µA

∆V

47

input signal variation for complete
tuner control

I

O(max)

= 1 mA 1 2 4 dB

AFC OUTPUT; NOTE 14 (PIN 44)
V

44

output voltage swing − 6 − V

f

sl

AFC slope − 33 − mV/kHz

f

os

AFC offset note 7 −−50 kHz

V

O

output voltage at centre frequency − 3.5 − V

Z

O

output impedance − 50 − kΩ
SWITCHING TO POSITIVE MODULATION (TDA8362); NOTE 15 (PIN 1)
V

1

minimum voltage on pin 1 to switch

the video demodulator and AGC to

positive modulation

−−V

P

−1V

I

I

input current −−1mA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 14

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

VIDEO IDENTIFICATION OUTPUT (PIN 4)
V

O

output voltage video not identified −−0.5 V
Z

O

output impedance − 25 − kΩ
V

O

output voltage video identified;

colour signal
available;
f

osc

= 3.5 MHz

− 6 − V

video identified;
colour signal
available/unavailable
;f

osc

= 4.4 MHz

− 8 − V

t

d

delay time of identification after

the AGC has stabilized on a new

transmitter

−−10 ms

I

4

maximum load current at pin 4 −−25 µA

Sound circuit

D

EMODULATOR INPUT; NOTE 16 (PIN 5)

V

5(rms)

input limiting for PLL catching range

(RMS value)

− 12mV

∆f catching range PLL note 17 4.2 − 6.8 MHz

R

I

DC input resistance note 3 100 −−kΩ
C

I

input capacitance note 3 − 15 − pF
AMR AM rejection V

I

= 50 mV RMS;

note 18

60 66 − dB

DE-EMPHASIS (PIN 1)
V

O(rms)

output signal amplitude (RMS value) note 17 − 350 − mV
R

O

output resistance − 15 − kΩ
V

1

DC output voltage − 3 − V
AUDIO ATTENUATOR OUTPUT (PIN 50)
V

50(rms)

controlled output signal amplitude

(RMS value)

−6 dB; note 17 500 700 900 mV

R

O

output resistance − 250 −Ω
V

50

DC output voltage − 3.3 − V
THD total harmonic distortion note 19 −−0.5 %
S/N

int

internal signal-to-noise ratio note 7 − 60 − dB
S/N

ext

external signal-to-noise ratio note 7 − 80 − dB
VOL

cr

control range see also Fig.5 − 80 − dB
OSS suppression of output signal when

mute is active

− 80 − dB

∆V

50

DC shift of the output when mute is

active

note 20 − 10 50 mV

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 15

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

EXTERNAL AUDIO INPUT (TDA8361, TDA8362); NOTE 21 (PIN 6)
V

6(rms)

input signal amplitude (RMS value) − 350 700 mV
R

I

input resistance − 25 − kΩ
∆G

V

voltage gain difference between input

and output

maximum volume − 12 − dB

α

cr

crosstalk between internal and

external audio signals

60 −−dB

CVBS/On-Screen Display and CD inputs

I

NTERNAL AND EXTERNAL CVBS INPUTS (PINS 13 AND 15)

V

13(p-p)

internal CVBS input voltage

(peak-to-peak value)

notes 3 and 22 − 2 2.8 V

I

13

internal CVBS input current − 4 −µA
V

15(p-p)

external CVBS input voltage;

TDA8361, TDA8362

(peak-to-peak value)

note 3 − 1 1.4 V

I

15

external CVBS input current;

TDA8361, TDA8362

− 4 −µA

ISS suppression of non-selected CVBS

input signal; TDA8361, TDA8362

note 23 50 −−dB

C

OMBINED CHROMINANCE AND SWITCH INPUT (TDA8361, TDA8362; PIN 16)

V

16(p-p)

chrominance input voltage

(peak-to-peak value)

notes 3 and 24 − 0.3 − V

V

16(p-p)

input signal amplitude before clipping

occurs (peak-to-peak value)

note 7 1 −−V

R

I

chrominance input resistance − 15 − kΩ
C

I

chrominance input capacitance note 3 −−5pF
V

16

DC input voltage to switch the

A/V switch to internal mode

−−0.5 V

V

16

DC input voltage to switch the

A/V switch to external mode

VP − 0.5 −−V

V

16

DC input voltage for chrominance

insertion

345V

SS

CVBS

suppression of non-selected

chrominance signal from CVBS input

notes 7 and 23 50 −−dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 16

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

RGB INPUTS FOR ON-SCREEN DISPLAY (PINS 22, 23 AND 24)
V

22,23,24(p-p)

input signal amplitude for an output

signal of 4V (black-to-white)

(peak-to-peak value)

note 25 − 0.7 0.8 V

V

22,23,24(p-p)

input signal amplitude before clipping

occurs (peak-to-peak value)

1 −−V

V

diff

difference of black level of internal

and external signals at the outputs

−−100 mV

I

22,23,24

input currents − 0.1 −µA
FAST BLANKING (PIN 21)
V

I

fast blanking input voltage no data insertion −−0.4 V
V

I

fast blanking input voltage data insertion 0.9 −−V
V

21(max)

maximum input pulse data insertion −−3V
t

d

delay of data insertion −−20 ns
I

21

input current − 0.2 − mA
SS

int

suppression of internal RGB signals

with data insertion at

f = 0 to 5 MHz

note 23 46 −−dB

SS

ext

suppression of external RGB signals

with data insertion at

f = 0 to 5 MHz

note 23 46 −−dB

V

I

input voltage to blank the RGB

outputs to facilitate

‘On-Screen-Display’ signals being

applied to these outputs

note 26 4 −−V

t

d

delay between the input pulse and

the blanking at the output

note 7 − 30 − ns

COLOUR DIFFERENCE INPUT SIGNALS (PINS 28 AND 29)
V

29(p-p)

input signal amplitude (R−Y)

(peak-to-peak value)

− 1.05 − V

V

28(p-p)

input signal amplitude (B−Y)

(peak-to-peak value)

− 1.35 − V

I

28,29

input current for both inputs − 0.1 1.0 µA

Chrominance filters

C

HROMINANCE TRAP CIRCUIT

f

trap

trap frequency − f

SC

− MHz
QF trap quality factor notes 7 and 27 − 2 −
SR colour subcarrier rejection 20 −−dB

C

HROMINANCE BANDPASS CIRCUIT

f

c

centre frequency − f

SC

− MHz
QBP bandpass quality factor note 7 − 3 −

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 17

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Delay line and peaking circuit

Y DELAY LINE
t

d

delay time note 7 − 480 − ns

B bandwidth of internal delay line note 7 8 −−MHz

PEAKING CONTROL; NOTE 28, SEE ALSO FIG.6 (PIN 14)

t

W

width of preshoot or overshoot at 50% of pulse;

note 7

− 160 − ns

S

cth

peaking signal compression
threshold

− 50 − IRE

I

14

input current when no video input
signal present

− 1 − mA

V

I

voltage level to switch off peaking − 7 − V

Horizontal and vertical synchronization circuits

S

YNC VIDEO INPUT (TDA8361, TDA8362; PINS 13 AND 15)

V

13

sync pulse amplitude referenced to pin 15;

note 3

50 300 − mV

SL slicing level note 29 − 50 − %

VERTICAL SYNC

t

W

width of the vertical sync pulse
without sync instability

note 30 22 −−µs

HORIZONTAL OSCILLATOR
f

fr

free running frequency note 44 − 15625 − Hz

∆f

fr

spread on free running frequency −−±2%

∆f

osc

/∆V

P

frequency variation with respect to
the supply voltage

VP = 8 V ±10%;
note 7

− 0.2 0.5 %

∆f

osc

/∆T frequency variation with temperature T

amb

= 25 °C ±50 °C;

note 7

− 1 − Hz/K

∆f

osc( max

) maximum frequency deviation at the

start of the horizontal output

−−75 %

FIRST CONTROL LOOP; NOTE 31 (FILTER CONNECTED TO PIN 40)
f

HR

holding range PLL −±0.9 ±1.2 kHz

f

CR

catching range PLL note 7 ±0.6 ±0.9 − kHz

S/N signal-to-noise ratio of the video input

signal at which the time constant is
switched

− 20 − dB

HYS hysteresis at the switching point − 3 − dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 18

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

SECOND CONTROL LOOP; NOTE 32 (CAPACITOR CONNECTED TO PIN 39)

∆ϕ

i

/∆ϕ

o

control sensitivity without RL on pin 39 − 150 −µs/µs

t

cr

control range from start of horizontal
output to flyback

11 12 −µs

t

shift

maximum horizontal shift range note 7 ±2 −−µs

∆ϕ

i

/∆ϕ

o

shift control sensitivity note 7 − 3 −µA/µs

V

39

voltage to switch on the X-ray
protection

6 −−V

I

I

input current during protection −−tbf µA
HORIZONTAL OUTPUT (PIN 37)
V

OL

LOW level output voltage IO = 10 mA −−0.3 V
I

O(max)

maximum allowed output current 10 −−mA
V

O(max)

maximum allowed output voltage −−V

P

V

δ

df

duty factor note 7 − 50 − %
FLYBACK INPUT/SANDCASTLE OUTPUT (PIN 38)
I

38

required input current during flyback

pulse

note 7 100 − 300 µA

V

O

output voltage during burst key 4.8 5.3 5.8 V
V

O

output voltage during blanking 1.8 2.0 2.2 V
V

Icl

clamped input voltage during flyback 2.6 3.0 3.4 V
t

W

burst key pulse width 3.3 3.5 3.7 µs
t

W

vertical blanking pulse width note 33 − 14 − lines
t

d

delay of start of burst key to start

of sync

5.2 5.4 5.6 µs

VERTICAL SECTION; NOTE 34
f

fr

free running frequency − 50/60 − Hz
f

lock

locking range 45 − 64.5 Hz

divider value not locked − 625/525 −

locking range (lines/frame) 488 − 722
V

ERTICAL RAMP GENERATOR (PIN 42)

I

42

input current during scan note 7 −−2µA
I

dis

discharge current during retrace − 0.3 − mA
V

saw(p-p)

sawtooth amplitude

(peak-to-peak value)

in 50 Hz mode − 1.5 1.8 V

t

d

delay from field-to-field −−1.6 µs

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 19

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

VERTICAL OUTPUT (PIN 43)
I

O

available output current note 7 1 −−mA
I

int

internal bias current of NPN emitter

follower

− 0.2 − mA

V

O(max)

maximum available output voltage 4 −−V
V

O(min)

minimum available output voltage −−0.3 V
VERTICAL FEEDBACK INPUT (PIN 41)
V

41

DC input voltage 2.0 2.5 3.0 V
V

41

AC input voltage − 1 − V
I

41

input current −−15 µA
∆t

p

internal pre-correction to sawtooth note 35 − 3 − %
∆T/∆V temperature dependency on

amplitude

∆T = 40 °C −−1%

V

GL

vertical guard switching level with

respect to the DC feedback level;

switching level LOW

−−−1.5 V

V

GH

vertical guard switching level with

respect to the DC feedback level;

switching level HIGH

−−+1.5 V

t

d

delay of scan start power on at 60 Hz − 140 − ms

Colour demodulation part

C

HROMINANCE AMPLIFIER

ACC

cr

ACC control range note 36 26 −−dB
∆V change in amplitude of the output

signals over the ACC range

−−2dB

THR

on

threshold colour killer ON −30 −−38 dB
HYS

off

hysteresis colour killer OFF note 7

strong input signal S/N ≥ 40 dB − +3 − dB
noisy input signal − +1 − dB

ACL CIRCUIT

chrominance burst ratio at which the

ACL starts to operate

2.3 − 2.7

REFERENCE PART

Phase-locked loop; note 37

f

CR

catching range 300 −−Hz
∆ϕ phase shift for a ±200 Hz deviation of

the oscillator frequency

note 7 −−2 deg

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 20

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Oscillator

TC

osc

temperature coefficient of f

osc

note 7 − 2.0 2.5 Hz/K

∆f

osc

f

osc

deviation with respect to V

P

note 7;
VP = 8 V ±10%

−−250 Hz

R

I

input resistance (pin 34) fi= 3.58 MHz; note 4 − 1.5 − kΩ
R

I

input resistance (pin 35) fi= 4.43 MHz; note 4 − 1 − kΩ
C

I

input capacitance (pins 34 and 35) note 4 −−10 pF
R required resistance to V

P

to force the

oscillator into one crystal mode

− 47 − kΩ

HUE CONTROL AND CHROMINANCE OUTPUT (TDA8361, TDA8362); NOTE 38 (PIN 27)
HUE

cr

hue control range see also Fig.7 ±45 ±60 − deg
∆HUE hue variation for ±10% V

P

note 7 − 0 5 deg

∆HUE/∆T hue variation with temperature T

amb

= 0 to +7 °C;

note 7

− 0 − deg

R value of resistor connected to V

P

to
switch the P AL decoder and to obtain
a chrominance input signal for the
TDA8395 (TDA8362)

4.7 10 12 kΩ

V

O(p-p)

chrominance output signal to the
TDA8395 (peak-to-peak value)

nominal output signal − 330 − mV

DEMODULAT ORS
V

30(p-p)

(R−Y) output signal amplitude
(peak-to-peak value)

note 39 − 0.525 − V

V

31(p-p)

(B−Y) output signal amplitude
(peak-to-peak value)

note 39 − 0.675 − V

G gain ratio of both demodulators

G(B−Y)/G(R−Y)

1.6 1.78 1.96

spread of signal amplitude ratio
PAL/NTSC

note 7 −1 − +1 dB

Z

O

output impedance (R−Y)/(B−Y)
output

− 250 −Ω

B bandwidth of demodulators −3 dB; note 40 − 650 − kHz
V

30,31(p-p)

residual carrier output voltage
(peak-to-peak value)

f = f

osc

(R−Y) output −−10 mV
(B−Y) output −−10 mV

V

30,31(p-p)

residual carrier output voltage
(peak-to-peak value)

f = 2f

osc

(R−Y) output −−10 mV
(B−Y) output −−10 mV

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 21

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

DEMODULATORS
V

30(p-p)

H/2 ripple at (R−Y) output
(peak-to-peak value)

only burst fed to
input

−−25 mV

∆V

O

/∆T change of output signal amplitude

with temperature

note 7 − 0.1 − %/K

∆V

O

/∆V

P

change of output signal amplitude
with supply voltage

note 7 −−±0.1 dB

ϕ

e

phase error in the demodulated
signals

−−5 deg

COLOUR DIFFERENCE MATRIXES IN CONTROL CIRCUIT
G−Y/−(R−Y) PAL/SECAM mode with

TDA8362/TDA8395

−(R−Y) and −(B−Y)
not affected

−−0.51
±10%

−

G−Y/−(B−Y) −−0.19

±25%

−

−(B−Y) NTSC mode; the CD matrix results in

the following signal (1.14/−10°)

nominal hue setting −1.12U

R

− 1.12V

R

−(R−Y) NTSC mode; the CD matrix results in
the following signal (1.14/100°)

nominal hue setting −0.20UR + 1.12V

R

G−Y NTSC mode; the CD matrix results in

the following signal (0.30/235°)

nominal hue setting −0.25VR− 0.17U

R

REFERENCE SIGNAL OUTPUT FOR TDA8395 (TDA8362; PIN 32)
f

ref

reference frequency note 41 − 4.43 − MHz

V

32(p-p)

output signal amplitude
(peak-to-peak value)

0.2 0.25 0.3 V

V

O

output voltage level PAL/NTSC identified − 1.5 − V

V

O

output voltage level no PAL/NTSC;

SECAM (by
TDA8395) identified

− 5 − V

I

32

required current to force
TDA8362/TDA8395 combination in
SECAM mode

150 −−µA

Control part

S

ATURATION CONTROL; NOTE 25 (PIN 26)

SAT

cr

saturation control range see also Fig.8 52 −−dB

∆SAT/∆V saturation level change V

P

= ±10%;note 7 − 0 − %

I

I

input current no colour identified − 1 − mA

V

ctr

control voltage to switch colour PLL
in the free-running mode

note 37 VP− 1 −−V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 22

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

CONTRAST CONTROL; NOTE 25 (PIN 25)
CON

cr

contrast control range see also Fig.9 − 20 − dB
tracking between the three channels

over a control range of 10 dB

−−0.7 dB

B

RIGHTNESS CONTROL (PIN 17)

BRI

cr

brightness control range see also Fig.10 −±1−V

RGB AMPLIFIERS (PINS 18, 19 AND 20)
V

18,19,20(p-p)

output signal amplitudes
(peak-to-peak value)

nominal luminance
input signal and
nominal contrast;
note 25

3.5 4.0 4.5 V

V

20(p-p)

output signal amplitudes for the RED
channel (peak-to-peak value)

nominal settings for
contrast and
saturation control
and no luminance
signal to the R−Y
signal (PAL)

3.8 4.2 4.6 V

V

18,19,20

blanking level at the RGB outputs 0.5 0.6 0.8 V

V

18,19,20

black level at the RGB outputs note 25 1.2 1.3 1.4 V

V

pwl

maximum peak white level note 42 − 6 − V

I

O

available output current 5 −−mA

Z

O

output impedance − 150 −Ω

I

source

current source of output stage 1.8 2.0 − mA
relative spread between the RGB

output signals

−−5%

S/N signal-to-noise ratio of output signals note 43

for RGB input note 7 − 60 − dB
for CVBS input note 7 50 56 − dB

f

res(p-p)

residual frequency at f

osc

in the RGB

outputs (peak-to-peak value)

note 23 −−25 mV

f

res(p-p)

residual frequency at 2f

osc

plus
higher harmonics in the RGB outputs
(peak-to-peak value)

−−25 mV

V

diff

difference in black level between the
three outputs

nominal brightness −−100 mV

V

bl

black level shift with picture content note 7 − 0 − mV

∆bl/∆T variation of black level with

temperature

note 7 −2 − 0 mV/K

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 23

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Notes to the “Characteristics”

1. It is possible to start the horizontal oscillator when a current of 5.5 mA is supplied to this pin. In this condition the main
part of the IC is not active and this results in the frequency of the oscillator not being controlled at the correct value.
Consequently, the oscillator frequency will be higher than normal, the maximum deviation will be 75%. When the
start-up function is used the maximum voltage on pin 36 must be limited to 8.8 volts.

2. On set AGC.

3. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.

4. Measured at 10 mV RMS top sync input signal.

5. So called projected zero point, i.e. with switched demodulator.

6. Measured in accordance with the test line given in Fig.11. For the differential phase test the peak white setting is
reduced to 87%.

The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.

The phase difference is defined as the difference in degrees between the largest and smallest phase angle.

7. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.

8. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.12.

9. Insertion (suppression of the interference pulses) to a level of 2.6 V is active only during a strong input signal.
This is because the noise inverter has a negative effect on the sound performance at a weak input signal.

10. The test set-up and input conditions are given in Fig.13. The figures are measured with an input signal of
10 mV RMS.

RGB

AMPLIFIERS (PINS 18, 19 AND 20)

∆bl/∆CON variation of black level over contrast

range

nominal saturation;
note 7

−−100 mV

∆bl/∆SAT variation of black level over

saturation range

nominal contrast;
note 7

−−50 mV

∆bl relative variation in black level

between the three channels during
variations of

supply voltage (±10%) nominal saturation −−50 mV
saturation (50 dB) nominal contrast −−25 mV
contrast (20 dB) nominal saturation −−60 mV
brightness (±0.5 V) nominal controls −−100 mV

V

diff

differential drift of black level over a
temperature range of 40 °C

note 7 −−10 mV

B bandwidth of output signals for −3dB

RGB input 8 −−MHz
CVBS input f

osc

= 3.58 MHz − 2.8 − MHz

CVBS input f

osc

= 4.43 MHz − 3.5 − MHz

S-VHS input 8 −−MHz

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

March 1994 24

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

11. Measured with a source impedance of 75 Ω, where:

12. To obtain a good noise immunity of the AGC circuit the AGC detector is gated during the sync pulse. This gating is
switched off during the vertical retrace to avoid disturbances of the signal amplitude due to phase errors of the
incoming video signal which are caused by the head-switching of VCRs.

13. When the leakage current of the capacitor exceeds this value it will result in a reduced performance of the AGC
(amplitude variation during line or frame) but it will not result in a hang-up situation.

14. The AFC slope is directly related to the Q-factor of the demodulator tuned circuit. The given AFC steepness is
obtained with a Q-factor of 60. When a lower steepness is required this can be obtained by connecting an external
resistor to the AFC output (the output impedance is 50 kΩ). The AFC off-set is tested with a double sideband input
signal and with the reference tuned circuit tuned to minimum AGC voltage (optimum tuning for the demodulator).

15. For positive modulated signals the FM sound demodulator for the sound is not required. This is because the sound
signal is amplitude modulated. Therefore the TDA8362 can be switched to positive modulation via the de-emphasis
pin (pin 1). When switched to positive modulation the audio switch is set to ‘external’ so that the demodulated audio
signal can be supplied to the input. The option between AM sound and SCART audio signals is achieved by means
of an external switch.

16. The sound IF input is combined with the AF volume control. The IF signal is internally AC coupled to the limiter
amplifier. The volume control voltage must be supplied to this pin via a resistor.

17. VI = 100 mV RMS; FM: 1 kHz, ∆f = ±50 kHz.

18. VI = 50 mV RMS, f = 4.5/5.5 MHz;
FM: 70 Hz ±50 kHz deviation
AM: 1 kHz at 30% modulation.

19. VI = 100 mV RMS, 5.5 MHz; FM: 1 kHz, ±17.5 kHz deviation; 15 kHz bandwidth; audio attenuator at −6 dB.

20. Audio attenuator at −20 dB; temperature range 10 to 50 °C.

21. In the TDA8361 and TDA8362 the audio and CVBS switches are controlled via the chrominance input pin.
Table 1 lists the various possibilities.

When the DC voltage has a value between 3 and 5 V the switches are set to the S-VHS position. The chrominance
trap is then switched off and separate Y and chrominance signals have to be applied to the inputs (the audio switch
is set to external in this condition). The audio switch is also set to external when the IF amplifier is switched to positive
modulation (see also note 15).

22. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

23. This parameter is measured at nominal settings of the various control voltages.

24. Burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mV (p-p).

25. Nominal contrast is specified as maximum contrast −3 dB. Nominal saturation as maximum −12 dB. The nominal
brightness control voltage is 2.5 V.

26. When the data blanking input pulse exceeds a level of 4 V the RGB outputs are blanked. In this condition it is possible
to supply ‘On-Screen-Display’ signals to the outputs. This blanking overrules both the internal and external
RGB signals.

27. The −3 dB bandwidth of the circuit can be calculated by means of the following equation:

S/N = 20 log

V

O

(black-to-white)

V

m rms()

B = 5 MHz()

---------------------------------------------------------

f

3dB–

f

osc

1

1

2Q

--------

–





=

March 1994 25

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

28. The amplitude response curve can be expressed as follows:
A(f) = 1 + K1 − cos (180 x f/3.1 MHz)
and is realised with a transversal peaking filter having delay sections of 160 ns each. In the ‘neutral’ setting K = 0

and in the minimum setting K = −0.5.
The peaking signal amplifier is linear for 250 ns step input signals up to 50 IRE units. For higher amplitudes the

marginal gain is reduced. When the horizontal PLL is not synchronized (no signal present at the video input) the
peaking control voltage is pulled down by means of an internal current. This information can be used to detect
whether an input signal is available.

29. Slicing level independent of sync pulse amplitude.

30. The horizontal and vertical sync are stable while processing Copy Guard signals and signals with phase shifted sync
pulses (stretched tapes). Trick mode conditions of the VCR will also not disturb the synchronization. The value given
is the delay caused by the vertical sync pulse integrator. The integrator has been designed such that the vertical sync
is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 µs.

31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition. Therefore the circuit contains a noise detector and the time
constant is switched to ‘slow’ when excessive noise is present in the signal (only when the internal video signal is
selected, when the video switch is in the external mode the time constant is always ‘fast’). In the ‘fast’ mode during
the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of
the VCR are corrected as soon as possible.

When no video signal is received the time constant of the first loop is switched to ‘very slow’. This ensures a stable
OSD when the receiver is switched to a channel without transmitter.

The output current of the phase detector for the various conditions is shown in Table 2.

32. Picture shift can be obtained by means of a variable external load on the second phase detector. The control range
is ±2 µs; the required current for this phase shift is ±6 µA.

33. The vertical blanking pulse in the RGB outputs has a width of 22 or 17.5 lines (50 or 60 Hz system). The width of the
vertical sync pulse in the sandcastle pulse is 14 lines. This is to prevent a phase distortion on top of the picture due
to a timing modulation of the incoming flyback pulse.

34. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
This divider circuit has 2 search modes of operation:

The ‘large window’ mode is switched on when the circuit is not synchronized or, when a non-standard signal is
received (the number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between
261 and 264). In the search mode the divider can be triggered between line 244 and line 361 (approximately
45 to 64.5 Hz)

The ‘narrow window’ mode is switched on when more than 15 successive vertical sync pulses are detected in the
narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the
vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small.
The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found
within the window.

35. This precorrection is intended to compensate for non-linearity of AC coupled vertical output stages. The value given
indicates the amplitude of the correction waveform with respect to the sawtooth amplitude.

36. At a chrominance input voltage (related to CVBS2) of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal
amplitude 300 mV (p-p)) the dynamic range of the ACC is +6 and −20 dB.

March 1994 26

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

37. All frequency variations are referenced to 3.58/4.43 MHz carrier frequency.
All oscillator specifications are measured with the Philips crystal series 9922 520.
If the spurious response of the 4.43 MHz crystal is lower than −3 dB with respect to the fundamental frequency for a
damping resistance of 1 kΩ, oscillation at the fundamental frequency is guaranteed.
The spurious response of the 3.58 MHz crystal must be lower than −3 dB with respect to the fundamental frequency
for a damping resistance of 1.5 kΩ.

The catching and detuning range are measured for nominal crystal parameters. These are:
a) load resonance frequency f0 (CL = 20 pF) = 4.433619 or 3.579545 MHz
b) motional capacitance CM = 20.6 fF (4.43 MHz crystal) or (3.58 MHz crystal)
c) parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal).
The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on

and off chip.
The free-running frequency of the oscillator can be checked by pulling the saturation control pin to the positive supply
rail. In that condition the colour killer is not active so that the frequency off-set is visible on the screen. When two
crystals are connected to the IC the circuit must be forced to one of the crystals during this test to prevent the
oscillator continuously switching between the two frequencies.

38. In the TDA8362 the hue control pin has a double function. When the control voltage has a value of 0 to 5 V (normal
control range) the hue can be controlled when NTSC signals are decoded. When this voltage is increased to a value
greater than 5.5 V the decoder is forced to the PAL standard. When this pin is connected to the positive supply line
via a 10 kΩ resistor the selected CVBS signal, of the CVBS switch, is available. This signal can be applied to the
SECAM decoder TDA8395.
The phase shift of the hue control can be measured at the colour difference outputs (pins 30 and 31).

39. The −(R−Y) and −(B−Y) signals are demodulated with the 90° phase difference of the reference carrier and a gain
ratio −(B−Y)/−(R−Y) = 1.78. The matrixing to the required signals is achieved in the control part.

40. This value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter.
The bandwidth of the demodulator low-pass filter is approximately 1 MHz.

41. The reference signal for the TDA8395 is available only when the crystal oscillator is operating at a frequency of

4.43 MHz. When a SECAM signal is identified this signal is only available during the vertical retrace period thus
avoiding crosstalk with the incoming SECAM signal during scan.

42. When one of the three output signals exceeds this level the gain of the amplifiers is reduced. This is achieved by a
reduction of contrast and thus avoids clipping of the output signals. The discharge current at pin 25 is 0.2 mA. When
the black level exceeds a value of 2 V the maximum peak-to-peak value of the video output signal will be less than
4 V (p-p); this is due to the operation of the peak-white limiter.

43. The signal-to-noise ratio is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). During
the measurement the peaking control voltage is set to nominal.

44. The typical free running frequency is dependent on the crystal which is used for calibration. With 4.4 MHz the typical
free running frequency is 15625, with 3.58 MHz the typical free running frequency is 15734.
Calibration during start-up is always carried out with a 4.4 MHz crystal if no forced mode is used.

March 1994 27

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Table 1 Audio and CVBS switch selection.

Table 2 Output current of phase detector.

QUALITY SPECIFICATION

Quality level in accordance with UZW B0/FQ-0601.

Note

1. All pins are protected against ESD by means of internal clamping diodes.

LEVEL

(pin 16)

INTERNAL

CVBS

EXTERNAL

CVBS/Y

CHROMINANCE CHROMINANCE TRAP AUDIO

DC ≤ 0.5 V ON OFF OFF ON internal
3 ≤ DC ≤ 5 V OFF ON (Y) ON OFF external
DC ≥ 7.5 V OFF ON (CVBS) OFF ON external

CURRENT Φ1 DURING SCAN (µA) VERTICAL RETRACE (µA) GATED YES/NO

Weak signal and synchronized 30 30 YES (5.7 µs)
Strong signal and synchronized 180 270 NO
Not synchronized 180 270 NO
No video identification 6 6 NO

SYMBOL PARAMETER RANGE A RANGE B UNIT

ESD protection circuit specification (note 1) 2000 200 V

100 200 pF

1500 0 Ω

March 1994 28

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Fig.5 Volume control curve.

MBC208

0

20

40

60

80

100

(dB)

012345

(V)

Fig.6 Peaking control curve.

MBC207 - 1

50

30

10

10

30

50

(%)

012345

(V)

Fig.7 Hue control curve

MBC206 - 1

60

40

20

20

40

60

(deg)

012345

(V)

0

Fig.8 Saturation control curve.

MBC204

300

250

200

150

100

50

0

(%)

012345

(V)

March 1994 29

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

Fig.9 Contrast control curve.

MBC205

100

80

60

40

20

0

(%)

012345

(V)

Fig.10 Brightness control curve.

MBC209

1.0

0

1.0

(V)

012345

(V)

Fig.11 Video output signal.

MBC212

100%

92%

30%

16 %

for negative modulation

100% = 10% rest carrier

March 1994 30

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

handbook, full pagewidth

MBC213

SC CC PC

30 dB

13.2 dB

3.2 dB

SC CC PC

30 dB

13.2 dB

10 dB

BLUE

YELLOW

MBC210

ATTENUATOR

SPECTRUM

ANALYZER

TEST

CIRCUIT

CC

PC

SC Σ

gain setting
adjusted for blue

Fig.13 Test set-up intermodulation.

Input signal conditions: SC = sound carrier; CC = colour carrier;PC = picture carrier.
All amplitudes with respect to top sync level.

Value at 0.92 or 1.1 MHz 20 log

V

O

at 3.58 or 4.4 MHz

V

O

at 0.92 or 1.1 MHz

------------------------------------------------------------

3.6 dB+=

Value at 2.66 or 3.3 MHz 20 log

V

O

at 3.58 or 4.4 MHz

V

O

at 2.66 or 3.3 MHz

------------------------------------------------------------

=

Fig.12 Test signal waveform.

ndbook, full pagewidth

MBC211

100%

86%
72%
58%
44%
30%

646056524844403632221210 26

µs

March 1994 31

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

PACKAGE OUTLINE

Fig.14 52-lead shrink dual in-line; plastic (SOT247AG).

Dimensions in mm.

handbook, full pagewidth

1

27

26

1.3 max

14.1

13.7

47.92

47.02

4.57
max

5.08
max

0.51
min

3.2

2.8

seating plane

0.18

M

0.53
max

1.778
(25x)

1.73
max

15.80

15.24

0.32 max

15.24

17.15

15.90

MSA267

52

SOLDERING
Plastic dual in-line packages

B

Y DIP OR WAVE

The maximum permissible temperature of the solder is
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified storage maximum. If the printed-circuit board has
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within
the permissible limit.

REPAIRING SOLDERED JOINTS
Apply the soldering iron below the seating plane (or not

more than 2 mm above it). If its temperature is below
300 °C, it must not be in contact for more than 10 s; if
between 300 and 400 °C, for not more than 5 s.

March 1994 32

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

March 1994 33

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

NOTES

March 1994 34

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

NOTES

March 1994 35

Philips Semiconductors Objective specification

Integrated PAL and PAL/NTSC TV
processors

TDA8360; TDA8361; TDA8362

NOTES

Philips Semiconductors

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SCD29 © Philips Electronics N.V. 1994

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