Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA8358J
Fullbridgeverticaldeflectionoutput
circuit in LVDMOS with east-west
amplifier
Product specification
File under Integrated Circuits, IC02
1999 Dec 22
Page 2
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
FEATURES
• Few external components required
• High efficiency fully DC coupled vertical bridge output
circuit
• Vertical flyback switch with short rise and fall times
• Built-in guard circuit
• Thermal protection circuit
• Improved EMC performance due to differential inputs
• East-west output stage.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
P
V
FB
I
q(P)(av)
I
q(FB)(av)
P
EW
P
tot
supply voltage 7.5 12 18 V
flyback supply voltage 2V
average quiescent supply current during scan − 10 15 mA
average quiescent flyback supply current during scan −−10 mA
east-west power dissipation −−4W
total power dissipation −−15 W
Inputs and outputs
V
i(dif)(p-p)
I
o(p-p)
differential input voltage (peak-to-peak value) − 1000 1500 mV
output current (peak-to-peak value) −−3.2 A
Flyback switch
I
o(peak)
maximum (peak) output current t ≤ 1.5 ms −−±1.8 A
East-west amplifier
V
V
I
o
o
I(bias)
output voltage −−68 V
input bias voltage 2 − 3.2 V
output current −−750 mA
Thermal data; in accordance with IEC 747-1
T
stg
T
amb
T
j
storage temperature −55 − +150 °C
ambient temperature −25 − +75 °C
junction temperature −−150 °C
GENERAL DESCRIPTION
The TDA8358J is a power circuit for use in 90° and 110°
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9picturetubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.
The east-west output stage is able to supply the sink
current for a diode modulator circuit.
The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.
45 66 V
P
1999 Dec 22 2
Page 3
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
ORDERING INFORMATION
TYPE
NUMBER
NAME DESCRIPTION VERSION
TDA8358J DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6
BLOCK DIAGRAM
handbook, full pagewidth
V
I(bias)
COMP
13
COMP.
CIRCUIT
V
i(p-p)
1
INA
0
V
i(p-p)
FEEDBACK
CIRCUIT
GUARD
GUARD
CIRCUIT
INPUT
AND
PACKAGE
V
11 93
D1
P
M2
M4
D3
V
FB
M5
D2
OUTA
10
12
FEEDB
V
I(bias)
I
I(av)
0
I
i(p-p)
0
INB
INEW
2
Fig.1 Block diagram.
1999 Dec 22 3
M1
M3
TDA8358J
M6
67
VGND EWGND
4
85
OUTB
OUTEW
MGL866
Page 4
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
PINNING FUNCTIONAL DESCRIPTION
SYMBOL PIN DESCRIPTION
INA 1 input A
INB 2 input B
V
P
3 supply voltage
OUTB 4 output B
INEW 5 east-west input
VGND 6 vertical ground
EWGND 7 east-west ground
OUTEW 8 east-west output
V
FB
9 flyback supply voltage
OUTA 10 output A
GUARD 11 guard output
FEEDB 12 feedback input
COMP 13 compensation input
handbook, halfpage
EWGND
OUTEW
GUARD
FEEDB
Thedie hasbeen glued to the metal block ofthe package.If the metal
block is not insulated from the heatsink, the heatsink shall only be
connected directly to pin VGND.
INA
INB
V
OUTB
INEW
VGND
V
FB
OUTA
COMP
P
1
2
3
4
5
6
TDA8358J
7
8
9
10
11
12
13
MGL867
Vertical output stage
The vertical driver circuit has a bridge configuration.
The deflection coil is connected between the
complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially
designed for direct connection to driver circuits delivering
a differential signal but it is also suitable for single-ended
applications. The output currents of the driver device are
converted to voltages by the conversion resistors
R
CV1
and R
(see Fig.3) connected to pins INA
CV2
and INB. The differential input voltage is compared with
the voltage across the measuring resistor RM, providing
internal feedback information. The voltage across RM is
proportional with the output current. The relationship
between the differential input current and the output
current is defined by:
2 × I
i(dif)(p-p)
× RCV=I
o(p-p)
× R
The output current should measure 0.5 to 3.2 A (p-p) and
is determined by the value of RMand RCV. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances.DependingonthevalueofRMandtheinternal
bondwireresistance (typical value 50 mΩ) the actualvalue
of the current in the deflection coil will be about 5% lower
than calculated.
Flyback supply
The flyback voltage is determined by the flyback supply
voltage VFB.The principle of two supply voltages (class G)
allows to use an optimum supply voltage VP for scan and
an optimum flyback supply voltage VFB for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to VFB, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short
rise and fall times of the flyback switch are determined
mainly by the slew-rate value of more than 300 V/µs.
Protection
The output circuit contains protection circuits for:
• Too high die temperature
• Overvoltage of output A.
TDA8358J
M
Fig.2 Pin configuration.
1999 Dec 22 4
Page 5
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
Guard circuit
A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the
flyback period. The guard circuit is also activated for one
of the following conditions:
• During thermal protection (Tj≈ 170 °C)
• During an open-loop condition.
The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.
Damping resistor compensation
HF loop stability is achieved by connecting a damping
resistor RD1 (see Fig.4) across the deflection coil.
The current values in RD1 during scan and flyback are
significantly different. Both the resistor current and the
deflection coil current flow into measuring resistor RM,
resulting in a too low deflection coil current at the start of
the scan.
The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time.
TDA8358J
For that purpose a compensation resistor R
connected between pins OUTA and COMP. The value of
R
is calculated by:
CMP
VFBV
R
CMP
– V
=
------------------------------------------------------------------------------------------------------------V
loss FB()
– I
FBVloss FB()
–()R
× RS300+()×
P
D1
R
coil peak()
×–()R
where:
• R
is the coil resistance
coil
• V
isthe voltage loss between pins VFBand OUTA
loss(FB)
at flyback.
East-west amplifier
The east-west amplifier is a current driver sinking the
current of a diode modulator circuit. A feedback
resistor R
(see Fig.4) has to be connected between
EWF
the input and output of the inverting east-west amplifier in
order to convert the east-west correction input current into
an output voltage. The output voltage of the east-west
circuit at pin OUTEW is given by:
Vo≈ Ii× R
The maximum output voltage is V
EWF+Vi
= 68 V, while the
o(max)
maximum output current of the circuit is I
is
CMP
×
coil
o(max)
M
= 750 mA.
1999 Dec 22 5
Page 6
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
P
V
FB
∆V
VGND-EWGND
V
n
I
n
I
lu
V
es
P
EW
P
tot
T
stg
T
amb
T
j
supply voltage − 18 V
flyback supply voltage − 68 V
voltage difference between
− 0.3 V
pins VGND and EWGND
DC voltage
pins OUTA and OUTEW note 1 − 68 V
pin OUTB − V
pins INA, INB, INEW, GUARD,
−0.5 V
P
P
FEEDB, and COMP
DC current
pins OUTA and OUTB during scan (p-p) − 3.2 A
pins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms −±1.8 A
pins INA, INB, INEW, GUARD,
−20 +20 mA
FEEDB, and COMP
pin OUTEW − 750 mA
latch-up current input current into any pin;
− +200 mA
pin voltage is 1.5 × VP; Tj= 150 °C
input current out of any pin;
pin voltage is −1.5 × V
; Tj= 150 °C
P
−200 − mA
electrostatic handling voltage machine model; note 2 −300 +300 V
human body model; note 3 −2000 +2000 V
east-west power dissipation note 4 − 4W
total power dissipation − 15 W
storage temperature −55 +150 °C
ambient temperature −25 +75 °C
junction temperature note 5 − 150 °C
V
V
Notes
1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.
2. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.
3. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.
4. For repetitive time durations of t < 0.1 ms or a non repetitive time duration of t < 5 ms the maximum (peak) east-west
power dissipation P
EW(peak)
=15W.
5. Internally limited by thermal protection at Tj≈ 170 °C.
THERMAL CHARACTERISTICS
In accordance with IEC 747-1.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
R
th(j-c)
th(j-a)
thermal resistance from junction to case 4 K/W
thermal resistance from junction to ambient in free air 40 K/W
1999 Dec 22 6
Page 7
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
CHARACTERISTICS
VP= 12 V; VFB= 45 V; f
specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
P
V
FB
I
q(P)(av)
I
q(P)
I
q(FB)(av)
operating supply voltage 7.5 12 18 V
flyback supply voltage note 1 2V
average quiescent supply current during scan − 10 15 mA
quiescent supply current no signal; no load − 55 75 mA
average quiescent flyback supply
current
Inputs A and B
V
i(dif)(p-p)
differential input voltage
(peak-to-peak value)
V
I(bias)
I
I(bias)
input bias voltage note 2 100 880 1600 mV
input bias current − 25 35 µA
Outputs A and B
V
loss(1)
V
loss(2)
I
o(p-p)
voltage loss first scan part note 3
voltage loss second scan part note 4
output current (peak-to-peak value) −−3.2 A
LE linearity error I
V
offset
∆V
offset(T)
offset voltage across RM; V
offset voltage variation with
temperature
V
O
G
v(ol)
f
−3dB(h)
G
v
∆G
v(T)
DC output voltage V
open-loop voltage gain notes 7 and 8 − 60 − dB
high −3 dB cut-off frequency open-loop − 1 − kHz
voltage gain note 9 − 1 −
voltage gain variation with
temperature
PSRR power supply rejection ratio note 10 80 90 − dB
= 50 Hz; V
vert
I(bias)
= 880 mV; T
during scan −−10 mA
note 2 − 1000 1500 mV
across RM; V
=25°C; measured in test circuit of Fig.3; unless otherwise
amb
45 66 V
P
I
= 1.1 A −−4.5 V
o
I
= 1.6 A −−6.6 V
o
= −1.1 A −−3.3 V
I
o
I
= −1.6 A −−4.8 V
o
= 3.2 A; notes 5 and 6
o(p-p)
adjacent blocks − 12%
non adjacent blocks − 13%
=0V
i(dif)
V
= 200 mV −−±15 mV
I(bias)
V
=1V −−±20 mV
I(bias)
=0V −−40 µV/K
i(dif)
=0V − 0.5VP− V
i(dif)
−−10
−4
K
−1
1999 Dec 22 7
Page 8
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Flyback switch
I
o(peak)
V
loss(FB)
Guard circuit
V
O(grd)
V
O(grd)(max)
I
O(grd)
East-west amplifier
V
o
V
loss
V
I(bias)
I
I(bias)
G
v(ol)
THD harmonic distortion − 0.5 1 %
f
−3dB(h)
Notes
1. To limit V
and VFB at the first part of the flyback.
2. Allowable input range for both inputs: V
3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and
between pins OUTB and GND. Specified for Tj= 125 °C. The temperature coefficient for V
4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and
between pins OUTA and GND. Specified for Tj= 125 °C. The temperature coefficient for V
5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
parts. The 1st and 22nd parts are ignored, and the remaining 20 parts form 10 successive blocks k. A block consists
of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at k = 10,
where Vk and V
maximum and average voltages respectively. The linearity errors are defined as:
maximum (peak) output current t ≤ 1.5 ms −−±1.8 A
voltage loss at flyback note 11
I
= 1.1 A − 7.5 8.5 V
o
= 1.6 A − 89V
I
o
guard output voltage I
allowable guard voltage maximum leakage current
output current V
= 100 µA 567V
O(grd)
−−18 V
I
=10µA
L(max)
= 0 V; not active −−10 µA
O(grd)
= 4.5 V; active 1 − 2.5 mA
V
O(grd)
output voltage at pin OUTEW −−68 V
voltage loss Io= 750 mA; note 12 −−5V
input bias voltage 2 2.5 3.2 V
input bias current into pin INEW; note 13
= 100 mA − 2.5 −µA
I
o
I
= 500 mA − 11.5 −µA
o
open-loop voltage gain −−30 dB
high −3 dB cut-off frequency −−1 MHz
to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA
OUTA
I(bias)+Vi(dif)(peak)
are the measured voltages of two successive blocks. V
k+1
< 1600 mV and V
I(bias)
min
, V
− V
max
i(dif)(peak)
and V
> 100 mV.
is a positive value.
loss(1)
is a positive value.
loss(2)
are the minimum,
avg
–
V
a) (adjacent blocks)
LE
b) (non adjacent blocks)
LE
kVk1+
------------------------- V
avg
–
V
maxVmin
-------------------------------
V
avg
100%×=
100%×=
1999 Dec 22 8
Page 9
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
TDA8358J
in LVDMOS with east-west amplifier
6. The linearity errors are specified for a minimum input voltage of 300 mV single-ended. Lower input voltages lead to
voltage dependent S-distortion in the input stage.
V
–
7.
G
vol()
8. Pin FEEDB not connected.
9.
G
V
10. V
P(ripple)
11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.
12. This value specifies the internal voltage loss of the current path between pins OUTEW and EWGND.
13. Measured for R
a) For Io= 100 mA and a voltage of 9 V at R
input current (see Fig.4) is Ii= 300 µA.
b) For Io= 500 mA and a voltage of 21 V at R
input current (see Fig.4) is Ii= 350 µA.
OUTAVOUTB
=
-------------------------------------------V
V
FEEDBVOUTB
=
-------------------------------------------V
–
FEEDBVOUTB
–
–
INAVINB
= 500 mV (RMS value); 50 Hz < f
=10kΩ; R
EWF
EWL
< 1 kHz; measured across RM.
P(ripple)
=30Ω; Vo=6V.
connected to the line output transformer, the east-west amplifier
EWL
connected to the line output transformer, the east-west amplifier
EWL
1999 Dec 22 9
Page 10
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
APPLICATION INFORMATION
handbook, full pagewidth
V
I(bias)
0
V
I(bias)
0
I
I(av)
0
V
i(p-p)
I
I(bias)
I
I(bias)
V
i(p-p)
I
i(p-p)
I
i(dif)
I
i
INA
R
CV1
2.2 kΩ
(1%)
INB
R
CV2
2.2 kΩ
(1%)
INEW
I
i
CIRCUIT
1
2
COMP
13
COMP.
INPUT
AND
FEEDBACK
CIRCUIT
R
GRD
4.7 kΩ
CIRCUIT
R
EWF
10 kΩ
GUARD
11 93
GUARD
VGND EWGND
D1
V
M2
M4
M1
M3
6
P
V
FB
M5
D3
TDA8358J
7
M6
D2
10
12
4
85
OUTA
FEEDB
OUTB
OUTEW
TDA8358J
C1
100 nFC2100 nF
R
L
3.2 Ω
R
S
2.7 kΩ
C
M
10 nF
R
MGL873
EWL
30 Ω
R
M
0.5 Ω
to line output
transformer
V
P
V
FB
Fig.3 Test diagram.
1999 Dec 22 10
Page 11
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1999 Dec 22 11
ll pagewidth
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
V
I(bias)
0
DEFLECTION
CONTROLLER
V
I(bias)
0
I
I(av)
0
V
V
I
i(p-p)
i(p-p)
i(p-p)
C6
2.2 nF
C7
2.2 nF
R
CV1
2.2 kΩ
(1%)
R
CV2
2.2 kΩ
(1%)
I
i
INA
INB
INEW
1
2
COMP
13
COMP.
CIRCUIT
INPUT
AND
FEEDBACK
CIRCUIT
R
GRD
5.6 kΩ
R
EWF
82 kΩ
GUARD
11 3
GUARD
CIRCUIT
V
P
M2
D1
M4
M1
M3
6
VGND EWGND
V
FB
9
M5
D3
TDA8358J
M6
7
2.7 µH
D2
10
12
4
(3)
OUTA
OUTEW
85
FEEDB
OUTB
C3
100
nF
R
CMP
820 kΩ
R
2.7 kΩ
R
EWL
12 Ω
MGL874
S
C1
47 µF
(100 V)
R
D1
270 Ω
to line output
transformer
R
FB
10 Ω
C4
100 nF
(2)
D1
deflection
coil
5 mH
6 Ω
(W66ESF)
R
M
0.5 Ω
VP = 14 V
V
fb
C2
220 µF
(25 V)
(1)
C
D
47 nF
(1)
R
D2
22 Ω
= 30 V
Deflection circuit: f
East-west amplifier: I
(1) Optional, component values depend on the deflection coil impedance.
(2) Extended flash over protection; BYD33D or equivalent.
(3) Optional, extended flash over protection.
= 50 Hz; tFB= 640 µs; I
vert
= 290 µA; I
i(B)
i(T)
I(bias)
= 510 µA.
= 400 µA; I
i(dif)(peak)
= 290 µA; I
= 2.4 A.
o(p-p)
Fig.4 Application diagram.
TDA8358J
Page 12
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
Supply voltage calculation
For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required
maximum (peak) deflection coil current I
parameters R
coil
and L
, and the measuring resistance
coil
coil(peak)
of RM. The required maximum (peak) deflection coil
current should also include the overscan.
The deflection coil resistance has to be multiplied with 1.2
in order to take account of hot conditions.
Chapter “Characteristics” supplies values for the voltage
losses of the vertical output stage. For the first part of the
scan the voltage loss is given by V
. For the second
loss(1)
part of the scan the voltage loss is given by V
The voltage drop across the deflection coil during scan is
determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.
For the vertical frequency the maximum frequency
occurring must be applied to the calculations.
The required power supply voltage VP for the first part of
the scan is given by:
V
P1()Icoil peak()
L
coil2Icoil peak()
×=
R
coilRM
f
vert max()
+()
V
+××–
loss 1()
The required power supply voltage VPfor the second part
of the scan is given by:
V
P2()Icoil peak()
L
coil2Icoil peak()
R
+()×=
coilRM
f
vert max()
V
+××+
loss 2()
The minimum required supply voltage VP shall be the
highest of the two values V
P(1)
and V
. Spread in supply
P(2)
voltage and component values also has to be taken into
account.
Flyback supply voltage calculation
If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:
R
+
coilRM
V
FBIcoil p p–()
×=
-------------------------- -
–
1e
t–FBx⁄
where:
L
=
-------------------------- R
coilRM
coil
+
x
, the coil
loss(2)
.
TDA8358J
The flyback supply voltage calculated this way is about
5% to 10% higher than required.
Calculation of the power dissipation of the vertical output stage
The power dissipation of the vertical output stage is given
by the formula:
PV=P
The power to be supplied is given by the formula:
P
supVP
In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.
The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:
P
L
Example
Table 1 Application values
I
coil(peak)
I
coil(p-p)
L
coil
R
coil
R
M
f
vert
t
FB
Table 2 Calculated values
V
P
RM+R
t
vert
x 0.000641
V
FB
P
sup
P
L
P
V
− P
sup
L
I
coil peak()
-----------------------2
I
()
coil peak()
------------------------------- -
2
3
R
V
P
+()×=
coilRM
0.015 [A] 0.3 [W]+×+×=
SYMBOL VALUE UNIT
1.2 A
2.4 A
5mH
6 Ω
0.6 Ω
50 Hz
640 µs
SYMBOL VALUE UNIT
14 V
(hot) 7.8 Ω
coil
0.02 s
30 V
8.91 W
3.74 W
5.17 W
1999 Dec 22 12
Page 13
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
Power dissipation calculation for the east-west stage
In general the shape of the east-west output wave form is
a parabola. The output voltage will be higher at the
beginning and end of the vertical scan compared to the
voltage at the scan middle, while the output current will be
higheratthescanmiddle.Thisresultsin an almost uniform
power dissipation distribution during scan. Therefore the
power dissipation can be calculated by multiplying the
average values of the output voltage and the output
current of pin OUTEW.
When verifying the dissipation also the start-up and stop
dissipation should be taken into account. Power
dissipation during start-up can be 3 to 5 times higher than
during normal operation.
Heatsink calculation
The value of the heatsink can be calculated in a standard
way with a method based on average temperatures.
The required thermal resistance of the heatsink is
determined by the maximum die temperature of 150 °C.
In general we recommend to design for an average die
temperature not exceeding 130 °C. It should be noted
that the heatsink thermal resistance R
performing a standard calculation will be lower then
normally found for a vertical deflection stand alone device,
due to the contribution of the EW power dissipation to this
value.
EXAMPLE
Measured or known values:
PEW= 3 W; PV= 6 W; T
R
= 4 K/W; R
th(j-c)
th(c-h)
=40°C; Tj= 130 °C;
amb
= 1 K/W.
th(h-a)
found by
TDA8358J
The required heatsink thermal resistance is given by:
TjT
–
R
th h a–()
When we use the values known we find:
R
th h a–()
The heatsink temperature will be:
Th=T
amb+Rth(h-a)
Equivalent thermal resistance network
The TDA8358J has two independent power dissipating
systems, the vertical output circuit and the east-west
circuit.
Itisrecommended to verify the individual maximum (peak)
junction temperatures of both circuits. Therefore the
maximum (peak) power dissipations of the circuits and
also the heatsink temperature should be measured.
The maximum (peak) junction temperatures can be
calculated by using an equivalent thermal network
(see Fig.5).
The network does only consist the contribution of the
maximum (peak) power dissipation P
dissipation of the most critical transistor internally
connected to pins OUTB and VGND. The model assumes
equivalent maximum (peak) power dissipations during the
different vertical scan stages for all the functionally paired
transistors. The calculated maximum (peak) junction
temperatures should not exceed Tj= 150 °C.
amb
------------------------P
+
EWPV
130 40–
---------------------36+
× P
– R
R(
th j c–()
)+=
th c h–()
4(– 1 )+ 5 K/W==
=40+5×9=85°C
tot
TRv(peak)
, being the
1999 Dec 22 13
Page 14
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
th(EW-P1)
10.5 K/W
P
EW
T
EW(M)
T
handbook, halfpage
R
Fig.5 Equivalent thermal resistance network.
P1(M)
T
c
T
R
th(P1-c)
2.2 K/W
P
tot
TRv(M)
R
MGL872
th(TRv-P1)
5.2 K/W
P
TRv(M)
TDA8358J
EXAMPLE
Measured or known values:
• The east-west power dissipation: PEW=3W
• The vertical power dissipation: PV=6W
• The maximum (peak) power dissipation of the most
critical transistor: P
TRv(peak)
• The case temperature: Tc=85°C.
The IC total power dissipation is:
P
tot=PEW+PV
=6+3=9W
It should be noted that the allowed IC total power
dissipation is P
= 15 W (maximum value).
tot
The maximum (peak) temperature T
• T
P1(peak)=Tc
+(PEW+P
=85+(3+5)×2.2 = 102.6 °C
The maximum (peak) junction temperatures for the output
circuits are given by:
• T
j(EW)(peak)=TP1(peak)+Rth(EW-P1)
= 102.6 + 10.5 × 3 = 134.1 °C
• T
j(TRv)(peak)=TP1(peak)+Rth(TRv-P1)
= 102.6 + 5.2 × 5 = 128.6 °C
=5W
TRv(peak)
P1(peak)
) × R
× P
× P
is given by:
th(P1-c)
EW
TRv(peak)
1999 Dec 22 14
Page 15
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
INTERNAL PIN CONFIGURATION
PIN SYMBOL EQUIVALENT CIRCUIT
1 INA
1
2 INB
2
300 Ω
300 Ω
TDA8358J
MBL100
MBL102
3V
P
4 OUTB
6 VGND
9V
FB
10 OUTA
5 INEW
7 EWGND
8 OUTEW
300 Ω
MGL869
9
3
10
4
6
5
7
MGL868
1999 Dec 22 15
8
Page 16
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
PIN SYMBOL EQUIVALENT CIRCUIT
11 GUARD
300 Ω
12 FEEDB
13 COMP
300 Ω
300 Ω
TDA8358J
11
MGL870
12
MGL871
13
MGL875
1999 Dec 22 16
Page 17
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
PACKAGE OUTLINE
DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
non-concave
x
D
E
h
d
A
D
h
view B: mounting base side
2
TDA8358J
SOT141-6
j
113
e
Z
DIMENSIONS (mm are the original dimensions)
UNIT A e
mm
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
A2bpcD
17.0
4.6
4.4
0.75
0.60
15.5
1
e
(1)
deD
0.48
24.0
23.6
20.0
19.6
0.38
b
p
h
10 3.4
w M
0 5 10 mm
scale
(1)
E
12.2
11.8
1
1.7
e
5.08
B
E
A
L
3
L
E
2
h
6
Q
m
LL3m
3.4
12.4
3.1
11.0
2.4
1.6
c
e
2
4.3
2.1
1.8
v M
(1)
v
Qj
0.8
0.25w0.03
Z
x
2.00
1.45
OUTLINE
VERSION
SOT141-6
IEC JEDEC EIAJ
REFERENCES
1999 Dec 22 17
EUROPEAN
PROJECTION
ISSUE DATE
97-12-16
99-12-17
Page 18
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
SOLDERING
Introduction to soldering through-hole mount
packages
This text gives a brief insight to wave, dip and manual
soldering.Amorein-depth account of soldering ICs can be
found in our
Packages”
Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.
Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods
DBS, DIP, HDIP, SDIP, SIL suitable suitable
“Data Handbook IC26; Integrated Circuit
(document order number 9398 652 90011).
PACKAGE
Thetotalcontacttimeofsuccessivesolderwavesmustnot
exceed 5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.
SOLDERING METHOD
DIPPING WAVE
(1)
TDA8358J
). If the
stg(max)
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Dec 22 18
Page 19
Philips Semiconductors Product specification
Full bridge vertical deflection output circuit
in LVDMOS with east-west amplifier
NOTES
TDA8358J
1999 Dec 22 19
Page 20
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© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
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under patent- or other industrial or intellectual property rights.
1999
Internet: http://www.semiconductors.philips.com
68
Printed in The Netherlands 545004/100/01/pp20 Date of release: 1999 Dec 22 Document order number: 9397 750 06197
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