Datasheet TDA8357J Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8357J

Fullbridgeverticaldeflectionoutput
circuit in LVDMOS

Preliminary specification
File under Integrated Circuits, IC02

1999 Nov 10

Philips Semiconductors Preliminary specification

Full bridge vertical deflection outputcircuit

TDA8357J

in LVDMOS

FEATURES

• Few external components required

• High efficiency fully DC coupled vertical bridge output

circuit

• Vertical flyback switch with short rise and fall times

• Built-in guard circuit

• Thermal protection circuit

• Improved EMC performance due to differential inputs.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

V

FB

I

q(P)(av)

I

q(FB)(av)

P

tot

supply voltage 7.5 12 18 V
flyback supply voltage 2V
average quiescent supply current during scan − 10 15 mA
average quiescent flyback supply current during scan −−10 mA
total power dissipation −−8W

Inputs and outputs

V

i(dif)(p-p)

I

o(p-p)

differential input voltage (peak-to-peak value) − 1000 1500 mV
output current (peak-to-peak value) −−2.0 A

Flyback switch

I

o(peak)

maximum (peak) output current t ≤ 1.5 ms −−±1.2 A

Thermal data; in accordance with IEC 747-1

T

stg

T

amb

T

j

storage temperature −55 − +150 °C
ambient temperature −25 − +75 °C
junction temperature −−150 °C

GENERAL DESCRIPTION

The TDA8357J is a power circuit for use in 90° and 110°
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picturetubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of absence of second breakdown.

45 66 V

P

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8357J DBS9P plastic DIL-bent-SIL power package; 9 leads (lead length

12/11 mm); exposed die pad

1999 Nov 10 2

SOT523-1

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

BLOCK DIAGRAM

handbook, full pagewidth

V

I(bias)

V

I(bias)

V

i(p-p)

1

INA

0

V

i(p-p)

INB

2

0

GUARD

863

GUARD

CIRCUIT

D1

INPUT

AND

FEEDBACK

CIRCUIT

TDA8357J

V

P

M2

M4

M1

M3

D3

V

FB

M5

D2

OUTA

7

9

FEEDB

4

OUTB

PINNING

SYMBOL PIN DESCRIPTION

INA 1 input A
INB 2 input B
V

P

3 supply voltage
OUTB 4 output B
GND 5 ground
V

FB

6 flyback supply voltage
OUTA 7 output A
GUARD 8 guard output
FEEDB 9 feedback input

5

GND

Fig.1 Block diagram.

handbook, halfpage

TDA8357J

INA
INB

V

OUTB

GND

V

FB

OUTA

GUARD

FEEDB

MGS803

P

1
2
3
4
5

TDA8357J

6
7
8
9

MGS804

1999 Nov 10 3

The exposed die pad is connected to pin GND.

Fig.2 Pin configuration.

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

FUNCTIONAL DESCRIPTION
Vertical output stage

The vertical driver circuit has a bridge configuration.
The deflection coil is connected between the
complimentary driven output amplifiers. The differential
input circuit is voltage driven. The input circuit is specially
designed for direct connection to driver circuits delivering
a differential signal but it is also suitable for single-ended
applications. The output currents of the driver device are
converted to voltages by the conversion resistors
R

and R

CV1

and INB. The differential input voltage is compared with
the voltage across the measuring resistor RM, providing
internal feedback information. The voltage across RM is
proportional with the output current. The relationship
between the differential input current and the output
current is defined by:

2 × I

i(dif)(p-p)

The output current should measure 0.5 to 2.0 A (p-p) and
is determined by the value of RMand RCV. The allowable
input voltage range is 100 mV to 1.6 V for each input. The
formula given does not include internal bondwire
resistances. Depending on the values of RM and the
internal bondwire resistance (typical value of 50 mΩ) the
actual value of the current in the deflection coil will be
about 5% lower than calculated.

Flyback supply

The flyback voltage is determined by the flyback supply
voltage VFB.Theprincipleoftwosupplyvoltages(class G)
allows to use an optimum supply voltage VP for scan and
an optimum flyback supply voltage VFB for flyback, thus
very high efficiency is achieved. The available flyback
output voltage across the coil is almost equal to VFB, due
to the absence of a coupling capacitor which is not
required in a bridge configuration. The very short rise
and fall times of the flyback switch are determined mainly
by the slew-rate value of more than 300 V/µs.

(see Fig.3) connected to pins INA

CV2

× RCV=I

o(p-p)

× R

M

TDA8357J

Guard circuit

A guard circuit with output pin GUARD is provided.
The guard circuit generates a HIGH-level during the

flyback period. The guard circuit is also activated for one
of the following conditions:

• During thermal protection (Tj≈ 170 °C)

• During an open-loop condition.

The guard signal can be used for blanking the picture tube
and signalling fault conditions. The vertical
synchronization pulses of the guard signal can be used by
an On Screen Display (OSD) microcontroller.

Damping resistor compensation

HF loop stability is achieved by connecting a damping
resistor RD1across the deflection coil. The current values
in RD1 during scan and flyback are significantly different.
Boththeresistorcurrentandthe deflection coil current flow
intomeasuringresistor RM,resultinginatoolowdeflection
coil current at the start of the scan.

The difference in the damping resistor current values
during scan and flyback have to be externally
compensated in order to achieve a short settling time.
For that purpose a compensation resistor R
with a zener diode is connected between pins OUTA
and INA(see Fig.4). The zener diode voltage value should
be equal to VP. The value of R

VFBV

– V

R

CMP

=

-----------------------------------------------------------------------------------------------------------­V

FBVloss FB()

loss FB()

– I

is calculated by:

CMP

–()R

× R

Z

D1

R

coil peak()

×–()R

where:

• V

is the voltage loss between pins VFBand OUTA

loss(FB)

at flyback

• R

is the deflection coil resistance

coil

• VZ is the voltage of zener diode D5.

in series

CMP

×

CV1

×

coil

M

Protection

The output circuit contains protection circuits for:

• Too high die temperature

• Overvoltage of output A.

1999 Nov 10 4

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit

TDA8357J

in LVDMOS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

P

V

FB

V

n

I

n

I

lu

V

es

P

tot

T

stg

T

amb

T

j

supply voltage − 18 V
flyback supply voltage − 68 V
DC voltage

pin OUTA note 1 − 68 V
pin OUTB − V
pins INA, INB, GUARD and FEEDB −0.5 V

V

P

V

P

DC current

pins OUTA and OUTB during scan (p-p) − 2.0 A
pins OUTA and OUTB at flyback (peak); t ≤ 1.5 ms −±1.2 A
pins INA, INB, GUARD and FEEDB −20 +20 mA

latch-up current current into any pin; pin voltage

− +200 mA

is 1.5 × VP; note 2
current out of any pin; pin voltage

is −1.5 × V

; note 2

P

−200 − mA

electrostatic handling voltage machine model; note 3 −300 +300 V

human body model; note 4 −2000 +2000 V
total power dissipation − 8W
storage temperature −55 +150 °C
ambient temperature −25 +75 °C
junction temperature note 5 − 150 °C

Notes

1. When the voltage at pin OUTA supersedes 70 V the circuit will limit the voltage.

2. At T

j(max)

.

3. Equivalent to 200 pF capacitance discharge through a 0 Ω resistor.

4. Equivalent to 100 pF capacitance discharge through a 1.5 kΩ resistor.

5. Internally limited by thermal protection at Tj≈ 170 °C.

THERMAL CHARACTERISTICS

In accordance with IEC 747-1.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

R
R

th(j-c)
th(j-a)

thermal resistance from junction to case −−6 K/W
thermal resistance from junction to ambient in free air −−65 K/W

1999 Nov 10 5

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit

TDA8357J

in LVDMOS

CHARACTERISTICS

VP= 12 V; VFB= 45 V; f
specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

P

V

FB

I

q(P)(av)

I

q(P)

I

q(FB)(av)

operating supply voltage 7.5 12 18 V
flyback supply voltage note 1 2V
average quiescent supply current during scan − 10 15 mA
quiescent supply current no signal; no load − 55 75 mA
average quiescent flyback supply

current

Inputs A and B

V

i(dif)(p-p)

differential input voltage
(peak-to-peak value)

V

I(bias)

I

I(bias)

input bias voltage note 2 100 880 1600 mV
input bias current − 25 35 µA

Outputs A and B

V

loss(1)

V

loss(2)

I

o(p-p)

voltage loss first scan part note 3

voltage loss second scan part note 4

output current (peak-to-peak value) −−2.0 A

LE linearity error I

V

offset

∆V

offset(T)

V

O

G

v(ol)

f

−3dB(h)

G

v

∆G

v(T)

offset voltage across RM; V

offset voltage variation with temperature across RM; V
DC output voltage V
open-loop voltage gain notes 7 and 8 − 60 − dB
high −3 dB cut-off frequency open-loop − 1 − kHz
voltage gain note 9 − 1 −
voltage gain variation with the

temperature

PSRR power supply rejection ratio note 10 80 90 − dB

= 50 Hz; V

vert

I(bias)

= 880 mV; T

=25°C; measured in test circuit of Fig.3; unless otherwise

amb

45 66 V

P

during scan −−10 mA

note 2 − 1000 1500 mV

I

= 0.7 A −−3.9 V

o

I

= 1.0 A −−5.5 V

o

= −0.7 A −−2.8 V

I

o

I

= −1.0 A −−4.0 V

o

= 2.0 A; notes 5 and 6

o(p-p)

adjacent blocks − 12%
non adjacent blocks − 13%

=0V

i(dif)

V

= 200 mV −−±15 mV

I(bias)

V

=1V −−±25 mV

I(bias)

=0V −−40 µV/K

i(dif)

=0V − 0.5VP− V

i(dif)

−−10

−4

K

−1

1999 Nov 10 6

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit

TDA8357J

in LVDMOS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Flyback switch

I

o(peak)

V

loss(FB)

Guard circuit

V

O(grd)

V

O(grd)(max)

I

O(grd)

Notes

1. To limit V
and VFB at the first part of the flyback.

2. Allowable input range: V

3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and
between pins OUTB and GND. Specified for Tj= 125 °C. The temperature coefficient for V

4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and
between pins OUTA and GND. Specified for Tj= 125 °C. The temperature coefficient for V

5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
blocks k. The 1st and 22nd blocks are ignored, while the voltage amplitudes are measured across RM, starting at
k = 2 and ending at k = 21, where Vkand V
V

avg

a) (adjacent blocks)

maximum (peak) output current t ≤ 1.5 ms −−±1.2 A
voltage loss at flyback note 11

I

= 0.7 A − 7.5 8.5 V

o

= 1.0 A − 89V

I

o

guard output voltage I
allowable guard voltage maximum leakage current

output current V

to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

OUTA

I(bias)+Vi(dif)

< 1600 mV and V

are the measured voltages of two successive blocks. V

k+1

= 100 µA 567V

O(grd)

−−18 V

I

=10µA

L(max)

= 0 V; not active −−10 µA

O(grd)

= 4.5 V; active 1 − 2.5 mA

V

O(grd)

I(bias)

− V

> 100 mV for each input.

i(dif)

is a positive value.

loss(1)

is a positive value.

loss(2)

are the minimum, maximum and average voltages respectively. The linearity errors are defined as:

V

–

kVk1+

=

LE

------------------------- ­V

avg

min,Vmax

and

–

V

b) (non adjacent blocks)

LE

maxVmin

=

-------------------------------

V

avg

6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage
dependent S-distortion in the input stage.

V

–

7.

G

vol()

OUTAVOUTB

=

-------------------------------------------­V

–

FEEDBVOUTB

8. Pin FEEDB not connected.

9.

10. V

V

G

=

--------------------------------------------

v

P(ripple)

–

FEEDBVOUTB

V

–

INAVINB

= 500 mV (RMS value); 50 Hz < f

< 1 kHz; measured across RM.

P(ripple)

11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.

1999 Nov 10 7

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

APPLICATION INFORMATION

handbook, full pagewidth

V

I(bias)

0

V

I(bias)

0

I

I(bias)

I

I(bias)

V

I

V

i(p-p)

i(dif)

i(p-p)

R

CV1

2.2 kΩ
(1%)

R

CV2

2.2 kΩ
(1%)

INA

INB

1

2

R

GRD

4.7 kΩ
GUARD

863

GUARD

CIRCUIT

D1

INPUT

AND

FEEDBACK

CIRCUIT

V

P

M2

M4

M1

M3

5

GND

V

FB

M5

D3

TDA8357J

D2

7

9

4

MGS806

OUTA

FEEDB

OUTB

TDA8357J

C1
100 nFC2100 nF

R

5.2 Ω

R

S

2.7 kΩ

C

M

10 nF

R

0.8 Ω

V

P

V

FB

L

M

Fig.3 Test diagram.

1999 Nov 10 8

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1999 Nov 10 9

, full pagewidth

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit

in LVDMOS

V

I(bias)

0

DEFLECTION

CONTROLLER

V

V

i(p-p)

2.2 nF

2.2 nF

i(p-p)

C6

C7

R

CV1

2.2 kΩ
(1%)

R

CV2

2.2 kΩ
(1%)

INA

INB

1

2

R

GRD

12 kΩ

D1

V

M2

M4

M1

M3

P

GUARD

863

GUARD

CIRCUIT

INPUT

AND

FEEDBACK

CIRCUIT

V

M5

D3

TDA8357J

FB

D2

7

9

4

OUTA

FEEDB

OUTB

C3

100

nF

D5

12 V

R

CMP

270 kΩ

R

2.7 kΩ

R

FB

10 Ω

C1

47 µF

(100 V)

R
330 Ω

S

D1

C4

100 nF

(2)

D4

deflection
coil

8.82 mH

7.9 Ω
(W66ESF)

R

M

1.5 Ω

VP = 11 V
V

= 29 V

fb

C2

220 µF

(25 V)

(1)

C

D

47 nF

(1)

R

D2

22 Ω

V

I(bias)

0

f

= 50 Hz; tFB= 640 µs; I

vert

(1) Optional, depending on the deflection coil impedance.
(2) Optional extended flash over protection; BYD33D or equivalent.

I(bias)

= 400 µA; I

i(dif)(peak)

= 494 µA; I

o(p-p)

5

GND

= 1.45 A.

Fig.4 Application diagram.

MGS807

TDA8357J

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

Supply voltage calculation

For calculating the minimum required supply voltage,
several specific application parameter values have to be
known. These parameters are the required
maximum (peak) deflection coil current I
parameters R

coil

and L

, and the measuring resistance

coil

coil(peak)

of RM. The required maximum (peak) deflection coil
current should also include the overscan.

The deflection coil resistance has to be multiplied with 1.2
in order to take account of hot conditions.

Chapter “Characteristics” supplies values for the voltage
losses of the vertical output stage. For the first part of the
scan the voltage loss is given by V

. For the second

loss(1)

part of the scan the voltage loss is given by V
The voltage drop across the deflection coil during scan is

determined by the coil impedance. For the first part of the
scan the inductive contribution and the ohmic contribution
to the total coil voltage drop are of opposite sign, while for
the second part of the scan the inductive part and the
ohmic part have the same sign.

, the coil

loss(2)

.

TDA8357J

The flyback supply voltage calculated this way is about
5% to 10% higher than required.

Calculation of the power dissipation of the vertical output stage

The IC total power dissipation is given by the formula:
P

tot=Psup

The power to be supplied is given by the formula:

P

sup

In this formula 0.3 [W] represents the average value of the
losses in the flyback supply.

The average external load power dissipation in the
deflection coil and the measuring resistor is given by the
formula:

P

L

− P

L

I

coil peak()

V

------------------------

P

I

()

coil peak()

------------------------------- -

2

2

3

R

coilRM

0.015 [A] 0.3 [W]+×+×=

V

P

+()×=

For the vertical frequency the maximum frequency
occurring must be applied to the calculations.

The required power supply voltage VP for the first part of
the scan is given by:

×=

R

V

P1()Icoil peak()

L

coil2Icoil peak()

+()

coilRM

f

vert max()

+××–

V

loss 1()

The required power supply voltage VPfor the second part
of the scan is given by:

V

P2()Icoil peak()

L

coil2Icoil peak()

R

+()×=

coilRM

f

vert max()

V

+××+

loss 2()

The minimum required supply voltage VP shall be the
highest of the two values V

P(1)

and V

. Spread in supply

P(2)

voltage and component values also has to be taken into
account.

Flyback supply voltage calculation

If the flyback time is known, the required flyback supply
voltage can be calculated by the simplified formula:

R

+

coilRM

V

FBIcoil p p–()

×=

-------------------------- -

–

1e

t–FBx⁄

where:

Example
Table 1 Application values

SYMBOL VALUE UNIT

I

coil(peak)

I

coil(p-p)

L

coil

R

coil

R

M

f

vert

t

FB

0.725 A

1.45 A

8.82 mH

7.9 Ω

1.5 Ω
50 Hz
640 µs

Table 2 Calculated values

SYMBOL VALUE UNIT

V

P

RM+R
t

vert

(hot) 11 Ω

coil

11 V

0.02 s
x 0.000802
V

FB

P

sup

P

L

P

tot

29 V

4.45 W

1.93 W

2.52 W

L

=

-------------------------- ­R

coilRM

coil

+

x

1999 Nov 10 10

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

Heatsink calculation

The value of the heatsink can be calculated in a standard
way with a method based on average temperatures.
The required thermal resistance of the heatsink is
determined by the maximum die temperature of 150 °C.

In general we recommend to design for an average die
temperature not exceeding 130 °C.

EXAMPLE
Measured or given values: P

Tj= 110 °C; R

th(j-c)

= 5 K/W; R

= 3 W; T

tot

th(c-h)

amb

= 2 K/W.

=40°C;

TDA8357J

The required heatsink thermal resistance is given by:

TjT

–

R

th h a–()

When we use the values given we find:

R

th h a–()

The heatsink temperature will be:
Th=T

amb

+(R

amb

----------------------- ­P

tot

110 40–

----------------------

3.0

th(h-a)

R

th j c–()

R

+()–=

th c h–()

52+()– 16 K/W==

× P

) =40+(3×16) = 90 °C

tot

1999 Nov 10 11

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

INTERNAL PIN CONFIGURATION

PIN SYMBOL EQUIVALENT CIRCUIT

1 INA

1

2 INB

2

300 Ω

300 Ω

TDA8357J

MBL100

3V

P

4 OUTB
5 GND
6V

FB

7 OUTA

MBL102

MGS805

6

3

7

4
5

1999 Nov 10 12

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

PIN SYMBOL EQUIVALENT CIRCUIT

8 GUARD

300 Ω

9 FEEDB

300 Ω

TDA8357J

8

MBL103

9

MBL101

1999 Nov 10 13

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

PACKAGE OUTLINE

DBS9P: plastic DIL-bent-SIL power package; 9 leads (lead length 12/11 mm); exposed die pad

non-concave

x

D

h

D

D

1

P

k

q

2

view B: mounting base side

A

2

E

h

TDA8357J

SOT523-1

q

1

E

19

Z

DIMENSIONS (mm are the original dimensions)

(2)

UNIT b

A

p

2

2.7

mm

Notes

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

2. Plastic surface within circle area D1 may protrude 0.04 mm maximum.

0.80

2.3

0.65

OUTLINE
VERSION

SOT523-1

cD

0.58

0.48

(1)

(2)

D

1

13.2

6.2

12.8

5.8

IEC JEDEC EIAJ

e

1

E

3.5

b

e

h

2.54

e

(1)

D

h

14.7

3.5

14.3

w M

p

0 10 mm5

scale

e

e

1

2

3.0

1.27

5.08 4.85

REFERENCES

2.0

12.4

11.0

B

q

L

3

L

2

L

L

Qc

m

L

Lq

11.4

10.0

L

L

m

2.8

Pk

3.4

3.1

1

2

3

6.7

4.5

5.5

3.7

e

2

QE

q

q

1

1.15

17.5

0.85

16.3

EUROPEAN

PROJECTION

1

v M

(1)

v

2

3.8

3.6

w

0.8

0.3

ISSUE DATE

98-11-12

x

0.02

Z

1.65

1.10

1999 Nov 10 14

Philips Semiconductors Preliminary specification

Full bridge vertical deflection output circuit
in LVDMOS

SOLDERING
Introduction to soldering through-hole mount

packages

This text gives a brief insight to wave, dip and manual
soldering.Amorein-depthaccountofsolderingICscanbe
found in our

Packages”

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

DBS, DIP, HDIP, SDIP, SIL suitable suitable

“Data Handbook IC26; Integrated Circuit

(document order number 9398 652 90011).

PACKAGE

Thetotalcontacttimeofsuccessive solder waves must not
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

SOLDERING METHOD

DIPPING WAVE

(1)

TDA8357J

). If the

stg(max)

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Nov 10 15

Philips Semiconductors – a w orldwide compan y

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Middle East: see Italy

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252042 KIEV, Tel. [phone], Fax. [phone]

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

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For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of anyquotationor contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545004/200/01/pp16 Date of release:1999 Nov 10 Document order number: 9397 75006196