Datasheet TDA8354Q Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA8354Q

Full bridge current driven vertical
deflection output circuit in LVDMOS

Product specification
Supersedes data of 1998 Sep 03
File under Integrated Circuits, IC02

2001 Jul 11

Philips Semiconductors Product specification

Full bridge current driven vertical

TDA8354Q

deflection output circuit in LVDMOS

FEATURES

• Few external components required

• High efficiency fully DC-coupled vertical output bridge

circuit

• Vertical flyback switch with short fall and rise times

• Built-in guard circuit

• Thermal protection circuit

• Improved EMC performance due to differential inputs

• A guard signal in zoom mode.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC supply

V

P

V

flb

I

q(av)

I

Vflb(av)

supply voltage 7.5 12 18 V
flyback supply voltage 2 × VP45 68 V
average quiescent supply current during scan − 10 15 mA
average flyback supply current during scan −−10 mA

Vertical circuit

I

o(p-p)

I

i(diff)(p-p)

output current (peak-to-peak value) −−3.2 A
input current (peak-to-peak value) at pin 11 or 12 − 500 600 µA

Flyback switch

I

o(Vflb)

peak output current t ≤ 1.5 ms −−±1.6 A

Thermal data (in accordance with IEC 60747-1)

T

stg

T

amb

T

vj

storage temperature −55 − +150 °C
ambient temperature −25 − +85 °C
virtual junction temperature −−150 °C

GENERAL DESCRIPTION

The TDA8354Q is a power circuit for use in 90° and 110°
colour deflection systems for 25 to 200 Hz field
frequencies, and for 4 : 3 and 16 : 9 picturetubes. The IC
contains a vertical deflection output circuit, operating as a
high efficiency class G system. The full bridge output
circuit allows DC coupling of the deflection coil in
combination with single positive supply voltages.

The IC is constructed in a Low Voltage DMOS (LVDMOS)
process that combines bipolar, CMOS and DMOS
devices. DMOS transistors are used in the output stage
because of the absence of second breakdown.

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

TDA8354Q DBS13P plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) SOT141-6

2001 Jul 11 2

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

BLOCK DIAGRAM

handbook, full pagewidth

V

o(guard)

14 710

GUARD

CIRCUIT

V

P(B)VP(A)

TDA8354Q

V

flb

M1

D2

I

i(diff)

I

i(bias)

I

i(diff)

I

i(diff)

I

i(bias)

I

i(diff)

I

i(pos)

I

i(neg)

12

FEEDBACK

11

INPUT/

D3

M2

M3

M4

M5

6

GNDAGNDB

COMPENSATION

CIRCUIT

TDA8354Q

8

9

V

o(A)

13

I

i(comp)

2

V

i(M)

3

V

i(con)

5

V

o(B)

MGL461

Fig.1 Block diagram.

2001 Jul 11 3

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

PINNING FUNCTIONAL DESCRIPTION

SYMBOL PIN DESCRIPTION

V

o(guard)

V

i(M)

V

i(con)

V

P(B)

V

o(B)

1 guard output voltage
2 input measuring resistor
3 input conversion resistor
4 supply voltage B

5 output voltage B
GNDB 6 ground B
V

flb

7 flyback supply voltage
GNDA 8 ground A
V

o(A)

V

P(A)

I

i(neg)

I

i(pos)

I

i(comp)

9 output voltage A

10 supply voltage A
11 input power stage (negative);

includes I

signal bias

i(sb)

12 input power stage (positive);

includes I

signal bias

i(sb)

13 input for damping resistor

compensation current

Vertical output stage

The vertical driver circuit has a bridge configuration, with
the deflection coil connected between the complimentary
driven output amplifiers. The differential input circuit is
current driven, and is specially designed for direct
connectiontodriver circuits delivering a differential current
signal. However, it is also suitable for single-ended input
signals.

The current to voltage conversion is done by the external
resistor (R

) connected between the output of the input

con

conversion stage and output stage B. This voltage is
compared with the output current through the deflection
coil, measured as a voltage across RM, which provides
internal feedback information. The relationship between
the differential input current and the output current is
defined by:

2 × I

i(diff)

× R

con=Icoil

× R

M

The output current is determined by the value of R
should measure 0.5 to 3.2 A (peak-to-peak value). The
allowable input current range is 50 to 800 µA for each
input.

TDA8354Q

con

and

handbook, halfpage

Thediehasbeen gluedto themetal blockof thepackage. Ifthe metal
block is not insulated from the heat sink, the heat sink may only be
connected directly to pin 6 and pin 8.

V

o(guard)

V

i(con)

V
V

GNDB

GNDA

V
V

I

i(neg)

I

i(pos)

I

i(comp)

V

P(B)

P(A)

i(M)

o(B)

V

o(A)

flb

1
2
3
4
5
6

TDA8354Q

7
8

9
10
11
12
13

MGL462

Flyback supply

The flyback voltage is determined by an additional supply
voltage V

. The principle of operating with two supply

flb

voltages(class G)makesitpossibletooptimizethesupply
voltage VP for the scan voltage and optimize the second
supply voltage V

for the flyback voltage. Using this

flb

method, very high efficiency is achieved. The supply
voltage V

is almost totally available as flyback voltage

flb

across the coil, because of the absence of a coupling
capacitor (which is not necessary as a result of the bridge
configuration). The very short rise and fall times of the
flyback switch are >400 V/µs.

Protection

The output circuit has protection circuits for:

• Too high die temperature

• Overvoltage of output stage A.

Fig.2 Pin configuration.

2001 Jul 11 4

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

Guard circuit

A guard circuit with output signal V
The guard circuit generates an active HIGH level during

the flyback period. The guard circuit is also activated for
one or more of the following conditions:

• When the thermal protection is activated (Tj≈ 170 °C)

• During short circuit of the output pins (pins 5 and 9)

to VP or ground

• During open coil

• During open loop

• During short circuit of the input pins to VP or ground.

An active HIGH level of the guard signal is also generated
for the following conditions:

• No drive signal

• Short circuit of the coil.

However, for these events, the signal is generated via an
internaltimercircuit.Theguardsignalsetviathistimerhas
a delay of ≈120 ms. The delay time is given by the lowest
applicable field frequency.

o(guard)

is provided.

TDA8354Q

Damping resistor compensation

For HF loop stability, a damping resistor is connected
across the deflection coil. There is a large difference in
currentinthedampingresistor Rpduringscanandflyback.
The resistor current is summed to the current in the
deflection coil via the measuring resistor RM, which results
in a too low current in the deflection coil at the start of the
scan.

To reach a short settling time, the difference in the current
during scan and flyback in the damping resistor can be
compensated by external means. For this purpose, a
resistor (R
the output of output stage A (pin 9) and pin 13 (I

For a more accurate calculation of R

R

comp

) of about 1 MΩ can be connected between

comp

, we have:

comp

V

– VP–()R

flbVloss

=

------------------------------------------------------------------------------­V

– ILRL×–()R

flbVloss

×R

×

p

con

×

M

comp

).

The guard signal can be used to blank the picture tube
screen and signal a fault condition. The guard signal can
also be used as a vertical synchronisation input pulse for
an On Screen Display (OSD) microcontroller.

2001 Jul 11 5

Philips Semiconductors Product specification

Full bridge current driven vertical

TDA8354Q

deflection output circuit in LVDMOS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DC supplies

V

P

V

flb

Vertical circuit

I

o(p-p)

V

o(A)

V

o(B)

I

1,2,3,11,12,13

V

1,2,3,11,12,13

Flyback switch

I

o(Vflb)

Thermal data (in accordance with IEC 60747-1)

T

stg

T

amb

T

vj

Miscellaneous

t

sc

I

i/o

V

ESD

supply voltage − 18 V
flyback supply voltage − 68 V

output current (peak-to-peak value) − 3.2 A
output voltage note 1 − 68 V
output voltage − V

P

current in or out of pins 1 to 3 and 11 to 13 −20 +20 mA
peak voltage on pins 1 to 3 and 11 to 13 −0.5 V

P

peak output current t ≤ 1.5 ms −±1.6 A

storage temperature −55 +150 °C
operating ambient temperature −25 +85 °C
virtual junction temperature note 2 − 150 °C

short-circuiting time note 3 − 1hr
current into any pin 1.5 × VP (ABSmax); note 4 −+200 mA
current out of any pin −1.5 × V

(ABSmax); note 4 −200 − mA

P

electrostatic handling machine model note 5 −±300 V
electrostatic handling human body model note 6 −±2000 V

V

V

Notes

1. When the pin voltage exceeds 70 V, the device functions asa power Zener diode, and limits the voltage.

2. Internally limited by thermal protection; switching point ≈ 170 °C.

3. Up to V

4. Latch-up test at T

=18V.

P

j(max)

.

5. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

6. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R
R

th(j-c)
th(j-a)

thermal resistance from junction to case 4 K/W
thermal resistance from junction to ambient in free air 40 K/W

2001 Jul 11 6

Philips Semiconductors Product specification

Full bridge current driven vertical

TDA8354Q

deflection output circuit in LVDMOS

CHARACTERISTICS

VP= 12 V; Vflb= 45 V; fi= 50 Hz; I
specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC supplies

V

P

V

flb

I

q(av)

I

q

I

Vflb(av)

operating supply voltage 7.5 − 18 V
flyback supply voltage 2 × VP− 68 V
average quiescent supply current during scan − 10 15 mA
quiescent supply current no signal; no load − 60 80 mA
average flyback supply current during scan −−10 mA

Output stages A and B

V

loss

total voltage loss from pin 10 to 9 and from
pin 5 to 6

total voltage loss from pin 4 to 5 and from
pin 9 to 8

total voltage loss from pin 10 to 9 and from
pin 5 to 6

total voltage loss from pin 4 to 5 and from
pin 9 to 8

LE linearity error

adjacent blocks Io= 3.2 A (p-p); note 2 − 0.5 2 %
not adjacent blocks I

V

o

V

offset

∆V

offset(T)

V

, V

o(A)

G

v(ol)

V

3to5/V2to5

f

res

G

i

∆G

T current gain drift as a function of temperature −−10

c

output voltage swing (flyback) V

 offset voltage across R

offset voltage as a function of temperature I
DC output voltage I

o(B)

open-loop voltage gain V
voltage ratio V

3to5/V2to5

frequency response (−3 dB) open loop − 1 − kHz
current gain (Io/I

i(diff)

PSRR power supply rejection ratio note 6 80 90 − dB

Input stage

I

i(sb)

I

i(diff)(p-p)

signal bias current − 330 500 µA
differential mode input current (peak-to-peak

value) pin 11 or 12
V
V

i(diff)
i(cm)

differential mode input voltage I

common mode input voltage I

i(bias)

= 330 µA; T

=25°C; measured in test circuit of Fig.3; unless otherwise

amb

Io= +1.6 A; note 1 −−6.0 V

I

= −1.6 A; note 1 −−4.8 V

o

I

= +1.1 A; note 1 −−4.2 V

o

I

= −1.1 A; note 1 −−3.4 V

o

= 3.2 A (p-p); note 2 − 0.5 3 %

o

o(A)

− V

o(B)

I

i(diff)

= 0.3 mA;

− 46 − V

Io= −1.6 A
I

M

9to5/V3to5

)=0

i(diff

I

= 500 µA −−15 mV

i(bias)

= 100 µA −−13 mV

I

i(bias)

=0 −−40 µV/K

i(diff)

= 0; note 3 − VP/2 − V

i(diff)

notes 4 and 5 − 60 − dB
note 4 − 0 − dB

) − 8000 −

note 7 − 500 600 µA

= 500 µA − 0.75 − V

i(diff)

= 330 µA 0.95 1.15 1.35 V

i(bias)

−4

/K

2001 Jul 11 7

Philips Semiconductors Product specification

Full bridge current driven vertical

TDA8354Q

deflection output circuit in LVDMOS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Flyback switch

I

flb

V

loss

Guard circuit

I

o(guard)

V

o(guard)

Notes

1. At Tj= 125 °C, the temperature coefficient of the V

2. The linearity error is measured for a linear input signal without S correction and is based on the ‘on screen’
measurement principle. This method is defined as follows. The output signal is divided into 22 successive equal time
parts. The 1st and 22nd parts are ignored. The remaining 20 parts form 10 successive blocks k, where a block
consists of two successive parts. The voltage amplitudes are measured across RM, starting at k = 1 and ending at
k = 10, where Vk and V
minimum, maximum and average voltages respectively. The linearity errors are defined as:

LE

3. V

o(A)+Vo(B)=VP

4. The V value within formulae relates to voltages at or between relative pin numbers, i.e. V
across pins 9 and 5, divided by voltage value across pins 3 and 5.

5. V

2to5

6. At V

7. I

i(abs)(max)

output peak current t < 1.5 ms −−±1.6 A
voltage loss (Vflb− V

output current not active;

output voltage on pin 1 I
allowable voltage on pin 1 maximum leakage

o(A)

)

I

= 1.6 A − 89V

o

= 1.1 A − 7.5 8.5 V

I

o

−−10 µA

V
active; V

o(guard)

=0V

o(guard)

= 4.5 V 1 − 2.5 mA

o(guard)

= 100 µA 5 67V

−−18 V

current = 10 µA

has a positive sign.

loss

are the measured voltages of two successive blocks. V

k+1

–

V

kVk + 1

= LE

-------------------------­V

× 100% (adjacent blocks) and × 100% (non-adjacent blocks).

av

V

maxVmin

=

----------------------------- ­V

–

av

min

, V

and Vav are the

max

. At the start of the scan, this equation is one diode voltage less.

9to5/V3to5

AC short circuited.

= 500 mV

ripple

= 800 µA and I

at VP; measured across RM; f

eff

i(abs)(min)

=50µA per pin.

= 50 Hz to 1 kHz.

ripple

= voltage value

2001 Jul 11 8

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

INTERNAL CIRCUITS
Table 1 Equivalent pin circuits

PIN SYMBOL EQUIVALENT CIRCUIT

1V

2V

o(guard)

i(M)

1

300 Ω

2

300 Ω

TDA8354Q

MGL472

MGL465

3V

4V
5V

i(con)

P(B)
o(B)

6 GNDB

3

300 Ω

MGL466

4

5

6

MGL467

2001 Jul 11 9

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

PIN SYMBOL EQUIVALENT CIRCUIT

7V
8 GNDA
9V

10 V

11 I

flb

o(A)
P(A)

i(neg)

10

9

8

7

MGL471

300 Ω

TDA8354Q

11

12 I

13 I

i(pos)

i(comp)

300 Ω

300 Ω

MGL470

12

MGL469

13

MGL468

2001 Jul 11 10

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

TEST AND APPLICATION INFORMATION

handbook, full pagewidth

R

guard

V

o(guard)

14 710

GUARD

I

i(diff)

I

i(bias)

I

i(diff)

I

i(bias)

I

i(pos)

CIRCUIT

12

V

P(B)VP(A)

M2

D3

TDA8354Q

V

P

V

flb

V

M1

flb

D2

V

o(A)

9

C3

C4

I

i(diff)

I

i(bias)

I

i(diff)

RM= 0.5 Ω;

= 1.2 kΩ;

R

con

= 3.2 Ω;

R

L

= 300 Ω;

R

p

= 650 kΩ;

R

comp

=5kΩ;

R

(guard)

= 2.2 kΩ;

R

s

C3 = C4 = 100 nF.

I

i(diff)

I

i(diff)

I

i(bias)

I

i(neg)

FEEDBACK

11

INPUT/

M3

M4

M5

6

GNDAGNDB

COMPENSATION

CIRCUIT

TDA8354Q

8

13

2

3

5

I

i(comp)

V

i(M)

V

i(con)

V

o(B)

MGL463

R

compRp

R

s

R

con

R

L

R

M

Fig.3 Test diagram.

2001 Jul 11 11

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

handbook, full pagewidth

R

guard

I

i(diff)

I

i(bias)

I

i(diff)

DEFLECTION
PROCESSOR

I

i(diff)

I

i(bias)

I

i(diff)

I

i(pos)

I

i(neg)

C6

C7

V

o(guard)

12

FEEDBACK

11

GUARD

CIRCUIT

INPUT/

V

P(B)VP(A)

14 710

D3

M2

M3

M4

M5

V

flb

M1

COMPENSATION

CIRCUIT

D2

TDA8354Q

C3 C1

V

o(A)

9

R

comp R

I

i(comp)

13

V

i(M)

2

V

i(con)

3

V

o(B)

5

C4 C2

R

s

R

con

TDA8354Q

V

P

V

flb

C*

coil

p

R

filter

R*

filter

M

6

Coil: AT6216/42;

= 12.1 V at fv= 50 Hz (vertical frame frequency); inclusive spread (absolute) and

V

P

temperature rise in the coil;

= 12.8 V at fv= 100 Hz (vertical frame frequency); inclusive spread (absolute) and

V

P

temperature rise in the coil;

= 2.33 A (peak-to-peak value);

I

o(p-p)

= 330 µA;

I

i(bias)

I

i(diff)(12-11)

V
t

flb

= 485 µA (peak value);

=45V;

flb

= 0.6 ms.

Fig.4 Application diagram.

2001 Jul 11 12

8

GNDAGNDB

RM= 0.5 Ω;
R

con

R

p

R

comp

R

(guard)

R

s

= 1.2 kΩ;

= 300 Ω;

= 650 kΩ;

=5kΩ;

= 2.2 kΩ.

MGL464

C1 = 47 µF; 100 V;
C2 = 220 µF; 25 V;
C3 = C4 = 100 nF;
C6 = C7 = 10 nF;

= 47 nF*;

C

filter

= 1.5 Ω*.

R

filter

* Values depend on coil
impedance.

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

PACKAGE OUTLINE

DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)

non-concave

x

D

E

h

d

A

D

h

view B: mounting base side

2

TDA8354Q

SOT141-6

j

113

e

Z

DIMENSIONS (mm are the original dimensions)

UNIT A e

mm

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

A2bpcD

17.0

4.6

4.4

0.75

0.60

15.5

1

e

(1)

deD

0.48

24.0

23.6

20.0

19.6

0.38

b

p

h

10 3.4

w M

0 5 10 mm

(1)

E

12.2

11.8

scale

1

1.7

e

5.08

B

E

A

L

3

L

E

2

h

6

Q

m

LL3m

3.4

12.4

3.1

11.0

2.4

1.6

c

e

2

4.3

Qj

2.1

1.8

v M

v

0.8

x

0.25w0.03

(1)

Z

2.00

1.45

OUTLINE
VERSION

SOT141-6

IEC JEDEC EIAJ

REFERENCES

2001 Jul 11 13

EUROPEAN

PROJECTION

ISSUE DATE

97-12-16
99-12-17

Philips Semiconductors Product specification

Full bridge current driven vertical
deflection output circuit in LVDMOS

SOLDERING
Introduction to soldering through-hole mount

packages

This text gives a brief insight to wave, dip and manual
soldering.Amorein-depthaccountofsolderingICscan be
found in our

Packages”

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

DBS, DIP, HDIP, SDIP, SIL suitable suitable

“Data Handbook IC26; Integrated Circuit

(document order number 9398 652 90011).

PACKAGE

Thetotalcontacttimeof successive solder waves must not
exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

SOLDERING METHOD

DIPPING WAVE

(1)

TDA8354Q

). If the

stg(max)

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

2001 Jul 11 14

Philips Semiconductors Product specification

Full bridge current driven vertical

TDA8354Q

deflection output circuit in LVDMOS

DATA SHEET STATUS

PRODUCT

DATA SHEET STATUS

Objective data Development This data sheet contains data from the objective specification for product

Preliminary data Qualification This data sheet contains data from the preliminary specification.

Product data Production This data sheet contains data from the product specification. Philips

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

(1)

STATUS

(2)

development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.

Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.

Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.

DEFINITIONS

DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyotherconditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarranty that such applications willbe
suitable for the specified use without further testing or
modification.

DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingor selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofanyof these products, conveys no licenceortitle
under any patent, copyright, or mask work right to these
products,andmakesnorepresentationsorwarrantiesthat
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

2001 Jul 11 15

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 7 - 9 Rue du Mont Valérien, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Hungary: Philips Hungary Ltd., H-1119 Budapest, Fehervari ut 84/A,

Tel: [phone], Fax: [phone]
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, SemiconductorsDivision,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPSSEMICONDUCTORS, Via Casati, 23 - 20052 MONZA(MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218,5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2001

Internet: http://www.semiconductors.philips.com

72

Printed in The Netherlands 753504/02/pp16 Date of release: 2001 Jul 11 Document order number: 9397 750 08034