Datasheet TDA8351-N5, TDA8351-N4 Datasheet (Philips)

DATA SH EET

Product specification
Supersedes data of January 1995
File under Integrated Circuits, IC02

1999 Sep 27

INTEGRATED CIRCUITS

TDA8351

DC-coupled vertical deflection
circuit

1999 Sep 27 2

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

FEATURES

• Few external components

• Highly efficient fully DC-coupled vertical output bridge

circuit

• Vertical flyback switch

• Guard circuit

• Protection against:

– short-circuit of the output pins (7 and 4)
– short-circuit of the output pins to V

P

• Temperature protection

• High EMC immunity because of common mode inputs

• A guard signal in zoom mode.

GENERAL DESCRIPTION

The TDA8351 is a power circuit for use in 90° and 110°
colour deflection systems for field frequencies of 50 to
120 Hz. The circuit provides a DC driven vertical
deflection output circuit, operating as a highly efficient
class G system.

QUICK REFERENCE DATA

Note

1. Aflybacksupplyvoltageof>50 Vupto60 Visallowed in application. A 220 nF capacitor in series with a 22 Ω resistor
(depending on I

O

and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of VFB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of
33 Ω (see application circuit Fig.6).

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC supply

V

P

supply voltage 9 − 25 V

I

q

quiescent supply current − 30 − mA

Vertical circuit

I

O(p-p)

output current

(peak-to-peak value)

−−3A

I

diff(p-p)

differential input current

(peak-to-peak value)

− 600 −µA

V

diff(p-p)

differential input voltage

(peak-to-peak value)

− 1.5 1.8 V

Flyback switch

I

M

peak output current −−±1.5 A

V

FB

flyback supply voltage −−50 V

note 1 −−60 V

Thermal data (in accordance with IEC 747-1)

T

stg

storage temperature −55 − +150 °C

T

amb

operating ambient temperature −25 − +75 °C

T

vj

virtual junction temperature −−150 °C

1999 Sep 27 3

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

TDA8351 SIL9P plastic single-in-line power package; 9 leads SOT131-2

Fig.1 Block diagram.

handbook, full pagewidth

MBC988

5

V

9

7

4

8

36

1

2

TDA8351

GND

CURRENT

SOURCE

V

I(fb)

V

O(A)

+V

O(A)

V

O(B)

−V

O(B)

V

O(guard)

V

P

+V

P

+V

P

+V

P

−I

S

−I

T

+I

S

+I

T

V

FB

I

drive(pos)

I

drive(neg)

1999 Sep 27 4

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

PINNING FUNCTIONAL DESCRIPTION

The vertical driver circuit is a bridge configuration. The
deflectioncoilisconnectedbetweentheoutputamplifiers,
which are driven in opposite phase. An external resistor
(RM) connected in series with the deflection coil provides
internalfeedback information. The differential input circuit
is voltage driven. The input circuit has been adapted to
enable it to be used with the TDA9150, TDA9151B,
TDA9160A, TDA9162, TDA8366 and TDA8376 which
deliver symmetrical current signals. An external resistor
(R

CON

) connected between the differential input
determines the output current through the deflection coil.
Therelationship between the differential input current and
the output current is defined by: I

diff

× R

CON=Icoil

× RM.
The output current is adjustable from 0.5 A (p-p) to 3 A
(p-p) by varying RM. The maximum input differential
voltage is 1.8 V. In the application it is recommended that
V

diff

= 1.5 V (typ). This is recommended because of the
spread of input current and the spread in the value of
R

CON

.

The flyback voltage is determined by an additional supply
voltage VFB. The principle of operating with two supply
voltages (class G) makes it possible to fix the supply
voltage VPoptimum for the scan voltage and the second
supplyvoltageVFBoptimumfortheflyback voltage. Using
this method, very high efficiency is achieved.

The supply voltage VFB is almost totally available as
flyback voltage across the coil, this being possible due to
the absence of a decoupling capacitor (not necessary,
due to the bridge configuration). Built-in protections are:

• thermal protection

• short-circuit protection of the output pins (pins 4 and 7)

• short-circuit protection of the output pins to VP.

A guard circuit V

O(guard)

is provided. The guard circuit is

activated at the following conditions:

• during flyback

• during short-circuit of the coil and during short-circuit of

the output pins (pins 4 and 7) to VP or ground

• during open loop

• when the thermal protection is activated.

This signal can be used for blanking the picture tube
screen.

SYMBOL PIN DESCRIPTION

I

drive(pos)

1 input power-stage (positive);

includes I

I(sb)

signal bias

I

drive(neg)

2 input power-stage (negative);

includes I

I(sb)

signal bias

V

P

3 operating supply voltage

V

O(B)

4 output voltage B
GND 5 ground
V

FB

6 input flyback supply voltage
V

O(A)

7 output voltage A
V

O(guard)

8 guard output voltage
V

I(fb)

9 input feedback voltage

Fig.2 Pin configuration.

Metal block connected to substrate pin 5.
Metal on back.

handbook, 2 columns

1
2
3
4
5
6
7
8
9

TDA8351

I

drive(pos)

V

I(fb)

V

P

V

O(B)
GND

V

FB

V

O(A)

V

O(guard)

I

drive(neg)

MBC989

1999 Sep 27 5

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Aflybacksupplyvoltageof>50 Vupto60 Visallowed in application. A 220 nF capacitor in series with a 22 Ω resistor
(depending on I

O

and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of VFB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of
33 Ω (see application circuit Fig.6).

2. IO maximum determined by current protection.

3. Up to VP=18V.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DC supply

V

P

supply voltage non-operating − 40 V

− 25 V

V

FB

flyback supply voltage − 50 V

note 1 − 60 V

Vertical circuit

I

O(p-p)

output current (peak-to-peak value) note 2 − 3A

V

O(A)

output voltage (pin 7) − 52 V

note 1 − 62 V

Flyback switch

I

M

peak output current −±1.5 A

Thermal data (in accordance with IEC 747-1)

T

stg

storage temperature −55 +150 °C

T

amb

operating ambient temperature −25 +75 °C

T

vj

virtual junction temperature − 150 °C

R

th vj-c

resistance vj-case − 4 K/W

R

th vj-a

resistance vj-ambient in free air − 40 K/W

t

sc

short-circuiting time note 3 − 1hr

1999 Sep 27 6

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

CHARACTERISTICS

VP= 17.5 V; T

amb

=25°C; VFB= 45 V; fi= 50 Hz; I

I(sb)

= 400 µA; measured in test circuit of Fig.3; unless otherwise

specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC supply

V

P

operating supply voltage 9.0 − 25 V

V

FB

flyback supply voltage V

P

− 50 V

note 1 V

P

− 60 V

I

P

supply current no signal; no load − 30 55 mA

Vertical circuit

V

O

output voltage swing (scan) I

diff

= 0.6 mA (p-p);

V

diff

= 1.8 V (p-p);

IO= 3 A (p-p)

19.8 −−V

LE linearity error I

O

= 3 A (p-p); note 2 − 13%

I

O

= 50 mA (p-p); note 2 − 13%

V

O

output voltage swing (flyback)
V

O(A)

− V

O(B)

I

diff

= 0.3 mA;

IO= 1.5 A

− 39 − V

V

DF

forward voltage of the internal
efficiency diode (V

O(A)

− VFB)

IO= −1.5 A;
I

diff

= 0.3 mA

−−1.5 V

|I

os

| output offset current I

diff

=0;

I

I(sb)

=50to500µA

−−30 mA

|V

os

| offset voltage at the input of the

feedback amplifier (V

I(fb)

− V

O(B)

)

I

diff

=0;

I

I(sb)

=50to500µA

−−18 mV

∆V

os

T output offset voltage as a function

of temperature

I

diff

=0 −−72 µV/K

V

O(A)

DC output voltage I

diff

= 0; note 3 − 8.0 − V

G

vo

open-loop voltage gain (V

7-4/V1-2

) notes 4 and 5 − 80 − dB

open loop voltage gain
(V

7-4/V9-4

; V

1-2

=0)

note 4 − 80 − dB

V

R

voltage ratio V

1-2/V9-4

− 0 − dB

f

res

frequency response (−3 dB) open loop; note 6 − 40 − Hz

G

I

current gain (IO/I

diff

) − 5000 −

∆G

c

T current gain drift as a function of

temperature

−−10

−4

K

I

I(sb)

signal bias current 50 400 500 µA

I

FB

flyback supply current during scan −−100 µA
PSRR power supply ripple rejection note 7 − 80 − dB
V

I(DC)

DC input voltage − 2.7 − V
V

I(CM)

common mode input voltage I

I(sb)

=0 0 − 1.6 V

I

bias

input bias current I

I(sb)

=0 − 0.1 0.5 µA

I

O(CM)

common mode output current ∆I

I(sb)

= 300 µA (p-p);

fi= 50 Hz; I

diff

=0

− 0.2 − mA

1999 Sep 27 7

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

Notes

1. Aflybacksupplyvoltageof>50 Vupto60 Visallowed in application. A 220 nF capacitor in series with a 22 Ω resistor
(dependent on IO and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of VFB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of
33 Ω (see application circuit Fig.6).

2. The linearity error is measured without S-correction and based on the same measurement principle as performed on
the screen. The measuring method is as follows:
Divide the output signal I4− I7(VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two
succeedingparts called one block starting with part 2 and 3(block 1)and ending with part 20 and 21 (block 10). Thus
part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and linearity error for not
adjacent blocks (LENAB) are given below:

;

3. Referenced to V

P

.

4. TheV values within formulae relate to voltages ator across relative pin numbers, i.e. V

7-4/V1-2

= voltagevalue across

pins 7 and 4 divided by voltage value across pins 1 and 2.

5. V

9-4

AC short-circuited.

6. Frequency response V

7-4/V9-4

is equal to frequency response V

7-4/V1-2

.

7. At V

(ripple)

= 500 mV eff; measured across RM; fi= 50 Hz.

Guard circuit

I

O

output current not active;

V

O(guard)

=0V

−−50 µA

active; V

O(guard)

= 3.6 V 1 − 2.5 mA

V

O(guard)

output voltage on pin 8 IO= 100 µA 4.6 − 5.5 V
allowable voltage on pin 8 maximum leakage

current = 10 µA;

−−40 V

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LEAB

a

kak1+()

–

a

avg

----------------------------

= LENAB

a

maxamin

–

a

avg

----------------------------- -

=

1999 Sep 27 8

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

Fig.3 Test diagram.

handbook, full pagewidth

MBC987

5

V

FEEDBACK

INPUT

9

7

4

3

86

1

2

signal

bias

signal

bias

TDA8351

GND

2.2 kΩ

V

O(guard)

RM = 0.7 Ω

R = 6.0 Ω

V

P

V

FB

I

diff

R

CON

3 kΩ

I

drive(pos)

I

drive(neg)

I

I(sb)

I

I(sb)

Fig.4 Input currents.

handbook, full pagewidth

MLA776

I

diff

CON

R

1

2

I

sb

I

diff

I

diff

I

sb

I

sb

I

sb

0

I

diff

I

sb

0

I

diff

I

sb

TDA8351

1999 Sep 27 9

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

APPLICATION INFORMATION

Fig.5 Application diagram.

VP= 14 V; I

O(p-p)

= 2.14 A; I

I(sb)

= 400 µA; I

diff(p-p)

= 500 µA; VFB= 42 V; tFB= 0.6 ms.

handbook, full pagewidth

MBC986

5

V

FEEDBACK

INPUT

9

7

4

deflection coil
AT6005/31
L = 8.63 mH
R = 5.0 Ω

3

86

1

2

signal

bias

signal

bias

TDA8351

GND

100

nF

V

I(fb)

V

O(A)

V

O(B)

I

(coil)

V

O(guard)

RM = 0.7 Ω

V

P

V

FB

I

diff

R

CON

3 kΩ

I

drive(pos)

I

drive(neg)

I

I(sb)

I

I(sb)

100
nF

10
nF

10
µF

100

µF

1999 Sep 27 10

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

Fig.6 Application circuit; 50 V ≤ VFB≤ 60 V.

VP= 14 V; I

O(p-p)

= 2.14 A; I

I(sb)

= 400 µA; I

diff(p-p)

= 500 µA; VFB= 60 V; tFB= 0.4 ms.

handbook, full pagewidth

MLA777

5

V

FEEDBACK

INPUT

9

7

4

deflection coil
AT6005/31
L = 8.63 mH
R = 5.0 Ω

3

86

1

2

signal

bias

signal

bias

TDA8351

GND

220

nF

20 Ω

100
nF

100

nF

30

V

I(fb)

V

O(A)

V

O(B)

I

(coil)

V

O(guard)

RM = 0.7 Ω

V

P

V

FB

I

diff

R

CON

3 kΩ

I

drive(pos)

I

drive(neg)

I

I(sb)

I

I(sb)

10
nF

10
µF

100
µF

1999 Sep 27 11

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

PACKAGE OUTLINE

UNIT A

b

max.

b

p2

cD

(1)

E

(1)

Z

(1)

deD

h

Lj

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

4.6

4.2

1.1

0.75

0.60

0.48

0.38

24.0

23.6

20.0

19.6

10 2.54

12.2

11.8

3.4

3.1

A

max.

1

2.0

E

h

6

2.00

1.45

2.1

1.8

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

17.2

16.5

SOT131-2

92-11-17
95-03-11

0 5 10 mm

scale

Q

0.25w0.03

x

D

L

A

E

c

A

2

Q

w M

b

p

d

D

Z

e

x

h

19

E

h

non-concave

seating plane

1

b

j

SIL9P: plastic single in-line power package; 9 leads

SOT131-2

view B: mounting base side

B

1999 Sep 27 12

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

SOLDERING
Introduction to soldering through-hole mount

packages

This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can
be found in our

“Data Handbook IC26; Integrated Circuit

Packages”

(document order number 9398 652 90011).

Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.

Soldering by dipping or by solder wave

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.

The total contact time of successive solder waves must
not exceed 5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg(max)

). If the
printed-circuit board has been pre-heated, forced cooling
maybe necessary immediately after soldering to keep the
temperature within the permissible limit.

Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

Suitability of through-hole mount IC packages for dipping and wave soldering methods

Note

1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PACKAGE

SOLDERING METHOD

DIPPING WAVE

DBS, DIP, HDIP, SDIP, SIL suitable suitable

(1)

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

1999 Sep 27 13

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

NOTES

1999 Sep 27 14

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

NOTES

1999 Sep 27 15

Philips Semiconductors Product specification

DC-coupled vertical deflection circuit TDA8351

NOTES

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

1999

68

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Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

Printed in The Netherlands 545004/02/pp16 Date of release: 1999 Sep 27 Document order number: 9397 750 06203